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Manufacturing considerations for VLSI interconnect systems
ELSEVIER
Materials Chemistry and Physics 41 ( 1995) 167-172
Manufacturing considerations for VLSI interconnect systems Michael E. Thomas National Semiconductor
Corporation,
Fairchild Research Center, 2900 Semiconductor Drive, MS E-100, Santa Clara, CA 95052, USA
Received 2 March 1995
Abstract In the next decade, it is expected that integrated circuits having 5-7 levels of metal will be common in VLSI technologies with linear interconnect densities approaching 200 m/cm* level. Multilevel interconnect technology needs are presently generating processing and
structural issues which will dominate the future manufacturing yield and performance of these integrated circuits. The challenge of meeting these needs will require a concurrent improvement in design and manufacturing simplicity and cleanliness. This presentation will examine the architectural needs of future multilevel metal systems in light of the lithography, materials and electrical requirements which must be addressed by the interconnect
engineer. A comparison
of interconnect
systems based on different conductor materials will be presented.
Keywords: VLSI interconnect systems; Manufacture
1. Introduction
1Device Technology lUemory[
One of the greatest challenges in the production of verylarge-scale integrated (VLSI) electronic circuits lies in the ability of engineers and scientists to use ultra fine conducting metallic wires to link hundreds of millions of transistors on a postage stamp sized sliver of silicon. Because of routing limitations in a single level of conducting metal wire, one’s ability to obtain high degrees of connectivity between these millions of electrically active transistors cannot be achieved without multilevel metal (MLM) interconnect. In the next decade, it is projected that up to 7 levels of on-chip interconnect wiring with feature sizes approaching 0.12 pm will be required to utilize all of the active devices built into the Si substrate. At present, there are two technology paths involving memory and logic devices which have different interconnect requirements. Fig. 1 summarizes the interconnect needs for each technology. In order to optimize the resolution from production lithography tools, a high degree of wafer surface flatness at all interconnect levels must be established prior to delineating and etching high resolution interconnect patterns. This flatness (which is expected to be on the order of = 200 nm) facilitates tighter feature size control since a smaller depth of focus (DOF) must be employed. Subsequent etch process margins are also improved, since metal films which used to run over the sidewalls of rough topographical features and look thicker to anisotropic etches are essentially eliminated. 0254-0X34/95/$09.50 0 1995 Elsevier Science S.A. All rights reserved SSDIO254-0584(95)01510-2
r
* Periodic
Designs
. Tight Pitches / Density Optimized - More Defect Sensitive in Any Single Level
Considerations pPsI Logic
-Random mEmploy
Designs
Looser Piches More Layout Latitude
Sensitivity / Level Less than for Memory
*Five
- Easier
* More Difficult
*Employs
Redundancy
I
*Defect
. Two to Three Metal Layers Planatfzation
Devices
to Seven Metal Layen
- Limited
Planaffzation
Redundancy
* More Reliability
Issues
Fig. 1. Interconnect needs for memory and logic devices.
Due to memory’s periodic design and optimized density, planarization requirements for this technology can probably still be met, for the foreseeable future, by spin-on glass dielectrics (SOGs) used in conjunction with CVD SiOZ films. Since these materials facilitate good levelling of features having spacings of up to 5 pm, the above dielectrics or the incorporation of new ECR CVD dielectrics can be employed and provide good levelling in the memory cell array. Logic devices are not so fortunate, since they typically possess a myriad of functions which employ the Si real estate in a less efficient manner. In many cases, since interconnect features are laid out using auto-routing techniques which attempt to optimize wiring delay, power and interconnectivity a wide variety of feature sizes are generated which range over hundreds of microns. These device characteristics make it necessary to use many more levels of metal for logic versus
168
M.E. Thomas/Materials Chemistry and Physics 41 (1995) 167-172
2. Interconnect manufacturing
2. Schematic per 1994).
Fig.
cross section of a typical logic interconnect
system (as
less but denser levels for memory. These characteristic requirements of logic devices having a wide range of interconnect features makes the attainment of global planarization much more difficult. This need has ushered in the use of them-mechanical planarization (CMP) techniques, in which a slurry and porous polymeric pad material are placed in contact with the wafer and are used to globally level dielectric surfaces [ 1,2]. In the past decade, memory technology was the major market driver and 2 levels of metal were common among memory and 3 levels of metal for logic devices. At present, microprocessors have become the major market driver and some present designs use 5 levels of metal to connect all of the functions needed on chip to provide more computational horsepower. This need may severely impact device yield and reliability due to the numerous thermal excursions to temperatures approaching 400 “C, the metal levels will see during subsequent processing. The functional yield per level of interconnect for memory is lower than logic devices, however, there are less metal levels used in memory. Memory because of its repetitive nature can implement redundancy to recover from functional defects. This is a luxury that logic has a more difficult time utilizing. Fig. 2 shows a schematic cross section of the interconnect system which is in wide use today for logic. The system employs metals such as TiN and Ti which perform a number of functions. The Ti acts to reduce the contact/via resistance between the Si device and subsequent metal levels or between different metal levels. The TIN acts as a diffusion and nucleation barrier for CVD W plug deposition and is also used in stacked Al alloy films to provide strength to subsequently patterned interconnect lines. When this film is placed on top of the Al alloy, the main conductor of the interconnect system, it is also used as an anti-reflective coating for lithography and hillock suppression layer. At present, the W plugs are employed in the technology since CVD W filling of contacts and vias have matured at a much faster pace than other metal fill technologies. This situation is expected to change in the near future. The following sections will focus on a number of generic process issues, for logic devices, and address these described issues in more detail.
technological barriers
There are a number of key interconnect issues which could critically hinder technological development and manufacturability which are summarized below and are as follows: ( 1) yield (2) process simplicity (3) reliability (4) performance The remainder of this paper will address issues in each of these areas to identify where intensive R&D will be required.
3. Interconnect yield Back end of line (BEOL) processing which involves the generation of interconnect from the device contact level will continue to be a major functional yield detractor for submicron interconnect fabrication. The total functional yield of the interconnect system can be described using the following expression: YTOT
FUN =
YFE
n
yINT
(1)
I
where Yror roN = the total functional yield, YE = the total front end yield, II YINT= the total yield of all interconnect I levels. Since the interconnect metallization is not as amenable to chemical cleaning as previously processed single crystalline and polycrystalline Si, a larger number of defects are expected to be retained in these layers leading to device failure. At present, yield loss associated with interconnect processing can be substantial. It is imperative that good defect control is exercised over these layers. This situation will not go away and likely become worse with the ever increasing need for more metal levels. As metal features approach 0.25 pm, it is the opinion of the author that optical defect detection techniques will become exceedingly more expensive and difficult to apply and the uncertainty of differentiating between particulates and defects will increase. (In this discussion, it should be pointed out that particulates and defects are not the same since, for example, a defect caused by the flow of resist over a particle could be much larger than the particle’s physical dimensions causing it.) In order to more accurately assess interconnect defects associated with various processes, electrical test techniques will have to be employed and find greater utility. It is critical that the present method of using single valued numbers to describe defect levels be replaced with a functional defect description which is independent of device layout. This can be accomplished by generating a previously described defect distribution function,f(R) [ 3,4]. Past studies [S] have described the methodology which can be used to obtain the defect distribution function f(R) from defect histograms. In order to perform yield estimation,
M.E. Thomas/Materials
27
IL-
Fig. 3. General
ex& -jA(RYtR)
characteristics
(a)
-
(b)
fi(R) n
of the defect distribution
A(R) \
function, f(R),
and the critical
area, A(R),
as a function
of defect radius R. Y,N7=
W.
the critical area A(R) [6,7] of the layout must also be extracted to help accurately assess the yield impact attributed to an interconnect level. The critical area is the fraction of the total die area which is susceptible to a defect of size R. The critical area has the property of increasing with the radius of the defects present in the system, where the defects become large enough to effectively become the whole area of the die. The general characteristics of both the defect distribution and the critical area as a function of the defect radius are shown in Fig. 3. (The defect distribution function will have different characteristics for different facilities and must be evaluated individually.) If we take the product of these two curves and integrate them together the yield for any metal level i can be estimated using the following modified Poisson equation: Y,=exp(
169
Chemistry and Physics 41 (1995) 167-l 72
A(R)f(R)
dR)
(2)
I
where: Yi= yield of the ith level of metal, A(R) = the critical area function,f(R) = the defect distribution function. Fig. 3 can be used to qualitatively demonstrate how one can make tradeoffs in the design and/or manufacturing areas to enhance device yield. Fig. 3(a) addresses the influence that changes in manufacturing cleanliness have on the functional yield of an interconnect level. If the layout of the interconnect level is not changed, which fixes the critical area function A(R), it can be seen that by shifting the magnitude of defect distribution downward fromf, (R) tof2( R) the value of the integration described in relation (2) also decreases. This change would positively impact the yield since the value of the integral is exponentially related to it. Fig. 3 (b) shows the impact of the modifying the layout, where the critical area change from A1 (R) to A,(R) reduces the value of the integral and positively impacts the yield. These qualitatively obvious results explain how tradeoff can be made in manufacturing or design to optimize yield. Presently studies are underway to see if the device interconnect yields can be quantitatively captured with high degrees of accuracy using this approach.
4. Interconnect process simplicity In the past decade, interconnect processing has evolved from what was once a conceptually simple methodology to one having great complexity. This evolution occurred due to an order of magnitude reduction in the interconnect feature size and the drive to implement more functions on a monolithic integrated circuit. This development has placed much greater demands on the mechanical and electrical performance of the materials. Due to these demands, new technologies were adopted, such as: ( 1) anisotropic dry etching of interconnect stacks; (2) generation of complicated keyhole free interlevel dielectrics ( ILDs) ; (3) straight walled contact and vias; (4) metal deposition technologies having high conformality and the ability to fill deep vias and contacts; (5) high temperature refractory metals which act as barriers, nucleation layers, contact formers and anti-reflection coatings for optical lithography; (6) multilayer interconnect stacks having better mechanical and electromigration stability; (7) them-mechanical planarization of ILD surfaces and metals. With the greater offered functional complexity, the need for many levels of metallization has made the generation and filling of vias between levels of metal a key problem to address for high density circuits. It was unfortunate that a mature Al alloy deposition process capable of filling vias was not developed before that of CVD W. If Al via filling processes had been developed, a more natural evolution of interconnect technology would have occurred and the complicated structure shown in Fig. 2 would not have been adopted. Recent studies are exploring the use of lower resistivity metals such as CVD Cu and Al and physically vapor deposited (PVD) Al, which will provide via/contact filling of features having aspect ratios greater than 5: 1 and widths near 100 nm. The generation of these technologies will be
170
M.E. Thomas/Materials
Chemistry and Physics 41 (1995) 167-l 72
Interconnect Via Processes qlllil%~r~~i,l~ll~
1) ILD Deposition 2 1 SOG Dep 3 SOG Et&back 2 1 kL;AP Deposition 6) Via Mask 7) Via Etch i ;;; ~rt$r
Dep
101 ’ W EtchbacR 11j Layered Al Dep 121 Pattern Al 13 Etch Al
1) ILD Deposition 2 1 SCG Dep 3 SOG Etchback 2 1 ILLFAP Deposition 6) Via Mask 7) Via Etch 6 Layered Al Dep 9 Pattern Al 101 Etch Al
fTqq
1) SOD Dep 2 1 ViaMask 3 Via Etch 5 1Layered 4 Pattern Al Al Dep 6) Etch Al 2 HIGH T STEPS
4 HIGH T STEPS
6 HIGH T STEPS
Fig. 4. Potential manufacturing
pathways
for multilevel interconnect.
expected to supplant the present interconnect system which employs CVD W plugs. An emphasis has also been placed on the development of organic dielectrics which can be used as replacements for CVD deposited SiOp films. If these films can be proven and integrated into a full process flow with new plug filling metallization deposition technologies, even greater reductions in process complexity can be achieved. This will occur since the application of the films will be substantially easier (spinning) and faster than CVD deposition. The interlevel dielectric (ILD) process will involve only a single layer of material as opposed to 3-layer dielectric stacks which are presently used consisting of SiO,/SOG/ SiOZ. Fig. 4 shows two potential manufacturing pathways which will be adopted once mature via fill techniques, new dielectrics and integrated process flows are developed. When a generalized analysis is performed of the interconnect processes presently used versus those proposed, an estimate can be made of the simplification afforded by the adoption of the new technologies. Fig. 5 is a schematic which has extracted the Al via fill technology path from Fig. 4. In this figure, the major process steps required to generate a via and interconnect level using present and proposed interconnect formation techniques were estimated. The estimates were based on identifying major pieces of equipment that a wafer would have to be passed between and processed through to complete the fabrication. (The analysis of the vias process was performed since the contact level involves only one of several levels of metal in the device.) From this analysis, it was observed that a great amount of process overhead presently exists in the generation of the W plugs and ILD layers. If an Al via fill process can be employed to replace the CVD W plug formation, a better than 20% decrease in process complexity can be achieved. By replacing the layered silicate/SOGinsulators with a single organic based dielectric, the overall process complexity can be reduced by 50%. In the analysis for the contact formation process, the reduction in complexity is less since there are a number of metals common to the present interconnect which
* Possible to Cut Ma/x Processes by roughly50% using good material design
Fig. 5. Schematic of reduction in the number of steps in a via process using Al plugs vs. CVD W plugs.
are required with high temperature processes to make good electrical contacts to silicon. From a cost point of view, there is also a notable cost advantage of replacing WF6 with a less expensive Al deposition source. In performing this analysis where Cu is used as the conductor system, the picture is less clear about reductions in process complexity since: (i) Cu requires barriers to inhibit its diffusion and (ii) it is extremely difficult to plasma etch. These two issues have forced technologists to implement an approach where the Cu is deposited into barrier metal lined channels of dielectric. The Cu is then removed by CMP processing leaving the Cu in the channels (Damascene process [ 81) . Although this process is structurally very attractive, since it leaves a top metal surface which is planar with its ILD layer, a large number of process steps are required to generate a level of wiring. A large amount of work is presently being focused on Cu based interconnect systems to prove its viability in large integrated circuits and simplify its process integration. Unless attractive Cu alternatives are developed, Al based interconnects with low dielectric constant ILDs will probably be the future system of choice supplanting W plug based technologies.
5. Interconnect reliability In light of future interconnect requirements, reliability will become an ever increasing concern. The higher density of wiring which approximately doubles with every generation of technology introduces greater potential for device failure. Besides increased interconnect length, the reduction in wire cross section makes it more susceptible to failure by void formation due to stress migration (SM) and electromigration (EM). Since the demands for more functional device density have imposed the need for many levels of wiring, the first levels of interconnect experience a number of large thermal cycles between room temperature and roughly 400 “C. Fig. 6
171
M.E. Thomas /Materials Chemistry and Physics 41(1995) 167-172
1 AEUABIUTY
ISSUES - STRESS HYSTERESIS
. WANT TO STAY IN THE TENSILE REGIME FOR SM CHARACTERIZATION ED ‘KUOS . ACCELERATED TESTS FOR EM SHOULD MEASURE STRESS DURING TESTING
L
I
I
I\
COOLING
COMPRESSION
Fig. 6. Schematic representation of a typical stress hysteresis loop for Al alloys.
shows a schematic representation of the stress which an interconnect sees as it is thermally cycled. At room temperature, the interconnects experience a high degree of tensile stress which is conductive to stress void growth. Upon heating to elevated temperatures, the stress that the Al alloy experiences changes from a tensile to compressive state due its higher expansion rate compared to SiOZ and silicon. Although voids cannot form in compression, Al does have the potential of cracking interlevel dielectrics and extruding through them. In light of these concerns, it is evident that a reduction in total number of thermal cycles seen by the wiring can only help to ensure greater future system reliability. The attainment of a more simple process, which was previously described, should support this need and make it possible to build a greater degree of interconnect integrity into the system. In referring to Fig. 5, it can be seen that the number of thermal cycles per level of processed interconnect can be substantially reduced (in this case by 66%) by simplifying the metal and dielectric processing. The electromigration resistance of the interconnect will depend on its physical integrity at the completion of processing and the crystallographic state of the metallization.
6. Performance
issues
The concurrent need for higher frequency operation and greater device density is contrary to simpler processing and reliability. These future requirements will become critical as electronic systems, operating at multihundred megahertz frequencies become available. As faster electrical pulses are driven along an interconnect in excess of 100 MHz, electromagnetic coupling can impose substantial unwanted voltages on neighboring undriven lines. This situation has been previously modelled [9] for two adjacent interconnect lines shown in Fig. 7. Suppose two interconnects are placed in close proximity (i.e., 1 pm space) at 2 pm above a ground plane for a length of 1 mm and one sees a rise time pulse of = 20 ps while the other is attached to ground. (The dense array of underlying wiring can look like a ground plane.) During the rise and fall of the waveform on the driven line,
a substantial unwanted voltage ( = 50% of V,) will be generated on the undriven line. This situation becomes substantially worse as the spacing between the wires is decreased. At 0.5 pm spacing, this crosstalk would rise to approximately 70% of the total voltage applied to the driven line. In addition we make smaller lines more resistive, there is a larger RC delay associated with the decay of the unwanted signal. A number of approaches can be implemented to alleviate these problems which involve: ( 1) reducing the common length of the two interconnects (i.e., more levels of wiring, smart routing) ; (2) increasing the wiring pitch; (3) using more conductive metals so that the height of the interconnect and overall sidewall capacitance can be reduced; (4) lowering the dielectric constant of the insulation between the wires in a level; (5) providing electrical isolation between the wires. The first two approaches are solutions which can be provided by compromises in design. By moving lines farther away from one another this problem can be relaxed. However, this solution typically increases the size of the Si die. This resulting increase can lead to a smaller number of total die per wafer which may adversely impact system cost. Since the coupling is also directly proportional to the length along which interconnect traces are in close proximity, it is possible to reduce these effects by minimizing the length at which two lines are next to one another. This is accomplished by retaining the tighter interconnect spacing and die size but implementing a greater number of interconnect levels of metal, where segments of common wiring traces are broken up and separated. This non-trivial task can be accomplished using computer aided design (CAD) design tools, presently under development, where the collective placement of large numbers of lines is optimized to reduce coupling. The last three approaches are related to the introduction of new materials and processes into the wiring architecture. The use of higher conductivity metals and low E dielectrics were mentioned earlier, but must be addressed in the context of process simplicity and cost. Studies [ lo] are presently in progress involving the generation of submicron sized
-1.6
0.1
0.2
0.3
0.4
0.5 TIME
0.6
0.7
0.6
0.9
1.0
( NANOSEC)
Fig. 7. Crosstalk observed between two interconnects having a cross section of 1 Frn’ separated by 1 pm with a ground plane 2 pm below it. The driven line sees Vl and magnitude of crosstalk is V2 (from ref. [ 91)
172
M.E. Thomas /Materials Chemistry and Physics 41(1995)
shielded interconnections which are substantially less susceptible to this phenomena. The new technology involves the generation of 3-D ‘micro-coaxial’ interconnects where each interconnect on the device is individually enclosed in an encapsulating ground plane. Although this process technology has not been demonstrated on devices, the technique of simultaneously shielding all lines with a common ground plane holds great promise in dramatically simplifying the computationally intensive CAD layout methodology.
7. Conclusions In summary, the next decade of semiconductor device development will be dominated by the interconnectivity challenge. Device performance will be severely impacted by interconnect parasitic considerations and to a lesser extent by active device switching speeds. The interconnect issues previously discussed will require novel material approaches and architectures to provide solutions which allow high performance systems to enter the marketplace at a cost effective price with high reliability. Present efforts in material research appear to indicate that Al via filling technologies will supplant W plug technology in the near future. This will occur if robust deposition processes can be developed along with efficient process flows having high yields. This technological development along with the replacement of silicate ILDs with organic based systems, having lower dielectric constants, should positively impact process yield, simplicity, cost and performance. Copper technology will have to overcome a number of process
167-172
integration problems before it will meet acceptance in manufacturing. New design methodologies for routing many levels of dense interconnect should greatly help designers avoid signal integrity issues at high frequency operation. This will, however, probably occur at the expense of requiring more levels of metal to obtain the correct level of functionality. Effective methods for the physical shielding of individual interconnect lines have been proposed to simplify the CAD routing problem, however, a great deal of work must be performed to ascertain the validity of such an approach. Although the interconnect challenges for deep submicron devices seem formidable, it appears that there are a number of potential solutions which will support the production of dense deep submicron integrated circuits for the next decade.
References [l] P. Renteln, M.E. Thomas and J.M. Pierce, V-MIC ConJ, (1990) 57. [2] M.E. Thomas, S. Sekigahama, P. Renteln and J.M. Pierce, V-MIC co?& (1990) 438. [ 31 W. Maly and J. Deszczka, Electron. Len., 19 ( 1993) 226. [4] C.H. Stapper, Proc. IEEE, 71 (1983) 453. [S] J. Khare, B. Daniels, D. Campbell, M.E. Thomas and W. Maly, In?. Symp. VLSI Tech, Systems and Applications, Taipei, Taiwan, May 1991, p. 424. [6] W. Maly, IEEE Trans. CAD, (July) (1985) 161. [7] A.V. Ferris-Prabhu, IEEE J. SoWState Circuits, SC-20 (1985) 874. [8] B. Luther et al., VLSI Multilevel Interconnect Con&, (1993) 15. [9] LA. Saadat and M.E. Thomas, VLSIlnterconnect Optionsfor On-Chip High Performance Applicafions, Weston, Nov., 1991, p. 3 18. [lo] M.E. Thomas, LA. Saadat and S. Sekigahama, ht. Electron Device Meet., (Dec.) (1990) 3.5.1.
Materials Chemistry and Physics 41 ( 1995) 167-172
Manufacturing considerations for VLSI interconnect systems Michael E. Thomas National Semiconductor
Corporation,
Fairchild Research Center, 2900 Semiconductor Drive, MS E-100, Santa Clara, CA 95052, USA
Received 2 March 1995
Abstract In the next decade, it is expected that integrated circuits having 5-7 levels of metal will be common in VLSI technologies with linear interconnect densities approaching 200 m/cm* level. Multilevel interconnect technology needs are presently generating processing and
structural issues which will dominate the future manufacturing yield and performance of these integrated circuits. The challenge of meeting these needs will require a concurrent improvement in design and manufacturing simplicity and cleanliness. This presentation will examine the architectural needs of future multilevel metal systems in light of the lithography, materials and electrical requirements which must be addressed by the interconnect
engineer. A comparison
of interconnect
systems based on different conductor materials will be presented.
Keywords: VLSI interconnect systems; Manufacture
1. Introduction
1Device Technology lUemory[
One of the greatest challenges in the production of verylarge-scale integrated (VLSI) electronic circuits lies in the ability of engineers and scientists to use ultra fine conducting metallic wires to link hundreds of millions of transistors on a postage stamp sized sliver of silicon. Because of routing limitations in a single level of conducting metal wire, one’s ability to obtain high degrees of connectivity between these millions of electrically active transistors cannot be achieved without multilevel metal (MLM) interconnect. In the next decade, it is projected that up to 7 levels of on-chip interconnect wiring with feature sizes approaching 0.12 pm will be required to utilize all of the active devices built into the Si substrate. At present, there are two technology paths involving memory and logic devices which have different interconnect requirements. Fig. 1 summarizes the interconnect needs for each technology. In order to optimize the resolution from production lithography tools, a high degree of wafer surface flatness at all interconnect levels must be established prior to delineating and etching high resolution interconnect patterns. This flatness (which is expected to be on the order of = 200 nm) facilitates tighter feature size control since a smaller depth of focus (DOF) must be employed. Subsequent etch process margins are also improved, since metal films which used to run over the sidewalls of rough topographical features and look thicker to anisotropic etches are essentially eliminated. 0254-0X34/95/$09.50 0 1995 Elsevier Science S.A. All rights reserved SSDIO254-0584(95)01510-2
r
* Periodic
Designs
. Tight Pitches / Density Optimized - More Defect Sensitive in Any Single Level
Considerations pPsI Logic
-Random mEmploy
Designs
Looser Piches More Layout Latitude
Sensitivity / Level Less than for Memory
*Five
- Easier
* More Difficult
*Employs
Redundancy
I
*Defect
. Two to Three Metal Layers Planatfzation
Devices
to Seven Metal Layen
- Limited
Planaffzation
Redundancy
* More Reliability
Issues
Fig. 1. Interconnect needs for memory and logic devices.
Due to memory’s periodic design and optimized density, planarization requirements for this technology can probably still be met, for the foreseeable future, by spin-on glass dielectrics (SOGs) used in conjunction with CVD SiOZ films. Since these materials facilitate good levelling of features having spacings of up to 5 pm, the above dielectrics or the incorporation of new ECR CVD dielectrics can be employed and provide good levelling in the memory cell array. Logic devices are not so fortunate, since they typically possess a myriad of functions which employ the Si real estate in a less efficient manner. In many cases, since interconnect features are laid out using auto-routing techniques which attempt to optimize wiring delay, power and interconnectivity a wide variety of feature sizes are generated which range over hundreds of microns. These device characteristics make it necessary to use many more levels of metal for logic versus
168
M.E. Thomas/Materials Chemistry and Physics 41 (1995) 167-172
2. Interconnect manufacturing
2. Schematic per 1994).
Fig.
cross section of a typical logic interconnect
system (as
less but denser levels for memory. These characteristic requirements of logic devices having a wide range of interconnect features makes the attainment of global planarization much more difficult. This need has ushered in the use of them-mechanical planarization (CMP) techniques, in which a slurry and porous polymeric pad material are placed in contact with the wafer and are used to globally level dielectric surfaces [ 1,2]. In the past decade, memory technology was the major market driver and 2 levels of metal were common among memory and 3 levels of metal for logic devices. At present, microprocessors have become the major market driver and some present designs use 5 levels of metal to connect all of the functions needed on chip to provide more computational horsepower. This need may severely impact device yield and reliability due to the numerous thermal excursions to temperatures approaching 400 “C, the metal levels will see during subsequent processing. The functional yield per level of interconnect for memory is lower than logic devices, however, there are less metal levels used in memory. Memory because of its repetitive nature can implement redundancy to recover from functional defects. This is a luxury that logic has a more difficult time utilizing. Fig. 2 shows a schematic cross section of the interconnect system which is in wide use today for logic. The system employs metals such as TiN and Ti which perform a number of functions. The Ti acts to reduce the contact/via resistance between the Si device and subsequent metal levels or between different metal levels. The TIN acts as a diffusion and nucleation barrier for CVD W plug deposition and is also used in stacked Al alloy films to provide strength to subsequently patterned interconnect lines. When this film is placed on top of the Al alloy, the main conductor of the interconnect system, it is also used as an anti-reflective coating for lithography and hillock suppression layer. At present, the W plugs are employed in the technology since CVD W filling of contacts and vias have matured at a much faster pace than other metal fill technologies. This situation is expected to change in the near future. The following sections will focus on a number of generic process issues, for logic devices, and address these described issues in more detail.
technological barriers
There are a number of key interconnect issues which could critically hinder technological development and manufacturability which are summarized below and are as follows: ( 1) yield (2) process simplicity (3) reliability (4) performance The remainder of this paper will address issues in each of these areas to identify where intensive R&D will be required.
3. Interconnect yield Back end of line (BEOL) processing which involves the generation of interconnect from the device contact level will continue to be a major functional yield detractor for submicron interconnect fabrication. The total functional yield of the interconnect system can be described using the following expression: YTOT
FUN =
YFE
n
yINT
(1)
I
where Yror roN = the total functional yield, YE = the total front end yield, II YINT= the total yield of all interconnect I levels. Since the interconnect metallization is not as amenable to chemical cleaning as previously processed single crystalline and polycrystalline Si, a larger number of defects are expected to be retained in these layers leading to device failure. At present, yield loss associated with interconnect processing can be substantial. It is imperative that good defect control is exercised over these layers. This situation will not go away and likely become worse with the ever increasing need for more metal levels. As metal features approach 0.25 pm, it is the opinion of the author that optical defect detection techniques will become exceedingly more expensive and difficult to apply and the uncertainty of differentiating between particulates and defects will increase. (In this discussion, it should be pointed out that particulates and defects are not the same since, for example, a defect caused by the flow of resist over a particle could be much larger than the particle’s physical dimensions causing it.) In order to more accurately assess interconnect defects associated with various processes, electrical test techniques will have to be employed and find greater utility. It is critical that the present method of using single valued numbers to describe defect levels be replaced with a functional defect description which is independent of device layout. This can be accomplished by generating a previously described defect distribution function,f(R) [ 3,4]. Past studies [S] have described the methodology which can be used to obtain the defect distribution function f(R) from defect histograms. In order to perform yield estimation,
M.E. Thomas/Materials
27
IL-
Fig. 3. General
ex& -jA(RYtR)
characteristics
(a)
-
(b)
fi(R) n
of the defect distribution
A(R) \
function, f(R),
and the critical
area, A(R),
as a function
of defect radius R. Y,N7=
W.
the critical area A(R) [6,7] of the layout must also be extracted to help accurately assess the yield impact attributed to an interconnect level. The critical area is the fraction of the total die area which is susceptible to a defect of size R. The critical area has the property of increasing with the radius of the defects present in the system, where the defects become large enough to effectively become the whole area of the die. The general characteristics of both the defect distribution and the critical area as a function of the defect radius are shown in Fig. 3. (The defect distribution function will have different characteristics for different facilities and must be evaluated individually.) If we take the product of these two curves and integrate them together the yield for any metal level i can be estimated using the following modified Poisson equation: Y,=exp(
169
Chemistry and Physics 41 (1995) 167-l 72
A(R)f(R)
dR)
(2)
I
where: Yi= yield of the ith level of metal, A(R) = the critical area function,f(R) = the defect distribution function. Fig. 3 can be used to qualitatively demonstrate how one can make tradeoffs in the design and/or manufacturing areas to enhance device yield. Fig. 3(a) addresses the influence that changes in manufacturing cleanliness have on the functional yield of an interconnect level. If the layout of the interconnect level is not changed, which fixes the critical area function A(R), it can be seen that by shifting the magnitude of defect distribution downward fromf, (R) tof2( R) the value of the integration described in relation (2) also decreases. This change would positively impact the yield since the value of the integral is exponentially related to it. Fig. 3 (b) shows the impact of the modifying the layout, where the critical area change from A1 (R) to A,(R) reduces the value of the integral and positively impacts the yield. These qualitatively obvious results explain how tradeoff can be made in manufacturing or design to optimize yield. Presently studies are underway to see if the device interconnect yields can be quantitatively captured with high degrees of accuracy using this approach.
4. Interconnect process simplicity In the past decade, interconnect processing has evolved from what was once a conceptually simple methodology to one having great complexity. This evolution occurred due to an order of magnitude reduction in the interconnect feature size and the drive to implement more functions on a monolithic integrated circuit. This development has placed much greater demands on the mechanical and electrical performance of the materials. Due to these demands, new technologies were adopted, such as: ( 1) anisotropic dry etching of interconnect stacks; (2) generation of complicated keyhole free interlevel dielectrics ( ILDs) ; (3) straight walled contact and vias; (4) metal deposition technologies having high conformality and the ability to fill deep vias and contacts; (5) high temperature refractory metals which act as barriers, nucleation layers, contact formers and anti-reflection coatings for optical lithography; (6) multilayer interconnect stacks having better mechanical and electromigration stability; (7) them-mechanical planarization of ILD surfaces and metals. With the greater offered functional complexity, the need for many levels of metallization has made the generation and filling of vias between levels of metal a key problem to address for high density circuits. It was unfortunate that a mature Al alloy deposition process capable of filling vias was not developed before that of CVD W. If Al via filling processes had been developed, a more natural evolution of interconnect technology would have occurred and the complicated structure shown in Fig. 2 would not have been adopted. Recent studies are exploring the use of lower resistivity metals such as CVD Cu and Al and physically vapor deposited (PVD) Al, which will provide via/contact filling of features having aspect ratios greater than 5: 1 and widths near 100 nm. The generation of these technologies will be
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Chemistry and Physics 41 (1995) 167-l 72
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Dep
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4 HIGH T STEPS
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Fig. 4. Potential manufacturing
pathways
for multilevel interconnect.
expected to supplant the present interconnect system which employs CVD W plugs. An emphasis has also been placed on the development of organic dielectrics which can be used as replacements for CVD deposited SiOp films. If these films can be proven and integrated into a full process flow with new plug filling metallization deposition technologies, even greater reductions in process complexity can be achieved. This will occur since the application of the films will be substantially easier (spinning) and faster than CVD deposition. The interlevel dielectric (ILD) process will involve only a single layer of material as opposed to 3-layer dielectric stacks which are presently used consisting of SiO,/SOG/ SiOZ. Fig. 4 shows two potential manufacturing pathways which will be adopted once mature via fill techniques, new dielectrics and integrated process flows are developed. When a generalized analysis is performed of the interconnect processes presently used versus those proposed, an estimate can be made of the simplification afforded by the adoption of the new technologies. Fig. 5 is a schematic which has extracted the Al via fill technology path from Fig. 4. In this figure, the major process steps required to generate a via and interconnect level using present and proposed interconnect formation techniques were estimated. The estimates were based on identifying major pieces of equipment that a wafer would have to be passed between and processed through to complete the fabrication. (The analysis of the vias process was performed since the contact level involves only one of several levels of metal in the device.) From this analysis, it was observed that a great amount of process overhead presently exists in the generation of the W plugs and ILD layers. If an Al via fill process can be employed to replace the CVD W plug formation, a better than 20% decrease in process complexity can be achieved. By replacing the layered silicate/SOGinsulators with a single organic based dielectric, the overall process complexity can be reduced by 50%. In the analysis for the contact formation process, the reduction in complexity is less since there are a number of metals common to the present interconnect which
* Possible to Cut Ma/x Processes by roughly50% using good material design
Fig. 5. Schematic of reduction in the number of steps in a via process using Al plugs vs. CVD W plugs.
are required with high temperature processes to make good electrical contacts to silicon. From a cost point of view, there is also a notable cost advantage of replacing WF6 with a less expensive Al deposition source. In performing this analysis where Cu is used as the conductor system, the picture is less clear about reductions in process complexity since: (i) Cu requires barriers to inhibit its diffusion and (ii) it is extremely difficult to plasma etch. These two issues have forced technologists to implement an approach where the Cu is deposited into barrier metal lined channels of dielectric. The Cu is then removed by CMP processing leaving the Cu in the channels (Damascene process [ 81) . Although this process is structurally very attractive, since it leaves a top metal surface which is planar with its ILD layer, a large number of process steps are required to generate a level of wiring. A large amount of work is presently being focused on Cu based interconnect systems to prove its viability in large integrated circuits and simplify its process integration. Unless attractive Cu alternatives are developed, Al based interconnects with low dielectric constant ILDs will probably be the future system of choice supplanting W plug based technologies.
5. Interconnect reliability In light of future interconnect requirements, reliability will become an ever increasing concern. The higher density of wiring which approximately doubles with every generation of technology introduces greater potential for device failure. Besides increased interconnect length, the reduction in wire cross section makes it more susceptible to failure by void formation due to stress migration (SM) and electromigration (EM). Since the demands for more functional device density have imposed the need for many levels of wiring, the first levels of interconnect experience a number of large thermal cycles between room temperature and roughly 400 “C. Fig. 6
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1 AEUABIUTY
ISSUES - STRESS HYSTERESIS
. WANT TO STAY IN THE TENSILE REGIME FOR SM CHARACTERIZATION ED ‘KUOS . ACCELERATED TESTS FOR EM SHOULD MEASURE STRESS DURING TESTING
L
I
I
I\
COOLING
COMPRESSION
Fig. 6. Schematic representation of a typical stress hysteresis loop for Al alloys.
shows a schematic representation of the stress which an interconnect sees as it is thermally cycled. At room temperature, the interconnects experience a high degree of tensile stress which is conductive to stress void growth. Upon heating to elevated temperatures, the stress that the Al alloy experiences changes from a tensile to compressive state due its higher expansion rate compared to SiOZ and silicon. Although voids cannot form in compression, Al does have the potential of cracking interlevel dielectrics and extruding through them. In light of these concerns, it is evident that a reduction in total number of thermal cycles seen by the wiring can only help to ensure greater future system reliability. The attainment of a more simple process, which was previously described, should support this need and make it possible to build a greater degree of interconnect integrity into the system. In referring to Fig. 5, it can be seen that the number of thermal cycles per level of processed interconnect can be substantially reduced (in this case by 66%) by simplifying the metal and dielectric processing. The electromigration resistance of the interconnect will depend on its physical integrity at the completion of processing and the crystallographic state of the metallization.
6. Performance
issues
The concurrent need for higher frequency operation and greater device density is contrary to simpler processing and reliability. These future requirements will become critical as electronic systems, operating at multihundred megahertz frequencies become available. As faster electrical pulses are driven along an interconnect in excess of 100 MHz, electromagnetic coupling can impose substantial unwanted voltages on neighboring undriven lines. This situation has been previously modelled [9] for two adjacent interconnect lines shown in Fig. 7. Suppose two interconnects are placed in close proximity (i.e., 1 pm space) at 2 pm above a ground plane for a length of 1 mm and one sees a rise time pulse of = 20 ps while the other is attached to ground. (The dense array of underlying wiring can look like a ground plane.) During the rise and fall of the waveform on the driven line,
a substantial unwanted voltage ( = 50% of V,) will be generated on the undriven line. This situation becomes substantially worse as the spacing between the wires is decreased. At 0.5 pm spacing, this crosstalk would rise to approximately 70% of the total voltage applied to the driven line. In addition we make smaller lines more resistive, there is a larger RC delay associated with the decay of the unwanted signal. A number of approaches can be implemented to alleviate these problems which involve: ( 1) reducing the common length of the two interconnects (i.e., more levels of wiring, smart routing) ; (2) increasing the wiring pitch; (3) using more conductive metals so that the height of the interconnect and overall sidewall capacitance can be reduced; (4) lowering the dielectric constant of the insulation between the wires in a level; (5) providing electrical isolation between the wires. The first two approaches are solutions which can be provided by compromises in design. By moving lines farther away from one another this problem can be relaxed. However, this solution typically increases the size of the Si die. This resulting increase can lead to a smaller number of total die per wafer which may adversely impact system cost. Since the coupling is also directly proportional to the length along which interconnect traces are in close proximity, it is possible to reduce these effects by minimizing the length at which two lines are next to one another. This is accomplished by retaining the tighter interconnect spacing and die size but implementing a greater number of interconnect levels of metal, where segments of common wiring traces are broken up and separated. This non-trivial task can be accomplished using computer aided design (CAD) design tools, presently under development, where the collective placement of large numbers of lines is optimized to reduce coupling. The last three approaches are related to the introduction of new materials and processes into the wiring architecture. The use of higher conductivity metals and low E dielectrics were mentioned earlier, but must be addressed in the context of process simplicity and cost. Studies [ lo] are presently in progress involving the generation of submicron sized
-1.6
0.1
0.2
0.3
0.4
0.5 TIME
0.6
0.7
0.6
0.9
1.0
( NANOSEC)
Fig. 7. Crosstalk observed between two interconnects having a cross section of 1 Frn’ separated by 1 pm with a ground plane 2 pm below it. The driven line sees Vl and magnitude of crosstalk is V2 (from ref. [ 91)
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M.E. Thomas /Materials Chemistry and Physics 41(1995)
shielded interconnections which are substantially less susceptible to this phenomena. The new technology involves the generation of 3-D ‘micro-coaxial’ interconnects where each interconnect on the device is individually enclosed in an encapsulating ground plane. Although this process technology has not been demonstrated on devices, the technique of simultaneously shielding all lines with a common ground plane holds great promise in dramatically simplifying the computationally intensive CAD layout methodology.
7. Conclusions In summary, the next decade of semiconductor device development will be dominated by the interconnectivity challenge. Device performance will be severely impacted by interconnect parasitic considerations and to a lesser extent by active device switching speeds. The interconnect issues previously discussed will require novel material approaches and architectures to provide solutions which allow high performance systems to enter the marketplace at a cost effective price with high reliability. Present efforts in material research appear to indicate that Al via filling technologies will supplant W plug technology in the near future. This will occur if robust deposition processes can be developed along with efficient process flows having high yields. This technological development along with the replacement of silicate ILDs with organic based systems, having lower dielectric constants, should positively impact process yield, simplicity, cost and performance. Copper technology will have to overcome a number of process
167-172
integration problems before it will meet acceptance in manufacturing. New design methodologies for routing many levels of dense interconnect should greatly help designers avoid signal integrity issues at high frequency operation. This will, however, probably occur at the expense of requiring more levels of metal to obtain the correct level of functionality. Effective methods for the physical shielding of individual interconnect lines have been proposed to simplify the CAD routing problem, however, a great deal of work must be performed to ascertain the validity of such an approach. Although the interconnect challenges for deep submicron devices seem formidable, it appears that there are a number of potential solutions which will support the production of dense deep submicron integrated circuits for the next decade.
References [l] P. Renteln, M.E. Thomas and J.M. Pierce, V-MIC ConJ, (1990) 57. [2] M.E. Thomas, S. Sekigahama, P. Renteln and J.M. Pierce, V-MIC co?& (1990) 438. [ 31 W. Maly and J. Deszczka, Electron. Len., 19 ( 1993) 226. [4] C.H. Stapper, Proc. IEEE, 71 (1983) 453. [S] J. Khare, B. Daniels, D. Campbell, M.E. Thomas and W. Maly, In?. Symp. VLSI Tech, Systems and Applications, Taipei, Taiwan, May 1991, p. 424. [6] W. Maly, IEEE Trans. CAD, (July) (1985) 161. [7] A.V. Ferris-Prabhu, IEEE J. SoWState Circuits, SC-20 (1985) 874. [8] B. Luther et al., VLSI Multilevel Interconnect Con&, (1993) 15. [9] LA. Saadat and M.E. Thomas, VLSIlnterconnect Optionsfor On-Chip High Performance Applicafions, Weston, Nov., 1991, p. 3 18. [lo] M.E. Thomas, LA. Saadat and S. Sekigahama, ht. Electron Device Meet., (Dec.) (1990) 3.5.1.