Materials interfaces in flip chip interconnects for optical components; performance and degradation mechanisms

MICROELECTRONICS RELIABILITY PERGAMON

Microelectronics Reliability 38 (1998) 1307-1312

Materials interfaces in flip chip interconnects for optical components; performance and degradation mechanisms Robert H. Esser a, A. Dimoulas a, N. Strifasa, A. Christou a, N. Papanicolaub ° Department of Materials and Nuclear Engineering And Centerfor OptoelectronicsDevices, Interconnects and Packaging, University of Maryland, College Park 20742

bNavalResearch Laboratory, Washington, DC 20375 Abstract

Flip chip solder joint reliability is dependant on final microstructure. The interface between the solder and the underlying metallization is of primary concern since the majority of joint failures occur at or near the interface. We report the results of our investigation on the structure-property relationships of the as deposited metallization and electroplated Pb/Sn solder, as they affect failure mechanisms. Samples investigated were prepared by electron beam evaporation of a Cr/Cu/Au metallization. Electroplated solders were prepared using a high tin solder bath and current density of 3.2mA/cm 2. It is shown that interdiffusion and intermetallic formation between gold and copper occurs during evaporation deposition. It is also shown that a significant amount of interdiffusion and intermetallic formation between the tin in the solder and the seed layer metals (Cu and Au) occurs during the electroplating operation. It is believed that this is due largely to resistive heating of the samples. The degree of interdiffusion in the as deposited state determines the ultimate reliability of the flip chip solder bumps in an optical configuration. © 1998 Elsevier Science Ltd. All rights reserved.

1.0 Introduction

Flip chip solder die attach schemes have many applications in the microeleelronics industry. The most common application to date is high density interconnection between the chip and the substrate [1,2,3]. A new application for solder ball bonding is in the area of vertically integrated free space optical interconnects [4]. Current microelectronic architectures are two dimensional. A vertically integrated structure allows expansion and utilization of frequently unused substrate area and expands interconnect connectivity to a volumetric one. The predominant concern with vertically integrated free space optical interconnects is planar alignment [5]. Flip chip

solder bonding technology can be applied to ensure planar alignment. The passive alignment achieved with properly designed flip chip structures is an adequate solution of the alignment problem [4]. In order for free space optical interconnects to meet specifications and requirements successfully, they must be aligned to extremely close optical tolerances. Flip chip solder interconnect technology has a self centering effect [4,5] that allows the alignment to be done passively. The passive alignment is almost entirely due to the surface tension of the solder [5]. As long as the solder can wet adequately over the majority of the interconnect sites, then the surface tension will provide a horizontal passive alignment. The alignment may be degraded by surface tension

0026-2714/98/$ - see front matter. O 1998 Elsevier Science Ltd. All rights reserved. PII: S0026-2714(98)0013 l-0

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variations due to the presence of intermetallic compounds. In order to realize the many benefits of optical interconnects, they must be reliable enough to rival current electrical interconnection architectures. Of great concern in flip chip solder bonding reliability is thermal fatigue [6-10] I. The thermal expansion mismatch between the substrate and the other chips in the module will result in mechanical strain on the solder bumps. As the module experiences a normal heating and cooling cycle during use, the solder joints experience low cycle fatigue that has been modeled by the CoffmManson equation [1,11]. The interface metallurgy between the solder and the wetting pad is critical to the solder joint reliability. In the present work, we will show that the degraded interface is present due to the high electroplating current density. The purpose of the current research is to characterize the interface between the solder bump and the wetting pad metaUization. The solder is electroplated, and during this operation, the interface experiences resistive heating which leads to interdiffusion and other diffusion controlled reactions, so, characterizing the material system in the as deposited state is very important, and may be used as a reliability indicator. In the present work, Rutherford Back Scattering(RBS) and X-Ray Diffraction(XRD) have been used to monitor the diffusion and investigate the existence of intermetallic formation respectively. These observations are then used as the basis for process optimization and for reliability prediction. This study is part of a larger investigation to fully characterize the effect different material parameters have on the evolution of the solder/wetting pad interface. Additional diagnostic tools such as Sputter-Auger spectroscopy and Focused Ion Beam analysis will be used interface analysis. The results will culminate in a physics of failure model for predicting the reliability of the flip chip optical interconnects.

for thermal expansion as possible. Other problems include solder wetting/dewetting and random fracture at brittle intermetallic layers. 2.1 Solder wetting

The first step in the fabrication of flip chip solder bonds is the formation of the solder wetting the pads. The wetting of solder is controlled by the Young-Dupree Law [ 12]: :r~, - Y , / = Ylv c o s 0

(1)

Where y~y is the surface energy, and the subscripts refer to interfaces of solid-vapor, solidliquid, and liquid-vapor. 0 refers to the angle between the solder and the wetting pad. Any factor that effects any of these surface energies, effects the wetting of the solder.[2,11,12] Oxidation at the solder surface can be a major problem during and after soldering. Even a partial pressure of oxygen of 10"6torr can be sufficient to oxidize solders [11]. The typical solutions for the oxidation problems include: scrubbing the solder pad before bonding; use of a flux to reduce the surfaces and remove oxides [12]; bonding in an inert atmosphere; and passivation of the bonding surface with a thin gold film. [11] Another factor that effects the solder wettability is the surface roughness. Shukla and Mencinger have modified from the Young-Dupree equation [2] in order to take into account surface roughness. Equation (2) shows the modified equation in terms of an adhesion energy (Wa):

-we =

[r,,0+cosO-r)]

(2)

Where ~v has the usual meaning and y is the strain energy due to thermal mismatch, k is the contact coefficient which depends on surface roughness. This equation has been used to qualitatively compare the surface tensions of the available solders for optical interconnects.

2.0 Flip chip design issues 2.2 Formation o f intermetallics

Flip chip design involves material and geometry selection. Both must be selected in order to overcome potential reliability problems [5]. The most significant reliability problem is strain fatigue caused by coefficient of thermal expansion mismatch as mentioned above. It is important to choose materials that have as similar coefficients

In order for a solder bond to adhere to the wetting pad, a metallurgical bond must form [12]. A good indicator of metallurgical bonding is the formation of intermetallics [13] (lntermetallies are chemical compounds of metals with a distinct chemical formula such as CthSn~ and Cu3Sn).

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R. H. Esser et al./Microelectronics Reliabifity 38 (1998) 1307-1312

Without the formation of intermetallics, the joint is only held together by surface tension and Van tier Walls forces. The typical bonding pad metallization in the present investigation includes copper [12], and the wetting pad metallization of Cr/Cu/Au. Solders use a combination of lead and tin, but, environmental concern ffas generated interest in developing lead free solders. At elevated temperatures, the tin of the solder can diffuse quite readily into the wetting pad. At the interface, a chemical reaction involving the metals of the solder and the metals of the wetting pad can occur forming the intermetallic. Most of these compounds form low melting temperature ternary eutectics. As the ternary eutectic forms, tin can diffuse even faster causing the intermetallic to grow faster. The most important intermetallics and their corresponding eutectics with melting points are listed in table 1.[11] As has been previously reported, kinetics of intermetallic growth goes through two phases [13]. Initially, the growth of intermetallics is reaction controlled. The intermetallic formation is controlled by the reactivity of the metals. The kinetics then become diffusion controlled since the tin must diffuse to the reacting interface through the intermetallic layer before it can further react with the copper or gold. 2.3 Solder f a t i g u e

A GaAs chip with an area of l cm 2 on a silicon substrate will generate approximately 0.08 of shear strain on the flip chip solder bonds with a temperature increase of just 100°C. As the solder is strained, it will elastically and plastically deform. The plastic deformation will result in the material becoming harder and more resistant to further Table 1 Common intermetallics for copper and gold. Metal Intermetallies Eutectic Eutectic components Melting Temperature Gold AuSn4, AuSn2, Pb+Sn+AuSn4 1770C* AuSn, AuPb3 Pb+Sn+AuPb3 211°Cb Copper Cu6Sns, Cu3Sn Pb+Sn+Cu~Sns 182°Cc 'Prince, Raynor & Evans [14] bFrear, Jones & Kinsman [I 1] CChang [15] and Marcotte & Schroeder [16]

Table 2 Fatigue properties for common solders. Solder Material

Grain Size

Fatigue Properties (Nf)*

Hard Solders

Au 30%- Sn

1-5~tm

Excellent>104

Pb 10% - Sn

5-101am

Intermediate 103

Pb 10% - Sn

1-31am

Excellent>104

Soft Solders

In

10-151am

Poor

PbSn

1-3p.m

Intermediate

AuSn

5-61~m

Intermediate 103

10 2- l0 3 10 3

Material data taken from ref. 11. Fatigue properties estimated from Coffin-Manson calculations. * Number of cycles to failure for a AT of 125°C plastic deformation. Further plastic deformation will result in the development of microcracks and eventually fracture. It is possible to design the solder so that the onset of fatigue failure is delayed. The solder's resistance to fatigue is very dependant on the initial microstructure [1]. If the grain size is sufficiently small, the material will behave superplasitically, and there will be no yield stress observed at equilibrium at either the high or low temperature state of the thermal cycle. However, as the material thermally cycles, the grain size increases reducing its plasticity [7]. The addition of hard nanoparticles such as nickel has been shown to delay the grain coarsening observed in thermal cycling [1]. Table 2 shows the comparisons of solder with respect to microstructure and fatigue resistance for flip chip solder in optical interconnects.

3.0 Reliability problems with intermetailics

While the formation of intermetallics is critical for the formation of strong metallurgical bond, excess intermetallic formation reduces the reliability of the solder joint [6,7]. The primary source of failure of solder joints is cracking at the interface between solder and substrate [12]. The

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R. H. Esser et al./Microelectronics Reliability 38 (1998) 1307-1312

Figure 1. SEM of a sample showing solder bumps

reason for this is that the intermetallics between gold and tin are more brittle than the solder. Gold/tin intermetallics are particularly brittle [ 11]. A second source of observed failure due to intermetallics is spalling. If there is a large quantity of intermetallic at the interface, it may conglomerate into spheroidal structures that become the source of dewetting during the life of the flip chip solder joint [6]. In order to eliminate these failure mechanisms, one must limit intermetaltic formation and inhibit its growth. Keeping process temperatures low during deposition is important for inhibiting growth, while using very thin films of the intermetallic constituents will limit the ultimate thickness of the intermetallic. 4.0 Experimental

procedures

In the present investigation, samples were prepared by electron beam deposition of 20nm Cr, 150nm Cu and 40nm Au as measured in situ using a crystal deposition monitor. Control samples were analyzed by Rutherford Back Scattering (RBS), while a second set of control samples were analyzed by X-Ray Diffraction (XRD) techniques. These tests were to observe the as deposited condition of the metallization before electroplating. Two sets of samples were prepared using the same metallization on a thermally oxidized silicon substrate. These samples were then electroplated with tin (hard solder) at a current density of 12.4 mA/cm 2. The thickness of the electroplated solder was 51am. The thickness of the

Figure 2. lntermetallics in an as grown sample.

tin electroplating was thin enough to allow X-Ray Diffraction (XRD) to be performed. Other crosssectioned samples were used to measure and monitor the intermetallic thickness. The flip chip samples were 8x8 and 16x16 arrays of solder bumps separated by 2561am. 4.1 Experimental results

Figures 1 and 2 show scanning electron micrographs of the solder bumps and a crosssection of the structure under analysis. Diffusion of the metallization into the silicon dioxide layer is evident. Also, some round structures are observable in the solder layer. These structures could be intermetallic nodules, or spalling which leads to de-adhesion of the flip chip bond during further processing or testing. X-Ray Diffraction analysis was also performed on the as deposited Cr/Cu/Au metallization for each type of array as shown in Figure 3(a). The prominent peaks of each metal and the substrate are evident. There is also a peak for a copper--gold intermetallic, showing a well adhered bond between the thin films is present. Additionally, XRD was performed on the as deposited metallization with the electroplated tin, as shown in Figure 3(b). The analysis was performed prior to reflow or any intentional sintering. The results show Au/Sn intermetallic formation and possible Cu/Sn intermetallic. One can note that the proportion of gold in the Cu3Au2 intermetallic is reduced. As the gold is consumed at both its upper and lower interfaces, its compounds will tend to be lower in gold content.

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R. H. Esser et al./Microelectronics Reliability 38 (1998) 1307-1312 - - - - , - - - -

1400

si (400)

1200 Au (111) 1000 >,

800

¢-

Cu(111)

600 400 200 0 20

30

40

50

60

70

80

70

80

2 Theta (a)

I

I

I

I

si (4oo)

1400 1200 1000

Cu(111)

8OO

Au (111)

t-

c

6O0 400

~(100}/S,uSn, Sn(311)

AuSn, AuSn4

200 0 20

3O

40

50

60

2 Theta

(b)

Figure 3: (a) As grown Cr/Cu/Au on a silicon substrate. (b) Tin electroplated on Cr/Cu/Au metallization. Intermetallic formation is clearly shown.

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5.0 Conclusion

References:

We have reported the important observation that interdiffusion and compound formation takes place during physical deposition of the materials on the substrate. The interdiffusion of the metals in the wetting pad must take place during deposition since the wafers are kept at room temperature during subsequent processing. The majority of the intermetallic formation between the gold and copper also forms during deposition. The gold--copper intermetallics become more copper rich as the gold is depleted. Electroplating introduces additional effects that could also have a significant effect on the microstructure. First, there is resistive heating at the interface. This increase in temperature results in enhanced diffusion between the metals and the solder, and increases the intermetallic reaction rate. There is also observable interdiffusion between the metals in the wetting pad and the substrate as well as between the metals themselves. The current during electroplating can also lead to electromigration, which may result in enhanced diffusion in the direction of current flow as well as the formation of voids. Electromigration may also cause localized material buildup resulting in local stress centers. We conclude that various parameters must be considered when designing solder bonded structures. Geometry and material properties, particularly CTE, must be considered in order to design reliability into the solder bonded structure or module. Material reactions play a very important role in determining the reliability of the module. The most important of these reactions is intermetallic formation that is present in order to ensure a good metallurgical bond. Control of intermetallic growth is critical so that the bond does not become brittle. Coarsening of the solder microstructure must also be addressed in order to ensure reliability during the lifetime of the device. Some other important considerations not discussed in this paper are thermal and environmental management. If the module is subject to cycles of extreme temperature change, the problems associated with thermal cycling will be amplified. If the module is exposed to corrosive environments, the solder may oxidize, or many other reactions could happen to the structure or active components that will be detrimental to device performance. Additional investigations are underway to quantify the observed reactions.

[11 [21 [31

[4]

[5] [6] [7] [81 [91 [10] [11]

[121

[131 [14]

[15]

[16]

G. Z. Pan, A. A. Liu, H. K. Kim, K. N. Tu, and P. A. Totta, Appl. Phys. Lett. 71, (20), p. 2946, 17 November 1997 R. K. Shukla and N. P. Mencinger, Solid State Technology. p. 67, July 1985 K. L. Lin, and S. Y. Chang, IEEE Transactions on Components, Packangin, and Manufacturing Technology B 19, (4), p. 747, Nov 1996 C. Pusarla, Design and Fabrication of Hybrid Optical Receiver For Free Space Optical Interconnections Using Flip-Chip Bonding. P h . D . Dissertation, Univ. Maryland, College Park. May 1996 S. Greathouse, Electronic Packaging and Production. p. 65 August 1997 D. R. Frear and P. T. Vianco, Metallurgical and Materials Transactions A, 25A, p. 1509, July 1994 D. Frear, D. Grivas, and J. W. Morris, Jr. Journal of Electronic Materials, 18 (6), p. 671, 1998 J. H. Lau, Engineering Fracture Mechanics, 45, (5), p 643, 1993 A. Yasukawa, IEEE Transactions on Components, Hybrids, and Manufacturing Technology. 13, (4), p. 1146, Dec. 1990 T. Pan, Journal of Electronic Packaging, 116, p. 163, Sept. 1994 D. R. Frear, W. B. Jones, and K. R. Kinsman. Solder Mechanics: A State of the Art Assessment Penn. The Minerals, Metals & Materials Society, 1991 F. G. Yost, F. M. Hosking, and D. R. Frear. The Mechanics of Solder Alloy Wetting & Spreading New York: Van Nostrand Reinhold, 1993 L. H. Su, Y. W. Yen, C. C. Lin and S. W. Chen, Metallurgical and Materials Transactions B. 28B, p. 927, Oct 1997 A. Prince, G. V. Raynor, and D. S. Evans, Phase Diagrams of Ternary Gold Alloys, 1990, Institute of Metals, London. Y. A. Chang, J. P. neuman, A. Kikula and D. Goldberg. Phase Diagrams and Thermodynamic Properties of Ternary Copper-Metal Systems. 1979, INCRA Monographs Series, Vol VI. V. C. Marcotte, and K. Schroeder. Proc 13~hNo. Amer. Thermal Analysis Soc. 13, p511 1984