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Role of reliability and accelerated testing in VHSIC technology
The use of high om.~gneticfields for the characterization of
impurities in epitaxiai GaAs M. N A F S A R Microelectron. J. 13 (1), 15 (1982) The only reliable method for indentification of donor contaminants such as Si, S, Si, Sn and Ge in ultra-high purity epitaxial GaAs is the observation of the 1 s --* 2 p transition by means of far-infrared photoconductivity in high-intensity magnetic fields. Until recently, interpretation of this simple data has been unreliable. For example, it is found that the inhomogeneous Stark broadening of the 1 s --* 2 p (m = -1) transition of the hydrogen-like donor in VPE grown GaAs almost disappears as the magnetic field is increased to 100 kilogauss (20 tesla). Moreover, our new method of employing robe epitaxial GaAs (p-type) slightly doped with a single type of donor now provides the solution to the problem of resolving and identifying the varity of possible substitutional donors, one at a time.
concept and by time zero functional performance verification of different part numbers. A voltage ramp test for rapid study (less than 100 h) of gate reliability of N-type metal-oxide semiconductor (NMOS) devices is discussed. H A S T (highly accelerated stess test) may also be used to accelerate significantly the corrosion of the A1 metallurgy of plastic encapsulated devices over the conventional temperature/humidity/bias test. Bomlin~ temperature measurements during device assembly
N. T. PANOUSIS, S. A. GEE and M. K. W. FISGHER Solid St. Technol., 91 (March 1983) A critical parameter in the assembly technique of thermosonic wire bonding is temperature. This article describes and compares two methods of measuring bonding temperatures. The first uses the voltage of a forward biased diode in a semiconductor device. The device is attached to a lead frame and placed on a bonder. During the bond cycle, the voltage across the diode is monitored Defect density and electrical properties of vacuum evap- against time. This voltage has been previously calibrated orated copper films for annealing studi~ of electrical against temperature under thermal equilibriumconditions to an accuracy and precision of -+I~ The second resistance K. N A R A Y A D A S , M. RADHAKRISHNAN and C. approach uses very thin (12 microns) foil thermocouples. The key is that the thermocouple is mechanically clamped BALASUBRAMANIAN to the device surface by bonding Au balls along the foil Electrocomponent Sci. Technol. 9, 171 (1982) Copper films (210-1650~) were deposited onto glass edges such that each ball is half un the foil and half on the microslides by vacuum evaporation. The films were sub- A1 metallization. These microclamps provide excellent jected to heat treatment at a constant rate and the varia- thermal contact without the well-known problems when tion of electrical resistance with temperature was using an intervening adhesive. The two approaches agree measured. The defect density and activation energy were to within • calculated for different thicknesses from the knowledge of the change in electrical resistance with temperature and time. The defect density, Fo(E)~,, varies from 17.2 to Circuit analysis, logic simulation and design verfieation 6.05 # m 9 cm eV -t in the thickness range 210-1650~ for VLSI whereas no appreciable variation in the activation energy A L B E R T E. R U E H I and GARY S. DITLOW Proc. IEE 71 (1), 34 (1983) is observed. Thickness dependence of resistivity and temperature In this paper, we consider computer-aided design techcoefficient of resitivity (TCR) were studied in the above niques for VLSI. Specifically, the areas of circuit analysis, thickness range and the bulk resistivity and TCR were logic simulation and design verification are discussed ~ith found to be 1.75/zt/. cm and 5.5 x 10-2 K -t respectively. an emphasis on time domain techniques. Recently, reAssuming the scattering coefficient to be zero, the mean searchers have concentrated on two general problem free path of conduction electrons was estimated. From areas. One important problem discussed is the efficient, the knowledge of the bulk resistivity and mean free path, exact-time analysis of large-scale circuits. The other area the Fermi surface area and the effective free electron is the unification of these techniques with logic simulation density per atom were evaluated as 21.86 x 1016cm-2 and design verification technique in so called multimode or multilevel systems. and 0.92 respectively. An overview of thickness mes.~rement techniques for Role of reliability and accelerated testing in VEISIC metallic thin film~
technoh~r SUSHIL K. MALIK I E E E Trans. Components Hybrids mfg Technol. (CHMT-5 (1), 138 (1982) In very high scale integrated circuits (VHSIC)/technology, reliability ground rules must be developed and included in chip design rules. This concept of"designedin" reliability, rather than the traditional "tested-in" reliability approach, will be necessary in VHSIC. Accelerated testing becomes important as timely feedback on process, design, and reliability must be provided during technology development. The functional part numbers may be qualified by the technology qualification
SHELDON C. P. LIM and D O U G RIDLEY Solid St. Technol., 99 (February 1983) Thickness monitoring is an essential part of process control in the manufacture of semiconductor devices. The thickness measurement techniques applicable to the metallic thick films commonly found in the integrated circuit industry are described. It is seen that the usual mechanical, electrical, and optical methods have limitations in measurement uncertainty due to variations in film composiiion or deposition conditions or in their use by manufacturing personnel. Attention is also drawn to the use of light absorption as a technique for measuring very thin metallic films. 63
impurities in epitaxiai GaAs M. N A F S A R Microelectron. J. 13 (1), 15 (1982) The only reliable method for indentification of donor contaminants such as Si, S, Si, Sn and Ge in ultra-high purity epitaxial GaAs is the observation of the 1 s --* 2 p transition by means of far-infrared photoconductivity in high-intensity magnetic fields. Until recently, interpretation of this simple data has been unreliable. For example, it is found that the inhomogeneous Stark broadening of the 1 s --* 2 p (m = -1) transition of the hydrogen-like donor in VPE grown GaAs almost disappears as the magnetic field is increased to 100 kilogauss (20 tesla). Moreover, our new method of employing robe epitaxial GaAs (p-type) slightly doped with a single type of donor now provides the solution to the problem of resolving and identifying the varity of possible substitutional donors, one at a time.
concept and by time zero functional performance verification of different part numbers. A voltage ramp test for rapid study (less than 100 h) of gate reliability of N-type metal-oxide semiconductor (NMOS) devices is discussed. H A S T (highly accelerated stess test) may also be used to accelerate significantly the corrosion of the A1 metallurgy of plastic encapsulated devices over the conventional temperature/humidity/bias test. Bomlin~ temperature measurements during device assembly
N. T. PANOUSIS, S. A. GEE and M. K. W. FISGHER Solid St. Technol., 91 (March 1983) A critical parameter in the assembly technique of thermosonic wire bonding is temperature. This article describes and compares two methods of measuring bonding temperatures. The first uses the voltage of a forward biased diode in a semiconductor device. The device is attached to a lead frame and placed on a bonder. During the bond cycle, the voltage across the diode is monitored Defect density and electrical properties of vacuum evap- against time. This voltage has been previously calibrated orated copper films for annealing studi~ of electrical against temperature under thermal equilibriumconditions to an accuracy and precision of -+I~ The second resistance K. N A R A Y A D A S , M. RADHAKRISHNAN and C. approach uses very thin (12 microns) foil thermocouples. The key is that the thermocouple is mechanically clamped BALASUBRAMANIAN to the device surface by bonding Au balls along the foil Electrocomponent Sci. Technol. 9, 171 (1982) Copper films (210-1650~) were deposited onto glass edges such that each ball is half un the foil and half on the microslides by vacuum evaporation. The films were sub- A1 metallization. These microclamps provide excellent jected to heat treatment at a constant rate and the varia- thermal contact without the well-known problems when tion of electrical resistance with temperature was using an intervening adhesive. The two approaches agree measured. The defect density and activation energy were to within • calculated for different thicknesses from the knowledge of the change in electrical resistance with temperature and time. The defect density, Fo(E)~,, varies from 17.2 to Circuit analysis, logic simulation and design verfieation 6.05 # m 9 cm eV -t in the thickness range 210-1650~ for VLSI whereas no appreciable variation in the activation energy A L B E R T E. R U E H I and GARY S. DITLOW Proc. IEE 71 (1), 34 (1983) is observed. Thickness dependence of resistivity and temperature In this paper, we consider computer-aided design techcoefficient of resitivity (TCR) were studied in the above niques for VLSI. Specifically, the areas of circuit analysis, thickness range and the bulk resistivity and TCR were logic simulation and design verification are discussed ~ith found to be 1.75/zt/. cm and 5.5 x 10-2 K -t respectively. an emphasis on time domain techniques. Recently, reAssuming the scattering coefficient to be zero, the mean searchers have concentrated on two general problem free path of conduction electrons was estimated. From areas. One important problem discussed is the efficient, the knowledge of the bulk resistivity and mean free path, exact-time analysis of large-scale circuits. The other area the Fermi surface area and the effective free electron is the unification of these techniques with logic simulation density per atom were evaluated as 21.86 x 1016cm-2 and design verification technique in so called multimode or multilevel systems. and 0.92 respectively. An overview of thickness mes.~rement techniques for Role of reliability and accelerated testing in VEISIC metallic thin film~
technoh~r SUSHIL K. MALIK I E E E Trans. Components Hybrids mfg Technol. (CHMT-5 (1), 138 (1982) In very high scale integrated circuits (VHSIC)/technology, reliability ground rules must be developed and included in chip design rules. This concept of"designedin" reliability, rather than the traditional "tested-in" reliability approach, will be necessary in VHSIC. Accelerated testing becomes important as timely feedback on process, design, and reliability must be provided during technology development. The functional part numbers may be qualified by the technology qualification
SHELDON C. P. LIM and D O U G RIDLEY Solid St. Technol., 99 (February 1983) Thickness monitoring is an essential part of process control in the manufacture of semiconductor devices. The thickness measurement techniques applicable to the metallic thick films commonly found in the integrated circuit industry are described. It is seen that the usual mechanical, electrical, and optical methods have limitations in measurement uncertainty due to variations in film composiiion or deposition conditions or in their use by manufacturing personnel. Attention is also drawn to the use of light absorption as a technique for measuring very thin metallic films. 63