SiGe Devices

Chapter 6

SiGe Devices Pouya Hashemi and Takashi Ando IBM Corporation, Yorktown Heights, NY, United States

6.1 SiGe CHANNEL PROMISES FOR HIGH PERFORMANCE FETs Scaling rules, as the main driving force of the CMOS industry, require doubling of the transistor aerial density per technology generation. Traditionally, the transistor dimension scaling by a factor of 0.7
has led to continuous performance enhancement or reduction in circuit delay. However, as the transistors are scaled down, the pace for performance boost slows down due the fact that the parasitic device components start to impact the overall device performance. To overcome this issue, strained Si has been introduced in the industry since the 90 nm technology node [1]. The channel strain has been enabled using tensile stress liners, mostly for n-MOSFETs and embedded silicon-germanium (SiGe) source/drain (S/D) for p-MOSFETs. The embedded SiGe in the S/D regions enforces compressive strain to the Si channel and has been optimized at each technology generation by the amount of Ge, boron doping, recess volume, and its profile to ensure the maximum strain benefit for the p-MOSFETs made on the bulk or SOI substrates [2,3]. On the other hand, it has been shown that beneficial impact of these known stressors is significantly degraded as the contacted gate pitch size is scaled down [4]. This issue is more pronounced for nonplanar architectures such as trigates, FinFETs, or gate-all-around nanowires especially when fabricated on SOI substrates. One option is to replace the Si with a high-mobility material such as SiGe or Ge. In particular, utilization of globally strained materials such as strained Si for nFET and strained SiGe for pFETs sounds to be a near-term technological solution, while replacing the channel with other candidates such as III-V or pure Ge is among the long-term solutions for advanced high-performance technologies. Germanium has a lattice constant of 0.5658 nm leading to 4% lattice mismatch with Si. When Ge atoms are combined with Si, a SiGe alloy forms, and its lattice constant can be linearly interpolated from those of Si and Ge. For thin SiGe layers pseudomorphically grown on Si substrates, the material is under biaxial compressive strain. On the other hand, SiGe layers on relaxed SiGe High Mobility Materials for CMOS Applications. https://doi.org/10.1016/B978-0-08-102061-6.00006-9 © 2018 Elsevier Ltd. All rights reserved.

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underlying buffers can have either biaxial compressive or tensile strain depending on the relative lattice mismatch between the two layers. Various studies have shown that strain plays a significant role on the band structure and transport properties of SiGe channels. Research on high-mobility SiGe channels ramped up at the early 1990s when significant advancements on high-quality substrates with low defect density levels were achieved [5,6]. For the sake of carrier-transport studies of SiGe, buried-channel SiGe heterostructures were the main research structure under investigation. Fig. 6.1 shows the schematic of a strained-Si/strained-Si1yGey/relaxed Si1xGex heterostructure commonly used to characterize the transport in buried SiGe-channel pFETs, along with its band diagram. For y larger than x, the buried Si1yGey layer is under biaxial compressive strain. For two reasons, the strained-SiGe layer is capped with a thin Si layer. First, as will be explained in details later in the chapter, surface passivation of Si and controlling the interface traps for SiGe without Si is extremely challenging. In addition, the use of Si cap provides a common substrate for dual-channel CMOS applications. The band alignment of strained Si and strained SiGe is such that it mostly confines the holes in the buried SiGe layer while confining the electrons in the strained-Si capping layer. Fig. 6.2A shows the effective hole mobility versus inversion charge density (Ninv) characteristics of such dual-channel structure for various y/x and y > 0.4 all the way up to the strained-Ge buried-channel devices [7–9]. In addition, Fig. 6.2B shows the mobility enhancement factor as a function of Ge fraction for such a quantum-well heterostructure. As can be seen, hole mobility monotonically increases with increasing Ge content in biaxially strained-SiGe quantum wells. By proper choice of Ge content in the channel and the buffer, a wide range of mobility values can be achieved with mobility enhancements up to 10
over (100)-oriented Si. Moreover, extremely high hole effective mobility numbers Gate electrode Gate dielectric Strained Si cap Strained Si1−yGey channel

ΔEV

Strain-relaxed Si1−xGex buffer

ΔEC Si Si1−yGey Si1−xGex

SiGe graded buffer Si substrate

(A)

(B)

EV

EC

FIG. 6.1 (A) Structure and (B) band diagram of strained-Si/strained-Si1yGey/relaxed-Si1xGex quantum-well heterostructure commonly used to characterize the transport in buried SiGe-channel pFETs.

y/x: 100/50 90/40 82/40 76/40 70/40 58/30 42/30 Si

2000 1500 1000 500

14 Mobility enhancement

Hole mobility (cm2/Vs)

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Biaxial compressive strain

12

Ninv = 5 × 1012 cm−2

10 8 6 4 2 0

0 0

(A)

5 × 1012

0

1013

−2

Ninv (cm )

(B)

20 40 60 80 100 Ge content, y (%)

FIG. 6.2 (A) Measured effective hole mobility versus Ninv for strained-Si/strained-Si1yGey/ relaxed-Si1xGex quantum-well heterostructures for various y/x. (B) Hole mobility enhancement factor over Si versus channel Ge fraction. (Data from J.L. Hoyt and C. Ni Chleirigh, Massachusetts Institute of Technology, with permission.)

above 1000 cm2/Vs have been measured for buried-channel strained-Ge quantum wells. These mobility results are quite exciting and have greatly motivated the scientists and engineers in both academia and industry to further investigate and evaluate the performance of such channel materials. However, the devices fabricated for these preliminary studies generally possessed relatively thick Si cap (2.5–5 nm) and thick SiO2 dielectric (3.5–11 nm) that suffer from scalability limitations for advanced technology nodes.

6.2 DEVICE CONSIDERATIONS In this section, we briefly address some key contributors to the device performance for a wide range of Ge fractions. Understanding some relevant fundamentals such as impact of the Ge content and strain on hole transport, band structure, material quality, and thermal conductivity can provide useful insight for device design and integration of SiGe-channel MOSFETs for various high-performance and low-power applications.

6.2.1 Hole Transport in SiGe Channel Effective carrier mobility of a MOSFET is a key factor that impacts the transport in the low drain field regime and in part contributes to the short-channel drive current. Mobility is inversely proportional to the scattering rate and the conductivity effective mass. The effective mass of SiGe is a strong function of Ge fraction, strain state (compression or tension), and strain type (uniaxial, biaxial, or combined). It can also be impacted by the current direction and surface orientation of the channel. On the other hand, the scattering rate

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collectively depends on the dominant scattering mechanism such as Coulomb scattering (from dopants or gate interface traps), phonon scattering, remote phonon scattering (in case of high-κ dielectrics), surface roughness scattering, thickness fluctuation scattering, and alloy scattering. For a relaxed SiGe system, theoretical calculations by Fischetti and Laux show that the latter mechanism is dominant for both electrons and holes with Ge content in the range of around 10%–85%, and mobility values lower than Si have been reported [10]. Similar study also reveals that for the biaxial compressively strained-SiGe system that is pseudomorphically grown on Si, the electron mobility is lower than Si mainly due to the alloy scattering, while the hole mobility monotonically increases (for Ge content more than 20%) with increasing the Ge fraction and the biaxial strain. This has also been experimentally verified by various experimental data from various research centers across the globe [9,11,12]. As discussed earlier, the strain state in SiGe layers pseudomorphically grown on Si or lower Ge-content-relaxed buffer layers is biaxial compression. The biaxial strain is shown to lift the degeneracy of the heavy-hole and light-hole subbands in the valence band, in addition to the effective mass reduction [10]. On the other hand, the theory suggests that the uniaxial compressive strain can further reduce the hole effective mass and is the optimum strain for the hole transport [13–15]. Fig. 6.3 shows the calculated hole effective mass of relaxed and uniaxially strained SiGe, lattice matched to Si, for various Ge fractions and surface orientations [15]. It can be seen that hole effective mass is monotonically decreased with increasing Ge content and uniaxial strain.

FIG. 6.3 Simulated hole effective mass as a function of Ge fraction for relaxed and uniaxial compressively strained Si1xGex (lattice matched to Si), with (100) and (110) surface orientations. (Reproduced with permission from K. Ikeda, M. Ono, D. Kosemura, K. Usuda, M. Oda, Y. Kamimuta, et al., High-mobility and low-parasitic resistance characteristics in strained Ge nanowire pMOSFETs with metal source/drain structure formed by doping-free processes, in: 2012 Symposium on VLSI Technology (VLSI Technology) Digest of Technical Papers, 2012, pp. 165–166. Copyright 2012 IEEE.)

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Interestingly, uniaxial strained SiGe with very moderate Ge fraction, that is, 20%, can provide lower effective mass than even pure relaxed Ge. In addition, the impact of surface orientation is diminished for Ge contents >50%, as the strain approaches significantly high levels. In practice, one way to achieve uniaxial strain is to start from globally biaxial strained substrates and pattern them to high-aspect-ratio fingers or bars [16]. As a result of patterning, a strain transformation occurs where the transverse component of the strain vanishes and a highly asymmetrical strain state close to uniaxial is obtained. This phenomenon has been verified by a recent experimental study on strained SiGe, and Ge fins and superior hole mobility values (near 2
over biaxial) have been achieved for highly asymmetrical strained SiGe and Ge FinFETs [17,18]. Based on the discussions so far, increasing Ge content results in hole mobility enhancement over Si. Here, a question arises whether this mobility benefit is due to the Ge content or the strain plays the dominant role. In other words, does the Ge content matter or does all the enhancements come from the strain? As most of the studies so far have been conducted on strained-SiGe structures lattice matched to Si, it is hard to decouple the strain and Ge fraction. To date, no systematic study exists to address this question for a wide range of Ge fractions, though it is possible to find some sporadic data. A study by IBM for low Ge fraction ( 25%) suggests that similar hole mobility and short-channel drive current can be observed for relaxed SiGe and Si channel pFETs [19]. In other words, for the low-Ge-content regime, strain plays the dominant role for transport enhancement. On the other hand, the study on high-Ge-content SiGe by the MIT group clearly suggests that even at a given level of strain, the Ge content also plays a role and increasing Ge can further boost the mobility [7].

6.2.2 SiGe Band Structure Understanding of the band structure for the SiGe system is essential for device designers to quantify the trade-offs between the performance and off-state leakage. The off-state leakage of a MOSFET can be limited by gate-induced drain leakage (GIDL) that is strongly correlated to the bandgap of the channel material at the drain side. For the relaxed SiGe system, the theoretical calculations by Braunstein et al. [20] and Weber and Alonso [21] suggest that for a Ge content below 85%, the band structure is Si-like, where the valence band has degenerate states for heavy holes and light holes, while the conduction band minima are defined by sixfold Δ valleys. For a Ge content above 85%, the conduction band minima are defined by L valleys, and the band structure is Ge-like. The SiGe bandgap decreases as the Ge content is increased. Moreover, the rate of the bandgap drop by changing Ge fraction is sharply increased for Ge contents above 85%. While the bandgap change is the result of the alteration in both conduction and valence bands, it is worth mentioning that the change mostly happens in the valence band and conduction band minima to the first order track that of Si.

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The band structure of the SiGe is strongly impacted by the strain. Biaxial strain is shown to lift the degeneracy of the heavy holes and light holes and lower the effective mass of the heavy holes [22]. On the other hand, uniaxial strain along the transport direction can result in further band warpage and reduction of the effective mass [15,23]. The change in valence band is 37 meV per 10% Ge for relaxed SiGe. On the other hand, for biaxial strained SiGe grown on Si, the theory suggests 74 meV per 10% Ge [24], while the experimental results predict a larger value of 87–101 meV per 10% Ge [7].

6.2.3 Material Quality and Thickness Constraints One of the key integration metrics for the SiGe and Ge devices is attributed to the material quality and defectivity of the channel. While the impact of defects on various device characteristics is not well understood, it may have implications on the leakage, transport, yield, and manufacturability of SiGe devices. To assure a high-quality and defect-free material, SiGe films should be grown under a critical thickness. Experimental data show that the critical thickness drops dramatically with increasing Ge content [25]. The critical thickness can be improved by changing the growth conditions in the metastable regime and by selective area epitaxy in advanced tools, such as low-pressure chemical vapor deposition chambers [26]. Interestingly, for high-Ge content above 50%, the equilibrium critical thickness is well below 10 nm. There have also been advances on the integration of SiGe channel on SOI substrates over the past few years. One approach utilizes high-quality epitaxial growth of strained SiGe on bulk Si or strained-relaxed buffer layers followed by a bond and etch-back technique [27,28]. In the other approach called Ge condensation, one takes advantage of the fact that under certain oxidation conditions and thermal processes, the Si atoms in the lower Ge-content SiGe layers are preferentially oxidized resulting in enrichment of the Ge in the remaining SiGe layer [29]. High-quality and low defect channels with superior mobilities have been reported using this technique. For advanced FinFET generations, having high-aspect-ratio and tall fins are desired to increase the current density per footprint. The state-of-the-art Si FinFETs have fin heights as tall as 42 nm [30]. If strained-SiGe fins are defined by epitaxial growth and lattice matched to Si, achieving competitive fin heights to the state-of-the-art Si FinFETs is extremely challenging due to the critical thickness constraints. This issue is more pronounced for high-Gecontent SiGe fins with Ge content above 50%. One approach to mitigate these constraints is to start with epitaxial growth of SiGe channels with a moderate Ge fraction, pattern the fins wider than the final target, and perform a Ge condensation to further enrich the Ge content [31]. This method is called 3D Ge condensation. The integration and device characterization using this technique will be discussed more in Section 6.4.

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6.2.4 Other Device Considerations In contrast to the state-of-the-art Si channel MOSFETs, SiGe devices can be impacted by some other differences in material properties such as thermal conductivity, permittivity, dopant diffusion, thermal budget, and interface traps. SiGe has lower thermal conductivity than both Si and Ge. Thus, the heat dissipation is significantly reduced for SiGe FETs resulting in enhanced self-heating effects, especially for those made on SOI substrates. A recent study on the self-heating effects of the Si, SiGe, and Ge FinFETs confirms this phenomenon [32]. Another issue with SiGe-channel devices is attributed to the higher relative dielectric permittivity of the SiGe compared with Si. The bulk relative permittivity (dielectric constant) of Si and Ge is 11.9 and 16, respectively. The scaling length of a MOSFET that is highly dependent on the gate architecture (planar, FinFET, or gate all around) is correlated to the channel’s dielectric constant [33]. Higher dielectric constant of the channel results in worse electrostatic scaling, and this is more tangible for high-Ge-content SiGe or pure Ge-channel MOSFETs. Beside fundamental challenges attributed to the physical material properties of SiGe systems, there are various process challenges that also depend on the Ge content. For instance, the melting point of Ge is 938°C, which is significantly lower than that of Si (1414°C). For SiGe systems, the melting point to the first order can be interpolated from those of pure Si and Ge. This sets an upper limit to the process thermal budget of SiGe MOSFETs. Furthermore, boron is commonly used in the S/D of group IV p-MOSFETs. For a given diffusion temperature, boron diffusivity is retarded in SiGe as compared with Si and is slowed down by increasing the Ge content [34]. Therefore, forming ion-implant-free junctions by diffusion of boron from the epitaxial S/D regions is expected to be challenging, especially for high-Ge-content transistors. Among the technological challenges of the SiGe MOSFETs, gate stack is one of the most challenging engineering issues. As mentioned earlier in this chapter, Si cap was traditionally used to passivate the channel by forming a quantum well to confine the holes in the buried SiGe layers of the pFETs. The utilization of a Si capping layer introduces some limitation for the electrostatic scaling of the device with high-κ/metal gate stack, in terms of capacitance oxide thickness (CET) or equivalent oxide thickness (EOT) scaling. While avoiding Si cap can be beneficial in scaling the CET, control of the interfacial layer (IL) to reduce the interface trap density (Dit) is very critical. The lack of a high-quality IL can have detrimental consequences to the device performance in terms of subthreshold swing, reliability, and transport. More details on the gate stack for SiGe MOSFETs will be discussed in Section 6.6.

6.3 PLANAR AND FDSOI SiGe CHANNEL DEVICES There has been extensive research on planar SiGe devices, mostly for pFET over the past two decades. Various groups have reported transport enhancement

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by tensile strain for Si nFETs and compressive strain for SiGe pFETs, in either bulk or SOI substrates. On the other hand, it has been shown that electron transport in strained-SiGe nFETs is significantly degraded compared with Si that could not be justified by interface traps or higher contact resistivity and is attributed to the large electron conductivity and small density-of-state effective masses of SiGe [35]. Strained-Si substrates were fabricated by epitaxial growth of Si on relaxed buffer layers on bulk. For SOI wafers, the strained Si was formed on relaxed SiGe on insulator (SGOI) substrates or directly on insulator (sSOI or SSDOI) by bonding methods through removal of the relaxed SiGe buffer layer utilizing ion implantation [36] or etch-back techniques [27]. It has been shown that the electron mobility increases by increasing the virtual buffer Ge content to around 30% by a factor of 2
and saturates at strain levels above that. On the other hands, to achieve considerable hole mobility enhancement over Si, Ge fraction of near 30% or more is required, which is technologically very challenging due to the defectivity and cost [36,37]. To achieve bulk biaxial compressive strained-SiGe substrates, pseudomorphic growth of SiGe on Si or on strained-relaxed buffer (SRB) layers with lower Ge fraction has been widely demonstrated. For SOI-based substrates, various approaches have been practiced such as direct epitaxial growth of strained SiGe on SOI, bonding from a strained-SiGe/SRB substrates and etch back [37], or using thermal intermix or blanket Ge condensation [11]. Regardless of the fabrication process, as discussed earlier, it was shown that increasing the Ge content can increase the hole mobility [7,12]. In addition, (110) substrate orientation has been shown to provide considerable mobility benefit for holes over conventional (100) [38,39]. For such orientation and at 30% Ge, UMC researchers have shown 3.3
hole mobility and 81% short-channel (80 nm) current boost over (100) Si pFETs [40]. Tezuka et al. found for narrow-width SiGe devices (x ¼ 34%) where strain is mainly uniaxial that short-channel (L ¼ 40 nm) current enhancement factor surpasses the mobility enhancement ratio [41]. As scaled gate stacks are required for short-channel FETs, attempts to use high-κ dielectrics on SiGe MOSFETs ramped up in 2004, where sub-100 nm gate-length (LG) SiGe-channel pFETs with Ge content of 20% with 15% short-channel current benefit and great reliability were demonstrated using HfSiON/polygate stack [42]. For a bulk SiGe with 28% Ge and Si cap, Weber et al. showed mobility and short-channel (55 nm) current boost with HfO2/TiN in a gate-last flow [43]. Research on short-channel SiGe pFETs with higher-Ge content ramped up in 2010. Imec group demonstrated scaled 45% SiGe pFETs with high mobility at scaled EOTs (sub-1 nm) using Si passivation with gatefirst high-κ/MG technologies [44–47] and replacement high-κ/metal gate technology [48]. In addition, the impact of the device layout to dramatically boost the current drive at narrow channels was experimentally examined for Ge content in the range of 50%  5%, and record pFET current drive was demonstrated for narrow-channel uniaxially strained-SiGe pFETs [49–51].

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On the CMOS front and heterogenous integration, researchers from CEA LETI demonstrated dual-channel fully depleted (FD)-SOI CMOS with gate-first high-κ/metal gate technology and 20 nm gate length, featuring sSOI (20%) for nFET and higher-Ge-strained SiGe (40%–60%) on sSOI and enhanced electron and hole mobility [52]. In 2012, IBM demonstrated extremely thin (ET) SOI with 22 nm gate length, featuring unipolar SSDOI nFET and low-Ge-content SGOI pFET with performance competitive or better than the state-of-the-art bulk strained Si for nFET and pFETs, respectively [53]. Later, IBM also demonstrated a high-performance hybrid-channel ETSOI CMOS technology featuring SGOI pFET and SOI nFET, Si-cap-free gate-first high-κ/metal gate, and recess-free raised source/drain technology outperforming the AC performance of the state-of-the-art SOI FinFETs [54]. In addition, significant current drive enhancement (near +70%) was observed by shrinking the device widths to sub-100 nm regime due to the transformation of strain from biaxial to uniaxial strain. Later, the research alliance led by the STMicroelectronics group demonstrated a dualchannel ultrathin body and ultrathin buried oxide (UTBB) FD-SOI technology with excellent short-channel performance (20 nm) and reliability, for 14 nm technology and beyond [55,56]. In addition, the same group demonstrated an enhanced version of this UTBB technology with 20% tensile strained Si for nFET and 35% partially strained SiGe for pFET extendable to the 10 nm node [57]. From the manufacturing point of view, IBM has utilized planar SiGe in production for 32 and 22 nm high-performance partially depleted (PD)-SOI technologies [58,59]. Taking advantage of SOI technology with embedded DRAM, reliable product transistors with enhanced Si-cap-free high-κ/metal gate technology are being manufactured for IBM high-performance servers and systems. It was shown that the utilization of SiGe for pFET lowers the threshold voltage in the gate-first technology; enhances the pFET reliability; and, combined with embedded SiGe S/D, boosts the channel mobility especially at the narrow design widths.

6.4 STRAINED SiGe FINFETs Offering better electrostatics and gate control in the subthreshold operation, multigate devices such as FinFETs or nanowires allow further gate-length scaling that is indeed required as the contacted gate pitch size is aggressively scaled down. Combining a high-mobility material with a nonplanar architecture allows to further reduce the power supply (VDD) at a given off-state leakage (by adjusting the threshold voltage) to achieve similar performance. As mentioned earlier in this chapter, when biaxial compressive strained SiGe is patterned to highaspect-ratio patterns, such as fins, strain transformation occurs. The net uniaxial strain, if maintained through the device fabrication process, can provide the device with the optimum benefit for hole transport through the reduction of the effective mass. While increasing Ge content can further reduce the effective mass that is beneficial from a transport point of view, it generally leads to

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FIG. 6.4 Schematic of a proposed CMOS FinFET system on chip featuring strained-Si1xGex fins for high-performance logic pFETs and Si or strained-Si fins for high-performance logic nFETs. For high-voltage transistors such as I/O or ULP devices with very low-drain leakage requirements, Si or strained-Si fins are favorable due to their higher bandgap to offer lower leakage currents.

reduction of the bandgap, increased GIDL, and off current due to the increased band-to-band or trap-assisted tunneling. This brings up concerns for some CMOS applications, such as input/output (I/O) devices and ultra-low-power (ULP) transistors that are favorable for new emerging Internet of things (IoT) and mobile applications. Fig. 6.4 shows the schematic of a proposed CMOS FinFET system on chip (SoC) featuring strained-Si1xGex fins for high-performance logic pFET and Si or strained-Si fins for high-performance logic nFET. For high-voltage transistors such as I/O or ULP devices with very low-drain leakage requirements, Si or strained-Si channels are favorable due to their higher bandgap to offer lower leakage currents. There are few reports on the demonstration of strained SiGe in FinFET or a trigate architecture. Researchers from Toshiba demonstrated the first uniaxial strained SiGe on insulator pFETs in a trigate architecture, with a Ge content of 34%, a fin width of 55 nm, and medium gate lengths, down to 130 nm [13]. A transconductance (gm) enhancement of +200% was observed compared with (100) Si, due to the uniaxial strain and (110) dominating sidewalls. In addition, they observed up to +90% gm benefit over their control SOI FinFET at LG ¼ 400 nm. Later, utilizing hydrogen thermal etching, the same group fabricated higher-Ge-content (48%) strained-SiGe trigate pFETs with fin widths of 32–38 nm and + 60% hole mobility enhancement over Si fins [60]. However, poor subthreshold slope (500 mV/dec) was observed on those devices due to the relatively thick oxide with a high density of interface traps. On the other hand, CEA LETI demonstrated narrow-channel (W ¼ 55 nm) SGOI (35%) trigate PFETs with up to 2.8
long-channel mobility enhancement over Si and short devices down to LG ¼ 20 nm [52]. In addition, researchers of the SEMATECH consortium further investigated the transport properties of low-Ge-content strained SiGe (x ¼ 20%–25%) on insulator FinFETs at fin widths as small as 20 nm and gate lengths down to 40 nm, utilizing a gate-first

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high-κ/metal gate technology. Three approaches were used to fabricate fins, including Ge condensation and fin patterning, cladding SiGe epitaxy around the Si fins, and direct SiGe epitaxy on SOI followed by fin patterning [61,62]. As a result, they demonstrated near 16% on-current enhancement over SOI FinFETs at a fixed off-current and superior hole mobility above 300 cm2/Vs for (110)/(110) fins with either direct growth or Ge condensation. However, lower mobility was measured for the cladding SiGe approach partially due to the defectivity at the fin corners. Imec researchers also investigated the transport in cladding Si/45% SiGe layers grown on 20 nm-wide bulk Si fins [63,64]. While benefit in hole mobility was observed on these faceted structures, the scalability and performance benefit at aggressive gate lengths were not demonstrated. To further investigate the device characteristics of strained-SiGe FinFETs at aggressively scaled dimensions relevant to future technology generations, IBM researchers demonstrated devices with gate-first high-κ/metal gate and ionimplant-free raised source/drain technology with scaled fin widths down to 10 nm and gate lengths as short as 18 nm [65]. High-performance Si0.7Ge0.3 devices with great electrostatics were demonstrated. However, nonideal subthreshold slopes (SS) near 78 mV/dec were reported due to the relatively high density of interface traps. By optimizing the gate stack using an improved surface passivation process, near an ideal subthreshold swing as low as 65 mV/dec and short-channel mobility enhancement of 1.3
were achieved [66]. Fig. 6.5 illustrates the cross-sectional TEM images and transfer characteristics of aggressively scaled strained-SiGe FinFETs with physical LG  15 and 8 nm fin width (WFIN). The impact of the optimized Si-cap-free surface passivation on the linear SS is shown in Fig. 6.6A. In addition, the Ion  Ioff characteristics of s-SiGe FinFETs with regular and new passivation processes are shown in Fig. 6.6B. It can be observed that the new passivation process results in +20% short-channel Ion enhancement at a fixed Ioff thanks to the reduction in SS and

FIG. 6.5 (A,B) Cross-sectional TEM images and (C) transfer characteristics of aggressively scaled strained-SiGe FinFETs with physical LG 15 nm and WFIN 8 nm.

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FIG. 6.6 (A) Linear subthreshold slope (SSLIN) versus LG and (B) Ion Ioff characteristics of strained-Si0.7Ge0.3 FinFETs using standard and optimized interface passivation processes. The optimized Si-cap-free process results in noticeable SS reduction to 65 mV/dec and + 20% Ion enhancement at a fixed Ioff, leading to Ion ¼ 1.2 mA/μm at Ioff ¼ 100 nA/μm at VDD ¼ 0.9 V.

in part to the mobility enhancement. As a result, a record pMOS FinFET current drive of 1.3 mA/μm at Ioff ¼ 100 nA/μm was demonstrated in a gate-first flow. For FinFETs with high-Ge-content SiGe channels, the IBM research team also demonstrated aggressively scaled pMOS FinFETs, for the first time [18]. Using a two-step blanket Ge condensation on SOI substrates, nearly fully strained 50% SGOI was fabricated at a thickness slightly below 20 nm. A gatefirst process was developed, the gate stack was optimized, and devices with sub10 nm WFIN and gate lengths as short as 16 nm were demonstrated. Fig. 6.7A shows a TEM image of high-Ge SiGe FinFETs, across the fin direction. Hysteresis-free high-quality C-V characteristics with minimal frequency

FIG. 6.7 (A) TEM image of a 10 nm-wide high-Ge-content SiGe fin formed by planar Ge condensation and direct patterning. (B) Measured hole mobility (Ninv ¼ 1013/cm2) versus device/fin width for high-Ge-content FinFETs fabricated on 50% SGOI substrates. Mobility increases as the strain in the channel is transformed from biaxial to uniaxial compression.

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˚ . In addition, longdispersion were measured with inversion CET 15  1 A channel hole mobility was systematically studied for various device widths ranging from wide planar mesas to 10 nm-wide fins (Fig. 6.7B). It was observed that hole mobility increases as the device width is scaled down to 100 nm dimensions and relatively saturates at smaller widths. This is attributed to the transformation of strain from biaxial to uniaxial compression. High hole mobilities near 400 cm2/Vs have been achieved for high-Ge-content SiGe fins, showing enhancement of 5
/1.6
over (100)/(110) Si hole universal (100), outperforming the state-of-the-art Ge FinFETs. Furthermore, an analysis on the minimum drain leakage current at various supply voltages was conducted showing that the GIDL-dominated off-state drain leakage could be a concern for low-power applications, even at power supply voltage of 0.5 V. To surpass the fin height limitation associated with the low critical thickness of high-Ge-content SiGe, IBM researchers developed an enhanced 3D Ge condensation method using a low-temperature oxide hard mask deposition on lower Ge-content SGOI and fin patterning followed by an oxidation and oxide removal, as shown in Fig. 6.8. The final oxidation conditions such as temperature, nitrogen flow, and time were optimized to achieve fins with Ge content in the range of 65%–80% and vertical sidewalls [67]. Devices with a gate-first flow were fabricated, and the gate stack was optimized to achieve excellent SS ¼ 68 mV/dec and mobility of 300 cm2/Vs at Ninv ¼ 1013/cm2 for 70% Ge ˚ [68]. Short-channel devices were also demoncontent at a scaled EOT ¼ 8.5 A strated but their performance was relatively degraded due to their high series resistance. The high external resistance was attributed to the slow diffusion of boron in an ion-implant-free junction scheme with relatively thick spacer. Later, IBM demonstrated record SiGe short-channel performance with further EOT ˚ and junction engineering using ultrathin spacers, with scaling down to 7 A an Ion ¼ 0.45 mA/μm at equivalent Ioff ¼ 100 nA/μm at VDD ¼ 0.5 V [69]. Two schemes were used for the junctions: ion-implant-free and hot boron-implanted

FIG. 6.8 (A) Schematic of the enhanced 3D Ge condensation process to fabricate high-aspectratio high-Ge-content SiGe fins. (B) High-resolution scanning transmission electron microscope (HR-STEM) image of a sub-10 nm high-Ge-content Si0.3Ge0.7 fin formed by 3D Ge condensation after complete device fabrication.

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junctions. The results indicated that implant-free devices with ultrathin spacers could be beneficial to scale the physical gate length, much needed for very tight gate pitch, due to their better short-channel control and can offer competitive current drive at a fixed off-state leakage with sufficiently scaled spacer thickness. However, resistance variation mainly under spacer could be a concern for implant-free high-Ge-content devices that are processed at relatively low temperatures. Fig. 6.9 shows the transconductance (gm) characteristics of highGe-content SiGe devices with fins fabricated by Ge condensation and junctions formed by hot boron implantation. Record gate-first SiGe pFET gm as high as 2.7 mS/μm has been demonstrated, thanks to EOT scaling and reduction of the external series resistance. With the dominance of replacement high-κ and metal gate technology (RMG) in the mainstream CMOS, research on SiGe FinFETs has recently moved from gate first to RMG. IBM research and alliance have recently demonstrated dual-channel RMG CMOS featuring low-Ge SiGe (20%) for pFET and Si for nFET at 10 nm ground rules [70]. Various challenges have been overcome at such tight gate and fin pitches, such as defectivity, SiGe well corner rounding, strain maintenance, and gate stack. As a result, pFET performance enhancement of +17% at a gate length of 20 nm was demonstrated. For higher-Ge SiGe in an RMG integration flow, Imec demonstrated Si-cap-free Si0.55Ge0.45 FinFETs [71]. Though some improvements in the gate stack process were achieved, the fabricated devices suffered from relatively high SS (over 85 mV/dec). Later, IBM researchers developed an RMG high-Ge˚ [72]. content SiGe (x 67%) FinFET process with an aggressive EOT ¼ 7 A Record SS 67  1 mV/dec and very high-mobility numbers close to 300 cm2/Vs at sub-10 nm WFIN down to 3 nm were demonstrated, thanks to the improved gate stack process. 3000

3000 2500 gm (μS/μm)

Peak gm (μS/μm)

2500 2000

VDS = −1 V

2000 1500 1000

VDS = −0.05 V

500

1500

0 −0.7

1000 500

−0.2 VGS (V)

0.3

VDD = 1 V

0 0

1000 2000 Ron (Ω . μm)

3000

FIG. 6.9 Peak transconductance (gm) versus on resistance (Ron) for high-Ge-content SiGe FinFETs along with a gm VGS characteristics (inset). High gm over 2700 μS/μm is achieved by junction engineering and EOT scaling.

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6.5 Ge CHANNEL MOSFETs Possessing high electron and hole mobility, pure Ge is an attractive material for both n- and pFETs, and many research groups have shown superior transport properties for Ge substrates. However, as the melting temperature of Ge is much lower than Si, most Ge devices should be made at significantly lower temperature than Si. This may result in some penalty on performance and reliability of Si devices that require higher processing temperatures, especially for mobile and SoC applications. Moreover, compared with uniaxial strained-SiGe or strained-Si FinFETs, which can be processed at much higher temperatures, relaxed Ge generally does not provide a considerably better mobility, SS, and off-state leakage characteristics. In addition to many efforts to study and improve the quality of gate stack for Ge MOSFETs, there are few outstanding reports on the integration and scaling of Ge transistors, mainly for pFET and recently some for nFETs. The AIST group was among the first group to show scaled Ge MOSFETs. They reported a 60 nm gate-length planar pFET using Si passivation and SiO2 dielectric, at relatively thick EOT where electrostatics was significantly degraded at short gate lengths [73]. Imec then reported a 65 nm gate-length planar Ge pFET at an EOT ¼ 1.3 nm using monolayer Si cap passivation with a mobility around 200 cm2/Vs [74]. With further EOT scaling to 0.85 using thinner Si cap and HfO2, 40% current drive enhancement was achieved at LG ¼ 70 nm. The study of the intrinsic transport of these devices shows near 60% source injection velocity benefit over Si at LG ¼ 100 nm [75]. The aspect-ratio-trapping (ART) technique in narrow trenches was adopted by TSMC, and Ge pMOS FinFETs with 40 nm fin widths and 110 nm gate length were demonstrated using a Si cap passivation, for the first time showing longchannel SS ¼ 76 mV/dec and gm over 1 mS/μm [76]. With further scaling of the fin dimensions and proper control of the gate stack, TSMC researchers demonstrated 35 nm gate-length devices with record gm ¼ 2.7 mS/μm at an ˚ [77]. aggressive EOT ¼ 8 A On the other hand, strained Ge on SRB with high-κ/metal gate has shown significant long-channel mobility promises with either Si cap or O3 passivation processes [78,79]. Among the earliest reports on scaled strained-Ge channel MOSFETs, Intel has shown strained-Ge quantum-well pFETs (LG ¼ 100 nm) on 70% SRB using ultrathin Si cap and high-κ/metal gate with high intrinsic gm > 1.4 mS/μm and superior long-channel hole mobility [80]. The AIST group showed 4%-strained Ge nanowire FinFETs at LG ¼ 40 nm using implant-free NiGe source/drain and Al2O3 gate stack, with an intrinsic gm ¼ 1.2 mS/μm and reasonably low minimum drain leakage of 2.7 nA/μm [81]. Imec has developed a replacement fin process and demonstrated strained-Ge/SRB SiGe quantum-well pMOS FinFETs with Si cap [82]. With further improvement of the gate stack process in an RMG flow, devices with impressive peak gm ¼ 2.3 mS/μm were demonstrated at LG ¼ 65 nm and recently at the 45 nm

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fin pitch [83,84]. However, the minimum drain leakage of these devices is even higher than the target for high-performance applications, due to the very low bandgap of the strained Ge. Finally, there are recent attempts on the qualification of Ge FinFET for nMOS. One major problem is associated with the high contact resistance of the Ge nFETs that is orders of magnitude higher than that of Si. While substantial improvement in the contact resistivity and gate stack has been recently achieved, most reported nFET data are unsatisfactory. For example, recent reports on the scaled Ge nMOS FinFETs show poor gm 0.3 mS/μm that is significantly lower than that of pFETs [85,86]. More innovations and breakthrough are required to improve the characteristics of nFETs to achieve a homogeneous Ge CMOS.

6.6 GATE STACK REQUIREMENTS FOR SiGe-CHANNEL DEVICES As discussed earlier, an epitaxial SiGe channel (cSiGe) has been already implemented in recent CMOS technologies with gate-first planar device structures [58,59]. In this section, we review how the industry ended up using cSiGe for those technologies and extend the discussion to the requirements for metal gate effective work function (EWF) when Ge-based channels are introduced for a wider range of device architectures.

6.6.1 Work Function Requirements High-κ metal gate stacks tend to show EWF corresponding to near Si midgap after high-temperature processing irrespective of the work function of the metal electrode. This results in unacceptably high pFET threshold voltages for gatefirst integration where high thermal budget on the gate stack is unavoidable. This phenomenon is explained by the formation of positively charged oxygen vacancies in Hf-based gate dielectrics [87,88]. In order to achieve sufficiently low pFET threshold voltages, cSiGe was introduced selectively on the pFET channel area [89]. The impact of cSiGe on EWF control is schematically shown in Fig. 6.10 with band diagrams. The valence band offset between SiGe and Si increases the EWF (lowers the pFET threshold voltage) by >300 mV. This shift enables appropriate pFET EWF values (4.9 eV) required for highperformance and low-power CMOS devices, even with the presence of oxygen vacancies. Thus, cSiGe was originally introduced for the purpose of EWF control of pFET with gate-first high-κ metal gate stacks. On the other hand, gatelast high-κ metal gate stacks do not suffer from this issue since high thermal budget is not applied on the gate stack and it is possible to attain EWF around 4.9 eV using conventional metal electrodes, such as TiN, with Si channel [90]. Therefore, cSiGe has not been implemented for gate-last high-κ metal gate technology as of the 14 nm node. This poses a new challenge when SiGe or Ge

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FIG. 6.10 Band diagrams of Si and SiGe channels and requirements for effective work functions of high-κ metal gate stacks for NMOS and PMOS.

channels are considered for gate-last process to enhance the carrier transport. For example, if a TiN electrode (with an EWF on Si channel around 4.9 eV) is used in conjunction with cSiGe in a gate-last process, the EWF becomes 5.2 eV or higher, resulting in positive pFET threshold voltages. In fact, such normally on pFETs are common in literature for Ge-channel devices [76,77,82–84]. One way to solve this issue is to employ a low work function metal electrode for pFETs, which is typically used for nFETs with gate-last process and to counteract the threshold voltage shift due to the valence band offset of the channel materials. Al-containing alloys are typically used as work function setting metals for nFETs, and they are applicable to pFET with SiGe or Ge channels to attain appropriate threshold voltages [83].

6.6.2 Interfacial Layer Formation Formation of a high-quality interface with a low Dit on a channel material is crucial to attain steep subthreshold slope, high carrier mobility, and good device reliability. pFETs on SiGe or Ge channels tend to have higher Dit values compared with the ideal Si/SiO2 interface. In addition, Si and Ge are miscible over the complete range of compositions, which makes it difficult to employ a universally applicable high-κ stack. In recently years, there has been significant progress in the understanding of interfacial layer formation on SiGe channels with a wide range of Ge contents. The commonly observed Dit degradation for SiGe channels has been attributed to formation of undesired GedO bonds in the interfacial layer. Therefore, the ideal approach for low to middle Ge-content SiGe channels is to form a nearly pure SiO2 interfacial layer. This can be achieved by employing an epitaxially grown Si cap on top of a SiGe channel [46]. The drawbacks of this approach are the increase of EOT and challenges associated with the

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applicability to nonplanar structures, such as FinFET or gate-all-around devices. More recently, direct formation of pure SiO2 on SiGe channels has been reported by taking advantage of thermodynamics of oxidation/reduction of SiO2 and GeO2. This can be achieved by using selective oxidation of Si at a SiGe surface [91]. The other approach is to form a GedO containing interfacial layer first and to selectively scavenge (or remove) the GeOx later [92]. In both cases, GeOx-free interfacial layers are formed on moderate Ge-content (40%–50%) SiGe channels. The latter approach resulted in an interface trap charge (Nit) as low as 2
1011/cm2. On the other hand, if Si atoms are absent at a channel surface, such as pure Ge channels, different approaches need to be taken. For Ge-channel pFETs, the common approach is to form a high-quality GeO2 interfacial layer. Typically, suboxides of Ge are readily formed, but this can be avoided by a couple of different techniques. It was reported that a high-pressure oxidation (under 70 atm) of a Ge surface grows an ideal GeO2 layer, resulting in midgap Dit of 2
1011/cm2/eV [93]. The challenge of this approach is the EOT scalability since the formation of extremely thin GeO2 layer is difficult. Other groups reported the formation of an ultrathin GeO2 layer via plasma post oxidation (PPO) through an Al2O3 layer, and low Dit values were achieved with a scaled EOT [94]. The latter approach has become a mainstream approach to form a high-quality interface on Ge channels. IBM research has recently investigated applicability of postoxidation of Al2O3 via an O3 treatment on SiGe channels with a wide range of Ge content and has found that this approach is most effective for a very high-Ge-content SiGe (>90%). At low to moderate Ge contents, formation of SiGeOx layer limits the EOT scaling [95]. The impact of interfacial layer formation on device characteristics of highGe-content (70%) SiGe FinFETs was investigated in Ref. [68]. Since the interface states of SiGe trap the electrons, they shift the threshold voltage toward the positive direction. This can end up with positive pFET threshold voltages for devices with poor interface quality. Such situation can be avoided by reducing Dit, which is critical to achieve appropriate pFET threshold voltages. In addition, low Dit values enable steep subthreshold slopes closer to the ideal value of 60 mV/dec. Therefore, various interfacial layer formation processes are compared on a subthreshold slope versus threshold voltage plot in Fig. 6.11. It is shown that the threshold voltage is adjusted to appropriate values by optimizing the interfacial layer forming process, and near-ideal subthreshold slope values (68 mV/dec) are obtained at the same time. This highlights the importance of the interfacial layer formation on SiGe-channel devices. As reviewed above, the community has made significant progress in improving the quality of interfaces of Ge-based channel devices. The key consideration to achieve high-quality interfaces is the transition from a SiO2-based interfacial layer to a GeO2-based interfacial layer as the Ge-content of the SiGe channel is increased.

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FIG. 6.11 Subthreshold slope as a function of threshold voltage for high-Ge-content SiGe FinFETs with various interfacial layer and anneal processes. The inset shows a Z-contrast image of the fin sidewall with the optimized interfacial layer obtained by HR-STEM.

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