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Simulation of ultra thin film SOI transistors using a non-local ballistic model for impact ionisation
Solid-Stare Electronics Vol. 35. No. 12, pp. 1761.-1770, 1992 Printed in Great Bntain. All rights reserved
0038-l lOI: $5.00 + 0.00 Copyright i: 1992 Pergamon Press Ltd
SIMULATION OFULTRA THIN FILM SO1 TRANSISTORS USING A NON-LOCAL BALLISTIC MODEL FOR IMPACT IONISATION G. A. ARMSTRONG and W. D. FRENCH Department
of Electrical
and Electronic Engineering, Queen’s Belfast BT9 5AH, N. Ireland
University
Belfast,
(Received 29 February 1992; in revised form 31 Muy 1992) Abstract-To model bipolar snapback in thin film SOI transistors accurately, it is necessary to employ a non-local model of impact ionisation. Such a model, based on the “Lucky electron” theory, has been incorporated in a two-dimensional device simulator. Accurate prediction of bipolar holding voltage has been obtained for SOI transistors with sub-micron gate lengths. The model has been applied to analyse separately the effects of both lightly doped source and lightly doped drain in maximising the holding voltage. The advantage of using ultra thin highly doped SOI films in conjunction with a lightly doped drain is discussed.
NOTATION electronic charge electric potential dielectric constant of silicon donor concentration acceptor concentration hole density electron density electron current density hole current density carrier generation rate carrier recombination rate carrier diffusivity carrier mobility Boltzmann constant temperature intrinsic carrier concentration effective intrinsic carrier concentration bandgap narrowing ionisation coefficient for electrons ionisation coefficient for holes Chynoweth constant for electrons Chynoweth constant for electrons electric field threshold energy for ionisation threshold energy for phonon scattering distance mean free path ratio multiplication factor for current peak hole generation current channel current junction leakage current injected electron current bipolar current gain carrier mean free path
emitter doping base doping effective doping level
INTRODUfflON
In the design of silicon-on-insulator transistors, the maximum operating voltage is limited by bipolar
snapback[ I], which reduces the maximum operating voltage to a value less than that which can be achieved by conventional bulk technology. This problem originates from holes, generated by impact ionisation at the drain junction, raising the potential of the floating region sufficiently to forward bias the source junction. In order to optimise transistor design for sub-micron gate lengths, it is essential to be able to model correctly the action of the parasitic bipolar transistor along with the subthreshold leakage of the associated MOS transistor. The breakdown mechanism is similar to VcEo breakdown in bipolar transistors with a floating base region[2]. An analytical model of this in SOI transistors has been proposed[3], and a more comprehensive physical model, where values of bipolar gain are extracted from device simulations, described in [4]. In both cases it is assumed that the onset of bipolar breakdown occurs when the product of the bipolar current gain and the multiplication factor tends to unity. In general, previous theoretical discussion of bipolar induced breakdown in SO1 transistors has been applied to conventional transistor structures (non-LDD). This paper proposes a treatment of this topic based on an improved model of impact ionisation, which is incorporated in the two-dimensional simulator MINIMOS[S]. This model is shown to be equally applicable to both lightly doped drain (LDD) and non-LDD transistors. The simulator is used to identify the relative significance of each mechanism to the onset of snapback. Simulated values of bipolar holding voltage are shown to compare favourably with measurements. A simple model of impact ionisation involves an exponential dependence of the ionisation rate for each carrier on the local electric field. This model is generally only valid for a limited range of values of 1761
G. A. ARMSTRONG and W. D. FRENCH
1162
electric field. The improved model of impact ionisation is based on the “Lucky electron” theory[6]. The advantage of using this type of model is it provides a more accurate physical description, whereby the ionisation rate at a given point is defined, not by the local electric field, but by the increase in carrier energy. The increase in energy is calculated by integrating the electric field back along a path normal to equipotential contours which defines the carrier trajectory in reaching that point[7]. In a bipolar transistor the current gain is strongly influenced by bandgap narrowing in the emitter region[8]. In an SO1 transistor which is liable to snapback. bandgap narrowing in the source region has a beneficial effect as it serves to reduce the injection of minority carriers. Nonetheless, it is important to model this mechanism accurately to obtain the correct balance between generation of holes in the drain region and recombination at the source junction. if an accurate prediction of the holding voltage is to be found. Choice of carrier recombination lifetime also has a significant influence on the bipolar gain. Once a physically accurate model is established, the options available to maximise the range of operating voltage of SOI transistors via both source and drain engineering can be considered. Three possible options are considered individually: (a) a body contact; (b) a lightly doped source; (c) a lightly doped drain.
The technique for simulation of bipolar snapback involves turning on the transistor with a small positive gate voltage at high drain bias. and then perturbing the solution by stepping down the gate voltage in small increments. The holding voltage, referred to in subsequent sections of this paper, is defined as that value of drain voltage at which the device fails to turn off. An example of a simulation illustrating snapback is indicated by the gate voltage characteristics in Fig. 1. In this instance the holding voltage for a 1 pm gate length non-LDD transistor is considered to be 4.6 V, since this represents the maximum voltage at which the transistor will just turn off. Although the simulation indicates a steep but finite subthreshold slope at a drain voltage of 4.6 V, precise measurement of subthreshold slope in this condition is difficult to carry out, as the device is in an unstable condition and tends to switch abruptly from an “on” (bipolar) state to an “off’ (subthreshold MOS) state. Nonetheless simulations of this kind are a useful indicator of the likely onset of snapback, provided an accurate balance between carrier generation at the drain and recombination at the source is used. A recent enhancement of the simulator[l I] to improve the modelling of the bipolar effect has been the inclusion of a model for bandgap narrowing. The inclusion of such a model modifies the form of the current flow equations such that: J,,=qD,Vn
-qnp,,V$
-p,,nkT.V
(4)
By examining the feasability and relative merit of each of these possibilities, an insight into the range of options that are available for a particular process to maximise the breakdown voltage is obtained. TWO
DIMENSIONAL
MODELLING
The two-dimensional device finite difference simulator MINIMOS4[5] has been adapted in order to simulate bipolar snapback in thin film SO1 MOSFETs[9]. In its original form this package solves Poisson’s equation, and the hole and electron continuity equations: V’I/? = -y(N,-
N,+p
V,J,=q(G V’J,,=
-y(G
-R) -R).
-n);~,
(5) The variation of effective intrinsic concentration with bandgap shrinkage AE, is given by
n,,
ni = nz exp(AE,ikT).
(6)
For heavily doped n-type material in excess of a reference level Nrer of 7 x IO” cm ‘. the experimental Drain
10-‘1
(1) (2) (3)
The techniques for solution of these equations and full descriptions of parameter models have been fully described[lO]. The advantage of using MINIMOS, as opposed to other two-dimensional simulators, is the simplicity of its input data format, availability of simplified process specification, ability to easily modify device geometry and the capability of automatic mesh generation. This allows design optimisation to be carried out in an economical manner. with only minimal change to the input data file.
,o-lo~ 10
-12
i
lo-l4 ’ -1
1
x
,,d
fi
/I
+
I’
)X
cd
+
Vd=4.*”
-8
“d=4.4”
*
“d=O.lV
x i
-0.75
-0.5
-0.25 Cat2
0
0.25
Voltage
(V)
0.5
0.75
I
Fig. 1. Simulated variation of drain current wth gate voltage and different drain biases for a I pm non-LDD transistor with a film thickness of 0.2 pm, a film doping of 3 x 10’bcm~q and a 20 nm gate oxide.
Simulation of ultra thin film SOI transistors data of de1 Alamo and Swanson transistors has been approximated, meV according to:
[12] for bipolar to give A& in
A& = 18.7 ln(lNd - Nal/N,,r).
(7)
Inclusion of such a model has no effect for MOS simulations, but has a significant effect on the prediction of the onset of snapback. Measurements of the intrinsic carrier lifetime may be made using relatively small SOI transistors based upon a method outlined in [13]. Further work has shown that when these results are combined with established generation-recombination theory[2], intrinsic carrier lifetime of approximately 2 x IO-' s are obtained. This value of the intrinsic carrier lifetime in thin SO1 films was introduced into the program and combined with a doping dependence as suggested in [14]. The generation of carriers by impact ionisation is linked to the current density by: G =~~.lJ,J+tlp.IJ~l
(8)
where tl, and ap are the respective ionisation coefficients of electrons and holes. In an n-channel transistor only the contribution due to tl, is significant. Previous modelling of impact ionisation in SO1 transistors[9] was based on the application of Chynoweth’s Law with optimised coefficients[l5] according to: u, = A,exp(-B,/e)
(9)
where the electric field t is defined locally at each mesh point. It has been found that accurate prediction of bipolar holding voltage[ 151 in non-LDD can be achieved using optimised transistors and B, = 1.9 x A, = 3.2 x lo6 cm-’ coefficients, lo6 V cm ’ respectively. While a significant spread exists in the range of values for these coefficients which are quoted in the literature, the latter coefficients are very close to the corresponding respective values of 2.5 x lO”cm-’ and 1.9 x 106V. cm-’ specified by Slotboom [16], from measurements of surface breakdown in gate controlled pn junctions. The numerical algorithm implemented in MINIMOS is based on a sequential solution of (l)-(3), using the step solving approach described in [17]. Initially the Poisson equation is solved assuming fixed quasi-Fermi levels for both electrons and holes. When convergence of the non-linear Poisson equation is achieved, the potential is substituted into the electron continuity equation which is linear and can be solved directly. When (I) and (2) have converged, (3) is introduced into the iteration loop with the generation term G set to zero. Finally the generation term G is computed and included in the right hand side of (2) and (3). In this way the impact ionisation current is calculated self consistently and the effect of the floating region potential is correctly modelled. When the term G becomes significant for high values of generation current, coupling between (2) and (3)
1763
becomes strong and overall convergence of the outer loop is degraded. At this stage only one update of the potential is made for the non-linear Poisson equation followed by successive solution of (2) and (3). This allows overall convergence to be achieved in a reasonable number of iterations (typically less than 50), without the overhead involved in a fully coupled solution of (l)-(3). Particular care has been taken only to update G when the relative change in terminal current in successive iterations is less than 1%. In order to resolve known problems of ill-conditioning of the equations[ 18,191, due to the presence of the floating region, a direct solver based on Gauss elimination is used for solution of (2) and (3), while the ICCG method is appropriate for the solution of (1). While reasonable accuracy can be achieved using appropriate coefficients A, and E, for a particular structure, it has been established that greater accuracy and wider applicability is achieved if the ionisation coefficients are calculated using a nonlocal implementation of Shockley’s “lucky electron” theory[6]. This introduces significant additional complexity in the software implementation, but leads to a more unified treatment which is equally applicable to both LDD and non-LDD transistors. In his original work, Shockley calculated the probability that a carrier will reach the threshold energy for ionisation E,, in travelling through a region of high electric field t, over a distance E,/(qc), without suffering phonon scattering, i.e. the probability of avoiding momentum relaxing collisions. By relating this probability to the mean number of phonons created per ionisation, r, and the distance required for phonon scattering E,,/(qt), Shockley determined a formula for the ionisation coefficient of the form: a=$&exp OP
E,
( > -1
%p 6
where I (= 17.5) is the fixed ratio of mean free path for impact ionisation to mean free path for phonon scattering. Assuming a homogeneous electric field, then d, = E, /qc and dop = Eop/qc and equation (IO) becomes 1
r=-.-exp
I
(11)
r 4,
This equation is similar in form to (9). However in a varying electric field such as exists in the drain region of an SO1 MOSFET, a carrier will gain energy nonlinearly along its trajectory. A non-local calculation of both d, and dop is required, treating the carriers ballistically, so that at any point the energy gained by the carrier is found by integrating the electric field from this point, back along the carrier trajectory. The precise trajectory can be found from the electric field lines calculated by two-dimensional simulation. For impact ionisation to occur the carrier must travel a distance d,, such that E, = q
(12)
G.
II64
A.
ARMSTRONG and
This is equivalent to calculating the distance along the carriers trajectory over which the potential changes by E,/q (1.1 V for an electron). The value of doP is calculated similarly. This method of estimating ionisation rate allows for large rates of change in the electric field over a short distance, such as occurs at pn junctions or even between II and n + regions. In these cases a local model tends to overestimate the ionisation rate, as it assumes that the electric field is high over the entire distance d,. and thereby underestimates this distance. ESTIMATION
OF BIPOLAR
CURRENT
I, = ( A4 - 1) (I& + I, + I, )
Ida = M
(13)
has a gain fl so that
I,=B~U,+I,) then the total drain current
(14) must become
(I,,, + I, + I, 1.
(15)
By combining equations (13-l 5). a theoretical estimate of the equivalent bipolar current gain has been given[4]. such that:
p=
L - M (Ich+ I, ) &j;(M-l)+MI,’
Fig. 2.
Currents Rowing in a
,I
Hole
1
FRENCH current (n.4)
source
Iunction
Drain JUnEtion
GAIN
Because of the floating region, the current flow in an SOI transistor at the onset of snapback is similar to that of a bipolar transistor with open circuit base. Figure 2 depicts the various currents that are found to flow. Idr is the total drain current, I,,, is the front channel current, f, is the leakage current at the drain junction (no impact ionisation), Ig is the peak hole current due to impact ionisation and 1, is the current injected into the base across the emitter-base junction. If it is assumed that the hole current generated by impact ionisation is related to the total current flowing into the drain by the multiplication factor M such that
and the lateral bipolar transistor
W. D.
SO1 MOSFET.
(16)
Fig. 3. Generated hole current vs position normalised to the source gate edge at V, = 3 V and V, = 0 V. for a 0.5 pm non-LDD transistor with a film thickness of 0.1 pm. a film doping of 1.1 x lO”cmand a 14 nm gate oxide.
As suggested in [4], equations (15) and (16) can be used in conjunction with the two dimensional device simulator to calculate values of/j’ and M for an SOI transistor using simulated values of the respective currents I,,, I,, I,Fand I,. The peak hole generation current Z, is found by simulating the device including impact ionisation and integrating the hole current through the entire film thickness. The channel current I,.h at a specific gate voltage is found by simulating with the impact ionisation model turned off. The junction leakage current I, may be found by simulating without impact ionisation at zero gate voltage. By way of illustration Fig. 3 shows a plot of the variation of simulated hole current within the thin SOI film, as a function of distance referenced to the edge of the gate. It should be noted that the peak current I, occurs, not in the drain region alongside the peak electric field, but within the channel at a point where the generation rate and recombination rate precisely balance-i.e. G - R = 0 in (3).
ANALYSIS
OF IMPACT
IONISATION
MODELS
Some success in modelling the variation of bipolar holding voltage with gate length can be achieved using Chynoweth’s law with optimised coefficients to calculate impact ionisation coefficients, as shown in Fig. 4. The measured results were obtained for a batch of n-channel transistors fabricated using SIMOX technology where the equivalent of 1.8 x IO” 0’ ions/cm’ were implanted at an energy of 200 keV, followed by an anneal at I300 C for 6 h. The gate, buried oxide and SO1 film thicknesses were 20. 400 and 200 nm respectively. No LDD implant was used, and the threshold adjust implant gave a nominal threshold voltage of I V. It is clear that with an appropriate choice of coefficients, an accurate prediction of holding voltage over dimerent gate lengths is possible. The simulated dependence of holding voltage on the chosen carrier lifetime is shown in Fig. 5, both with and without an LDD imnlant. The oredicted increase in holding
1765
Simulation of ultra thin film SO1 transistors
+ ++ .
++
LDD
0
0.5
1
1.5 2 2.5 Cats Length (Microns)
3
voltages for non-LDD 0.2pm, a film doping
transistors with a film thickness of of 1.5 x 10” cme3 and a 20 nm gate oxide.
voltage with decrease in lifetime is due to the reduced diffusion length of carriers injected across the source junction, while the use of an LDD implant is due to the reduced field in the drain region. In order to compare the “local” and “non-local” models of impact ionisation, some simulations of substrate current in bulk MOSFETs were carried out. The ratio of peak substrate current to drain current was measured, for a range of bulk MOSFETs with differing gate lengths. As is clear from Fig. 6, it is not possible to fit simultaneously the experimental measurements of both LDD and non-LDD transistors, using a “local” model of impact ionisation, even if the coefficients specified previously are used. If, however, the non-local model with a constant carrier mean free path A,, of 8.9 nm is used, a much better fit to the measured results is obtained for both cases, and is applicable for gate lengths exceeding 1 pm. This value of I,, compares favorably with the value of 9.1 nm found by other authors[20,21]. It is clearly much more difficult to assess the accuracy of the improved model for SO1 transistors, since it is not easy to measure either the bipolar gain
T
1
3.5
Fig. 4. Comparison of simulated and measured holding
t 1.2 Gate
Length
1.4
w, 1.6
i 1.8
(micron)
Fig. 6. Ratio of bulk to drain current vs gate length for measured (solid lines) and simulated (points) devices, using Chynoweth’s law (.) and a nonlocal Shockley method with constant (+) and field dependent (*) optical mean free paths. The film doping was 3 x lOI cm-’ with a 27 nm gate oxide and the LDD consisted of a 1 x 10’) cm-* n implant with a 0.25 pm oxide spacer.
or the ionisation rate. We have, however, used the simulator to compare the simulated bipolar holding voltage for a 0.8 pm gate length LDD transistor to measured results[22], as shown in Fig. 7. Once again the thin film SOI transistors were fabricated on SIMOX material. On this occasion the devices employed p + polysilicon gate and a gate overlapped LDD was included to reduce the drain field. In Fig. 7 a positive value of channel doping indicates a p-type doping, while a negative value indicates an n-type doping. It is clear that when the model of bandgap narrowing is included, an improved prediction of the bipolar holding voltage is obtained. If bandgap narrowing is omitted from the simulation, the bipolar current gain is greatly overestimated and results in much lower values of the simulated holding voltage. The estimated bipolar current gain of the SO1 transistor was calculated from detailed simulations of the various current components as defined in (16). The reduction 2 Holding I
,-
Voltage
(V)
current
Gain 3103
I
104
6-
S-
4-
1 I 103
109
3-
Fig. 5. Dependence of holding voltage on carrier lifetime for a 0.5 pm transistor. with and without a LDD, a tilm thickness of 0.1 pm and a film doping of I.1 x 10’7cm-3. The LDD comprised a 1 x IO”cm-’ n- implant and a 0.25 Frn oxide spacer.
Fig. 7. Measured (thick line) and simulated results with (+) and without (m) bandgap narrowing for a constant optical mean free path and with bandgap narrowing for a field dependent optical mean free path (*). The device comprised a 0.8 pm gate length, a 0.08 pm film thickness, a n implant dose of 5 x IO” cm-’ and a 0.25 pm spacer.
G. A. ARMSTRONG and W. D. FRENCH
1766
shown in the bipolar current gain associated with increased doping in the SOI film, arises due to an increase in effective base doping of the lateral bipolar transistor. The use of a constant value for the optical mean free path tends to overestimate the holding voltage for film doping > 10” cm-3. The reason for this is that the electric field profile in a thin film SOI transistor is high throughout the film, unlike a bulk transistor where it peaks close to the oxide interface. This is clear from Fig. 8 which compares the electric field contours in the drain region of two SOI transistors for film thicknesses of 0.05 and 0.15 pm respect-
ively. For the thinner film, the high lateral electric field extends throughout the film, whereas for the thicker film, the field peaks within the drain region close to the gate oxide interface. Initial estimates of E.,, were based on measurements taken from bulk transistors where the field profile is comparable to that shown in Fig. 8(b). Because of the different field pattern associated with the ultra thin film, this constant value of &, does not fit the measured variation of holding voltage for SO1 devices. Hence a spatially varying value of A,,, very similar to one used in [7], is required to accurately reproduce the variation in holding voltage with film doping. Detailed
I
.8
.7
.9
1
MICRON ELtCTRlC
I- IEI
0
(LHTERHIL)
I
.7
I
.I3
.9
--,--7
1
MICRON
(b) Fig. 8. Lateral electric field profiles at V,, = 3.5 V. V, = 0 V for a I pm gate length non-LDD transistor with a 20 nm gate oxide, a film doping of 3 x IO” cm-’ and film thickness of (a) 0.05 pm and (b) 0.15 /cm.
Simulation of ultra thin film SOI transistors simulations have suggested a dependency of &,, on trajectory path length d,, according to: &=
IO-5exp(-d/100)
OF THE BIPOLAR HOLDING
Voltage (V)
(17)
where all constants are expressed in nm. This appears to be an optimal model valid for both sub-micron SO1 and bulk devices respectively. Making A,,,dependent upon di implies that A,,, is indirectly dependent on the electric field along the carrier trajectory. This is a more physically meaningful relationship in line with the energy dependent optical mean free path model described in [23]. Only with this model can an accurate prediction of both the holding voltage in SOI transistors, and substrate current in a bulk transistor be obtained, for the same set of model parameters, as shown in Figs 7 and 6 respectively. OI’TIMISATION
5Edding
1767
VOLTAGE
From the literature it is clear that there are 3 basic methods that may be used to improve the holding voltage of SO1 transistors: (a) an extra contact to the SO1 film, a “body” contact, to remove holes generated by impact ionisation at the drain and so prevent the bipolar transistor from turning on; (b) drain engineering to reduce the peak electric fields at the drain and thereby reduce impact ionisation rate; (c) source engineering to reduce the current gain /I of the transistor so that higher drain voltages are required before /?(M - 1) + 1. These points are addressed in the following simulations. In all subsequent simulations we consider the specific case of a transistor with a gate length of 0.5 pm, an oxide thickness of 14 nm and a film doping chosen to give threshold voltage of 0.6V. (a) Body contact
The effect of a body contact has been simulated by allowing the source contact to extend below the level of the oxide interface to such an extent that it eventually contacts the SOI film directly, if the junction depth is less than the film thickness. Figure 9 shows the reduction in current gain and the associated increase in the holding voltage, as the distance from contact to metallurgical junction is progressively reduced. The reduction in current gain can be readily explained by the associated reduction in the diffusion length of holes[2]. Although the simulation represents a highly ideal situation not readily achievable in practice, controlled silicidation of the source can be used to achieve the same effect. Indeed, experimental results have confirmed an increase in the holding vohage[24] in such devices. However, this type of contact is only feasible when used with thicker films and the trend towards ultra-thin SO1 films will require other methods of maximising the holding voltage.
+
-
/
J
Holdin
Volta2s
currentCain
..:ii”\----_l:“” 0
0.1
0.2
contact
-
0.3
Junction
0.5
0.4
2epu.tion
(microns)
Fig. 9. Simulated variation of holding voltage and current gain with distance from the source contact to the junction for a 0.5 pm non-LDD transistor with a film thickness of 0.1 pm and a film doping of 1.1 x 10” cm-‘. (b) Lightly doped source
The bipolar current gain /.I is known(2] to depend upon the ratio of source (emitter) doping to film (base) doping. It is therefore obvious that low source and high film doping is desirable in SOI transistors. Figure 10 shows the simulated increase in holding voltage and the change in current gain which can be achieved by lowering the source implant dose, whilst keeping the drain implant dose constant. In this case there is no spacer region. By reducing the source implant from 5 x 10” to 1 x 10’) cmm2, an increase in the holding voltage of more than 1 V is predicted. The corresponding reduction in gain is partially offset by a reduction in bandgap narrowing, which is taken into account in the simulation. In practice, however, to achieve such a significant improvement, it is necessary to utilise an unrealistically low value of peak source doping i.e. less than lO’acm--‘, as opposed to a typical value of 1020cm-3. Even in a structure that employs some form of spacer, it is not possible to achieve an order of magnitude reduction in effective doping, because of the combined effect of the n + and n - regions. For example, in a device with an n - implant dose of 5 x lOI cmm2 and a 0.25 pm 4,5Holding
vo1t*ge
current
Vi-l(V)
Cain
700
-Vh 4-
+
, 1013
/
Id4
I,
I,
1015
,
Bet.
- 800 *eta
,uJ
I,,
lOI@
10IY
sourceImplant nome(crtr2)
Fig. 10. Simulated variation of holding voltage and current gain with source implant dose, with a constant drain implant dose of 5 x 1015cm-2, for a 0.5 pm non-LDD transistor.
1768
G. A. ARMSTRONG and W. D. FRENCH
spacer, simulation may be used to show [see Appendix I] that when bandgap narrowing is taken into account, the injection of carriers still occurs from an effective source doping of greater than 1 x 10” cm 3 despite the presence of the lightly doped region. (c) Light/J, doped druin The improved holding voltages with increased film doping shown in Fig. 7 can be used together with a lightly doped drain to maximise the holding voltage for ultra thin films as low as 50 nm. as shown in Fig. I I. For the two different film thicknesses, the film doping in each case has been chosen to give a threshold voltage of 0.6 V. Significantly, the thinner film with a doping of 2.5 x 10”cm-‘, has a higher maximum holding voltage than the thicker film device with a doping of 1. I x 10” cm- 3. This increase can be partially attributed to the reduction in bipolar gain associated with increased film doping. A further contributory factor, however, for an LDD transistor, concerns the effect of thinning the SOI film, which reduces the peak field strength in the n lightly doped drain. Figure 12 shows the dependence of peak lateral electric field for two film thicknesses, both with and without an LDD implant. For the non-LDD transistor shown in case (a), the higher peak field occurs for the thinner film, and increases with film doping, as reported in [25]. If these calculations are repeated, at the same gate length and bias condition, but including an LDD region, the variation of peak field with film thickness and doping exhibits a significantly different pattern, as shown by case (b). In this case the peak lateral field for both film thicknesses occurs within the depleted LDD region. As the SOI film doping is increased, the peak field associated with the thicker film increases more than the peak field associated with the thinner film, which remains independent of doping. This behaviour is a result of the thicker film becoming partially depleted for doping > 1.5 x lO”cm m3. The thinner film would also exhibit the same effect but now for doping greater than
Fig. 12. Variation in peak lateral electric field versus SO1 film doping for a 0.5pm gate length transistor. with and without a LDD, at VP = I V for a film thickness of 0. I pm (.) and 0.05 pm (+). The LDD comprised a 0.25 /urn spacer and a n implant dose of I x IO” cm ‘.
5 x 10” cmm3. This pattern is even more pronounced at a higher drain voltage, when there is now a significantly lower peak field for the thinner film, regardless of the doping level. The reduced electric field in case (c), however, now occurs because the thinner film gives rise to a much greater lateral spreading of the depletion region within the LDD, since the depletion in the transverse direction is limited by the film thickness. This point is evident from the plots of electric field contours in Fig. 13 where there is increased separation of the contour lines for the thinner film, and a corresponding reduction in the peak field from 3 x 10’ to 2.6 x lo5 V cm-‘. Finally, case (c) of Fig. 12 shows a small reduction in the electric field with increased doping. Simulations have shown that this is a result of fewer electric field lines from the drain terminating on the gate. A more uniform electric field profile is obtained and consequently a slightly lower electric field strength. CONCLUSIONS
In order to correctly estimate the bipolar holding voltage of thin film SO1 transistors with sub-micron gate lengths, it is necessary to obtain the correct balance between the bipolar current gain and impact ionisation. The bipolar current gain was found to be dependent upon bandgap narrowing in the heavily doped source, whilst impact ionisation may be accurately modelled only with a non-local ballistic model. The limitations of the model of impact ionisation, based on the “local” electric field were found to be essentially twofold:
Fig. I I. Simulated variation of holding voltage with II implant dose for a 0.5 pm transistor with a 0.25 /urn spacer and two film thicknesses. keeping the threshold voltage constant at 0.6 V.
(a) different for bulk (b) different for LDD
ionisation constants arc required and SO1 devices; ionisation constants are required and non-LDD devices.
A more generally applicable method was obtained when the non-local impact ionisation model was
Simulation
.3
of ultra thin film SO1 transistors
.4
.5
1769
.6
.7
MICRON ELECTRIC
FIELD
(LFITERAL)
(a)
-PN-JUNCTION
I
.2
.3
.5
.4
.6
.7-
MICRON ELECTRIC
FIELD
(LATERFILl
(b) Fig. 13. Lateral electric field contours in the n - region of a 0.5 pm transistor with a 0.25 pm spacer, n- implant dose of 1 x 10’3cm-’ and film thicknesses of (a) 0.1 pm and (b) 0.05 pm.
combined with an electric field dependent optical mean free path length. Simulation suggests that optimal engineering of both source and drain regions is necessary to maximise the bipolar holding voltage. The use of a symmetrical LDS/LDD structure with a spacer reduces the impact ionisation in the drain. However the presence of the spacer region in conjunction with a heavily doped source tends to limit the achievable reduction in effective emitter doping. Simulations of a lightly doped drain structure suggest that thinning the SO1 film gives rise to an unexpected reduction in the lateral electric field in the
a
n- drain region. This occurs because of increased lateral spreading of the drain depletion region when bounded by the buried oxide. Hence an ultra-thin highly doped film, with an optimised LDD, appears to be the optimum combination to maximise the bipolar holding voltage. Indeed with this combination, a maximum holding voltage in excess of 6.5 V has been simulated in a 0.5 pm gate length SOI transistor. Acknowledgemenfs-The authors support from the Procurement Defence (RSRE) and the U.K. Research Council.
acknowledge the financial Executive, Ministry of Science and Engineering
G. A. ARMSTRONG and W. D. FRENCH
1770 REFERENCES
Technology: Ma1. J. P. Colinge, Silicon-on-Insulator terials to VLSI. Kluwer Academic Publishers (1991). Devices. Wiley, 2. S. M. Sze, Physics of Semiconducfor New York (1981). 3. K. K. Young and J. A. Burns, IEEE Trans. Electron. Device ED-35, 426 (1988). 4. J. Y. Choi and J. G. Fossum, IEEE Trans. Electron. Device ED-38, 1384 (1991). 5. S. Selberherr et al., IEEE Trans. Electron Device ED-27, 1540 (1980). 6 W. Shockley, Solid-St. Electron. 2, 825 (1961). 7 T. Thuraate and N. Chan, IEEE Trans. Electron. Device ED-32,200 (1985). Bipolar Semiconductor Devices. 8 D. J. Roulston, McGraw-Hill, New York (1991). et al., IEEE Trans. Electron Device 9 G. A. Armstrong ED-38, 328 (1991). IEEE Trans. Electron. Device ED-36, 10 S. Selberherr, 1464 (1989). and W. French, Proc. INFOS, LiverII G. A. Armstrong pool, pp. 335-338 (1991). 12. J. de1 Alamo et al., IEDM Tech. Dig., pp. 290-293 (1985). and P. E. Belk, Proc. IEEE SOSjSOI 13. P. C. Karulkar Tech. Conf., Fla, pp. 139-140 (1990). and J. Kerr, GPS Marconi. Lincoln, 14. D. Kimpton private communication. et al.. Proc. IEEE SOSISOI Tech. 15. G. A. Armstrong Co& Nevada, pp. 4445 (1989). 16. J. W. Slotboom et al., IEDM Tech. Dig., pp. 494497 (1987). 17. K. Kato et al., IEEE Tram Electron. Device ED-32, 458 (1985). 18. R. Rios et al., IEEE Tram Electron. Device ED-39, 581 (1992). 19. S. Edwards et al., IEEE Tram Electron. Device ED-35, 1012 (1988). 20. T. H. Ning el al., J. uppl. Phys. 48, 286 (1977). 21. S. Tam et al., IEEE Trans. Electron. Device ED-31, 1 I16 (1984).
22. Y. Yamaguchi et al., IEDM Tech. Dig., pp. 591-594 (1990). 23. Y. Z. Chen and T. W. Tang, J. qpl. Phys. 65, 4279 (1989). 24. H. Lifka and P. H. Woerlee. Pro<,. ESSDERC. Nottingham, pp. 453 -456 ( 1990). 25. M. Yoshimi et al., IEEE Trans. Eleclron. Device ED-37, 2015 (1990). APPENDIX
I
It has been established[2] that for an abrupt junction, the bipolar current gain may be approximated by the emitter and base doping, according to: (Al) Therefore, using the values of current gain, both with and without bandgap narrowing, shown in Fig. 7. for a base doping of I x 10” cm-‘, we obtain:
It has also been shown[8] that bandgap narrowing may be viewed as introducing an “effective” doping level according to: N,,=N,exp(-AE,,kT).
(A31
Assuming therefore that injection of carriers from the emitter into the base is unaffected when bandgap narrowing is included, then equation (A2) becomes:
3 AE, = 0.0596 eV.
(.45)
Using equation (7), this value of bandgap narrowing corresponds to an effective doping in the composite emitter (comprising n + and n regions) of I .7 x 10’Ycm~’ rather than the actual doping level of 5 x lO”cm ’ in the II region.
0038-l lOI: $5.00 + 0.00 Copyright i: 1992 Pergamon Press Ltd
SIMULATION OFULTRA THIN FILM SO1 TRANSISTORS USING A NON-LOCAL BALLISTIC MODEL FOR IMPACT IONISATION G. A. ARMSTRONG and W. D. FRENCH Department
of Electrical
and Electronic Engineering, Queen’s Belfast BT9 5AH, N. Ireland
University
Belfast,
(Received 29 February 1992; in revised form 31 Muy 1992) Abstract-To model bipolar snapback in thin film SOI transistors accurately, it is necessary to employ a non-local model of impact ionisation. Such a model, based on the “Lucky electron” theory, has been incorporated in a two-dimensional device simulator. Accurate prediction of bipolar holding voltage has been obtained for SOI transistors with sub-micron gate lengths. The model has been applied to analyse separately the effects of both lightly doped source and lightly doped drain in maximising the holding voltage. The advantage of using ultra thin highly doped SOI films in conjunction with a lightly doped drain is discussed.
NOTATION electronic charge electric potential dielectric constant of silicon donor concentration acceptor concentration hole density electron density electron current density hole current density carrier generation rate carrier recombination rate carrier diffusivity carrier mobility Boltzmann constant temperature intrinsic carrier concentration effective intrinsic carrier concentration bandgap narrowing ionisation coefficient for electrons ionisation coefficient for holes Chynoweth constant for electrons Chynoweth constant for electrons electric field threshold energy for ionisation threshold energy for phonon scattering distance mean free path ratio multiplication factor for current peak hole generation current channel current junction leakage current injected electron current bipolar current gain carrier mean free path
emitter doping base doping effective doping level
INTRODUfflON
In the design of silicon-on-insulator transistors, the maximum operating voltage is limited by bipolar
snapback[ I], which reduces the maximum operating voltage to a value less than that which can be achieved by conventional bulk technology. This problem originates from holes, generated by impact ionisation at the drain junction, raising the potential of the floating region sufficiently to forward bias the source junction. In order to optimise transistor design for sub-micron gate lengths, it is essential to be able to model correctly the action of the parasitic bipolar transistor along with the subthreshold leakage of the associated MOS transistor. The breakdown mechanism is similar to VcEo breakdown in bipolar transistors with a floating base region[2]. An analytical model of this in SOI transistors has been proposed[3], and a more comprehensive physical model, where values of bipolar gain are extracted from device simulations, described in [4]. In both cases it is assumed that the onset of bipolar breakdown occurs when the product of the bipolar current gain and the multiplication factor tends to unity. In general, previous theoretical discussion of bipolar induced breakdown in SO1 transistors has been applied to conventional transistor structures (non-LDD). This paper proposes a treatment of this topic based on an improved model of impact ionisation, which is incorporated in the two-dimensional simulator MINIMOS[S]. This model is shown to be equally applicable to both lightly doped drain (LDD) and non-LDD transistors. The simulator is used to identify the relative significance of each mechanism to the onset of snapback. Simulated values of bipolar holding voltage are shown to compare favourably with measurements. A simple model of impact ionisation involves an exponential dependence of the ionisation rate for each carrier on the local electric field. This model is generally only valid for a limited range of values of 1761
G. A. ARMSTRONG and W. D. FRENCH
1162
electric field. The improved model of impact ionisation is based on the “Lucky electron” theory[6]. The advantage of using this type of model is it provides a more accurate physical description, whereby the ionisation rate at a given point is defined, not by the local electric field, but by the increase in carrier energy. The increase in energy is calculated by integrating the electric field back along a path normal to equipotential contours which defines the carrier trajectory in reaching that point[7]. In a bipolar transistor the current gain is strongly influenced by bandgap narrowing in the emitter region[8]. In an SO1 transistor which is liable to snapback. bandgap narrowing in the source region has a beneficial effect as it serves to reduce the injection of minority carriers. Nonetheless, it is important to model this mechanism accurately to obtain the correct balance between generation of holes in the drain region and recombination at the source junction. if an accurate prediction of the holding voltage is to be found. Choice of carrier recombination lifetime also has a significant influence on the bipolar gain. Once a physically accurate model is established, the options available to maximise the range of operating voltage of SOI transistors via both source and drain engineering can be considered. Three possible options are considered individually: (a) a body contact; (b) a lightly doped source; (c) a lightly doped drain.
The technique for simulation of bipolar snapback involves turning on the transistor with a small positive gate voltage at high drain bias. and then perturbing the solution by stepping down the gate voltage in small increments. The holding voltage, referred to in subsequent sections of this paper, is defined as that value of drain voltage at which the device fails to turn off. An example of a simulation illustrating snapback is indicated by the gate voltage characteristics in Fig. 1. In this instance the holding voltage for a 1 pm gate length non-LDD transistor is considered to be 4.6 V, since this represents the maximum voltage at which the transistor will just turn off. Although the simulation indicates a steep but finite subthreshold slope at a drain voltage of 4.6 V, precise measurement of subthreshold slope in this condition is difficult to carry out, as the device is in an unstable condition and tends to switch abruptly from an “on” (bipolar) state to an “off’ (subthreshold MOS) state. Nonetheless simulations of this kind are a useful indicator of the likely onset of snapback, provided an accurate balance between carrier generation at the drain and recombination at the source is used. A recent enhancement of the simulator[l I] to improve the modelling of the bipolar effect has been the inclusion of a model for bandgap narrowing. The inclusion of such a model modifies the form of the current flow equations such that: J,,=qD,Vn
-qnp,,V$
-p,,nkT.V
(4)
By examining the feasability and relative merit of each of these possibilities, an insight into the range of options that are available for a particular process to maximise the breakdown voltage is obtained. TWO
DIMENSIONAL
MODELLING
The two-dimensional device finite difference simulator MINIMOS4[5] has been adapted in order to simulate bipolar snapback in thin film SO1 MOSFETs[9]. In its original form this package solves Poisson’s equation, and the hole and electron continuity equations: V’I/? = -y(N,-
N,+p
V,J,=q(G V’J,,=
-y(G
-R) -R).
-n);~,
(5) The variation of effective intrinsic concentration with bandgap shrinkage AE, is given by
n,,
ni = nz exp(AE,ikT).
(6)
For heavily doped n-type material in excess of a reference level Nrer of 7 x IO” cm ‘. the experimental Drain
10-‘1
(1) (2) (3)
The techniques for solution of these equations and full descriptions of parameter models have been fully described[lO]. The advantage of using MINIMOS, as opposed to other two-dimensional simulators, is the simplicity of its input data format, availability of simplified process specification, ability to easily modify device geometry and the capability of automatic mesh generation. This allows design optimisation to be carried out in an economical manner. with only minimal change to the input data file.
,o-lo~ 10
-12
i
lo-l4 ’ -1
1
x
,,d
fi
/I
+
I’
)X
cd
+
Vd=4.*”
-8
“d=4.4”
*
“d=O.lV
x i
-0.75
-0.5
-0.25 Cat2
0
0.25
Voltage
(V)
0.5
0.75
I
Fig. 1. Simulated variation of drain current wth gate voltage and different drain biases for a I pm non-LDD transistor with a film thickness of 0.2 pm, a film doping of 3 x 10’bcm~q and a 20 nm gate oxide.
Simulation of ultra thin film SOI transistors data of de1 Alamo and Swanson transistors has been approximated, meV according to:
[12] for bipolar to give A& in
A& = 18.7 ln(lNd - Nal/N,,r).
(7)
Inclusion of such a model has no effect for MOS simulations, but has a significant effect on the prediction of the onset of snapback. Measurements of the intrinsic carrier lifetime may be made using relatively small SOI transistors based upon a method outlined in [13]. Further work has shown that when these results are combined with established generation-recombination theory[2], intrinsic carrier lifetime of approximately 2 x IO-' s are obtained. This value of the intrinsic carrier lifetime in thin SO1 films was introduced into the program and combined with a doping dependence as suggested in [14]. The generation of carriers by impact ionisation is linked to the current density by: G =~~.lJ,J+tlp.IJ~l
(8)
where tl, and ap are the respective ionisation coefficients of electrons and holes. In an n-channel transistor only the contribution due to tl, is significant. Previous modelling of impact ionisation in SO1 transistors[9] was based on the application of Chynoweth’s Law with optimised coefficients[l5] according to: u, = A,exp(-B,/e)
(9)
where the electric field t is defined locally at each mesh point. It has been found that accurate prediction of bipolar holding voltage[ 151 in non-LDD can be achieved using optimised transistors and B, = 1.9 x A, = 3.2 x lo6 cm-’ coefficients, lo6 V cm ’ respectively. While a significant spread exists in the range of values for these coefficients which are quoted in the literature, the latter coefficients are very close to the corresponding respective values of 2.5 x lO”cm-’ and 1.9 x 106V. cm-’ specified by Slotboom [16], from measurements of surface breakdown in gate controlled pn junctions. The numerical algorithm implemented in MINIMOS is based on a sequential solution of (l)-(3), using the step solving approach described in [17]. Initially the Poisson equation is solved assuming fixed quasi-Fermi levels for both electrons and holes. When convergence of the non-linear Poisson equation is achieved, the potential is substituted into the electron continuity equation which is linear and can be solved directly. When (I) and (2) have converged, (3) is introduced into the iteration loop with the generation term G set to zero. Finally the generation term G is computed and included in the right hand side of (2) and (3). In this way the impact ionisation current is calculated self consistently and the effect of the floating region potential is correctly modelled. When the term G becomes significant for high values of generation current, coupling between (2) and (3)
1763
becomes strong and overall convergence of the outer loop is degraded. At this stage only one update of the potential is made for the non-linear Poisson equation followed by successive solution of (2) and (3). This allows overall convergence to be achieved in a reasonable number of iterations (typically less than 50), without the overhead involved in a fully coupled solution of (l)-(3). Particular care has been taken only to update G when the relative change in terminal current in successive iterations is less than 1%. In order to resolve known problems of ill-conditioning of the equations[ 18,191, due to the presence of the floating region, a direct solver based on Gauss elimination is used for solution of (2) and (3), while the ICCG method is appropriate for the solution of (1). While reasonable accuracy can be achieved using appropriate coefficients A, and E, for a particular structure, it has been established that greater accuracy and wider applicability is achieved if the ionisation coefficients are calculated using a nonlocal implementation of Shockley’s “lucky electron” theory[6]. This introduces significant additional complexity in the software implementation, but leads to a more unified treatment which is equally applicable to both LDD and non-LDD transistors. In his original work, Shockley calculated the probability that a carrier will reach the threshold energy for ionisation E,, in travelling through a region of high electric field t, over a distance E,/(qc), without suffering phonon scattering, i.e. the probability of avoiding momentum relaxing collisions. By relating this probability to the mean number of phonons created per ionisation, r, and the distance required for phonon scattering E,,/(qt), Shockley determined a formula for the ionisation coefficient of the form: a=$&exp OP
E,
( > -1
%p 6
where I (= 17.5) is the fixed ratio of mean free path for impact ionisation to mean free path for phonon scattering. Assuming a homogeneous electric field, then d, = E, /qc and dop = Eop/qc and equation (IO) becomes 1
r=-.-exp
I
(11)
r 4,
This equation is similar in form to (9). However in a varying electric field such as exists in the drain region of an SO1 MOSFET, a carrier will gain energy nonlinearly along its trajectory. A non-local calculation of both d, and dop is required, treating the carriers ballistically, so that at any point the energy gained by the carrier is found by integrating the electric field from this point, back along the carrier trajectory. The precise trajectory can be found from the electric field lines calculated by two-dimensional simulation. For impact ionisation to occur the carrier must travel a distance d,, such that E, = q
(12)
G.
II64
A.
ARMSTRONG and
This is equivalent to calculating the distance along the carriers trajectory over which the potential changes by E,/q (1.1 V for an electron). The value of doP is calculated similarly. This method of estimating ionisation rate allows for large rates of change in the electric field over a short distance, such as occurs at pn junctions or even between II and n + regions. In these cases a local model tends to overestimate the ionisation rate, as it assumes that the electric field is high over the entire distance d,. and thereby underestimates this distance. ESTIMATION
OF BIPOLAR
CURRENT
I, = ( A4 - 1) (I& + I, + I, )
Ida = M
(13)
has a gain fl so that
I,=B~U,+I,) then the total drain current
(14) must become
(I,,, + I, + I, 1.
(15)
By combining equations (13-l 5). a theoretical estimate of the equivalent bipolar current gain has been given[4]. such that:
p=
L - M (Ich+ I, ) &j;(M-l)+MI,’
Fig. 2.
Currents Rowing in a
,I
Hole
1
FRENCH current (n.4)
source
Iunction
Drain JUnEtion
GAIN
Because of the floating region, the current flow in an SOI transistor at the onset of snapback is similar to that of a bipolar transistor with open circuit base. Figure 2 depicts the various currents that are found to flow. Idr is the total drain current, I,,, is the front channel current, f, is the leakage current at the drain junction (no impact ionisation), Ig is the peak hole current due to impact ionisation and 1, is the current injected into the base across the emitter-base junction. If it is assumed that the hole current generated by impact ionisation is related to the total current flowing into the drain by the multiplication factor M such that
and the lateral bipolar transistor
W. D.
SO1 MOSFET.
(16)
Fig. 3. Generated hole current vs position normalised to the source gate edge at V, = 3 V and V, = 0 V. for a 0.5 pm non-LDD transistor with a film thickness of 0.1 pm. a film doping of 1.1 x lO”cmand a 14 nm gate oxide.
As suggested in [4], equations (15) and (16) can be used in conjunction with the two dimensional device simulator to calculate values of/j’ and M for an SOI transistor using simulated values of the respective currents I,,, I,, I,Fand I,. The peak hole generation current Z, is found by simulating the device including impact ionisation and integrating the hole current through the entire film thickness. The channel current I,.h at a specific gate voltage is found by simulating with the impact ionisation model turned off. The junction leakage current I, may be found by simulating without impact ionisation at zero gate voltage. By way of illustration Fig. 3 shows a plot of the variation of simulated hole current within the thin SOI film, as a function of distance referenced to the edge of the gate. It should be noted that the peak current I, occurs, not in the drain region alongside the peak electric field, but within the channel at a point where the generation rate and recombination rate precisely balance-i.e. G - R = 0 in (3).
ANALYSIS
OF IMPACT
IONISATION
MODELS
Some success in modelling the variation of bipolar holding voltage with gate length can be achieved using Chynoweth’s law with optimised coefficients to calculate impact ionisation coefficients, as shown in Fig. 4. The measured results were obtained for a batch of n-channel transistors fabricated using SIMOX technology where the equivalent of 1.8 x IO” 0’ ions/cm’ were implanted at an energy of 200 keV, followed by an anneal at I300 C for 6 h. The gate, buried oxide and SO1 film thicknesses were 20. 400 and 200 nm respectively. No LDD implant was used, and the threshold adjust implant gave a nominal threshold voltage of I V. It is clear that with an appropriate choice of coefficients, an accurate prediction of holding voltage over dimerent gate lengths is possible. The simulated dependence of holding voltage on the chosen carrier lifetime is shown in Fig. 5, both with and without an LDD imnlant. The oredicted increase in holding
1765
Simulation of ultra thin film SO1 transistors
+ ++ .
++
LDD
0
0.5
1
1.5 2 2.5 Cats Length (Microns)
3
voltages for non-LDD 0.2pm, a film doping
transistors with a film thickness of of 1.5 x 10” cme3 and a 20 nm gate oxide.
voltage with decrease in lifetime is due to the reduced diffusion length of carriers injected across the source junction, while the use of an LDD implant is due to the reduced field in the drain region. In order to compare the “local” and “non-local” models of impact ionisation, some simulations of substrate current in bulk MOSFETs were carried out. The ratio of peak substrate current to drain current was measured, for a range of bulk MOSFETs with differing gate lengths. As is clear from Fig. 6, it is not possible to fit simultaneously the experimental measurements of both LDD and non-LDD transistors, using a “local” model of impact ionisation, even if the coefficients specified previously are used. If, however, the non-local model with a constant carrier mean free path A,, of 8.9 nm is used, a much better fit to the measured results is obtained for both cases, and is applicable for gate lengths exceeding 1 pm. This value of I,, compares favorably with the value of 9.1 nm found by other authors[20,21]. It is clearly much more difficult to assess the accuracy of the improved model for SO1 transistors, since it is not easy to measure either the bipolar gain
T
1
3.5
Fig. 4. Comparison of simulated and measured holding
t 1.2 Gate
Length
1.4
w, 1.6
i 1.8
(micron)
Fig. 6. Ratio of bulk to drain current vs gate length for measured (solid lines) and simulated (points) devices, using Chynoweth’s law (.) and a nonlocal Shockley method with constant (+) and field dependent (*) optical mean free paths. The film doping was 3 x lOI cm-’ with a 27 nm gate oxide and the LDD consisted of a 1 x 10’) cm-* n implant with a 0.25 pm oxide spacer.
or the ionisation rate. We have, however, used the simulator to compare the simulated bipolar holding voltage for a 0.8 pm gate length LDD transistor to measured results[22], as shown in Fig. 7. Once again the thin film SOI transistors were fabricated on SIMOX material. On this occasion the devices employed p + polysilicon gate and a gate overlapped LDD was included to reduce the drain field. In Fig. 7 a positive value of channel doping indicates a p-type doping, while a negative value indicates an n-type doping. It is clear that when the model of bandgap narrowing is included, an improved prediction of the bipolar holding voltage is obtained. If bandgap narrowing is omitted from the simulation, the bipolar current gain is greatly overestimated and results in much lower values of the simulated holding voltage. The estimated bipolar current gain of the SO1 transistor was calculated from detailed simulations of the various current components as defined in (16). The reduction 2 Holding I
,-
Voltage
(V)
current
Gain 3103
I
104
6-
S-
4-
1 I 103
109
3-
Fig. 5. Dependence of holding voltage on carrier lifetime for a 0.5 pm transistor. with and without a LDD, a tilm thickness of 0.1 pm and a film doping of I.1 x 10’7cm-3. The LDD comprised a 1 x IO”cm-’ n- implant and a 0.25 Frn oxide spacer.
Fig. 7. Measured (thick line) and simulated results with (+) and without (m) bandgap narrowing for a constant optical mean free path and with bandgap narrowing for a field dependent optical mean free path (*). The device comprised a 0.8 pm gate length, a 0.08 pm film thickness, a n implant dose of 5 x IO” cm-’ and a 0.25 pm spacer.
G. A. ARMSTRONG and W. D. FRENCH
1766
shown in the bipolar current gain associated with increased doping in the SOI film, arises due to an increase in effective base doping of the lateral bipolar transistor. The use of a constant value for the optical mean free path tends to overestimate the holding voltage for film doping > 10” cm-3. The reason for this is that the electric field profile in a thin film SOI transistor is high throughout the film, unlike a bulk transistor where it peaks close to the oxide interface. This is clear from Fig. 8 which compares the electric field contours in the drain region of two SOI transistors for film thicknesses of 0.05 and 0.15 pm respect-
ively. For the thinner film, the high lateral electric field extends throughout the film, whereas for the thicker film, the field peaks within the drain region close to the gate oxide interface. Initial estimates of E.,, were based on measurements taken from bulk transistors where the field profile is comparable to that shown in Fig. 8(b). Because of the different field pattern associated with the ultra thin film, this constant value of &, does not fit the measured variation of holding voltage for SO1 devices. Hence a spatially varying value of A,,, very similar to one used in [7], is required to accurately reproduce the variation in holding voltage with film doping. Detailed
I
.8
.7
.9
1
MICRON ELtCTRlC
I- IEI
0
(LHTERHIL)
I
.7
I
.I3
.9
--,--7
1
MICRON
(b) Fig. 8. Lateral electric field profiles at V,, = 3.5 V. V, = 0 V for a I pm gate length non-LDD transistor with a 20 nm gate oxide, a film doping of 3 x IO” cm-’ and film thickness of (a) 0.05 pm and (b) 0.15 /cm.
Simulation of ultra thin film SOI transistors simulations have suggested a dependency of &,, on trajectory path length d,, according to: &=
IO-5exp(-d/100)
OF THE BIPOLAR HOLDING
Voltage (V)
(17)
where all constants are expressed in nm. This appears to be an optimal model valid for both sub-micron SO1 and bulk devices respectively. Making A,,,dependent upon di implies that A,,, is indirectly dependent on the electric field along the carrier trajectory. This is a more physically meaningful relationship in line with the energy dependent optical mean free path model described in [23]. Only with this model can an accurate prediction of both the holding voltage in SOI transistors, and substrate current in a bulk transistor be obtained, for the same set of model parameters, as shown in Figs 7 and 6 respectively. OI’TIMISATION
5Edding
1767
VOLTAGE
From the literature it is clear that there are 3 basic methods that may be used to improve the holding voltage of SO1 transistors: (a) an extra contact to the SO1 film, a “body” contact, to remove holes generated by impact ionisation at the drain and so prevent the bipolar transistor from turning on; (b) drain engineering to reduce the peak electric fields at the drain and thereby reduce impact ionisation rate; (c) source engineering to reduce the current gain /I of the transistor so that higher drain voltages are required before /?(M - 1) + 1. These points are addressed in the following simulations. In all subsequent simulations we consider the specific case of a transistor with a gate length of 0.5 pm, an oxide thickness of 14 nm and a film doping chosen to give threshold voltage of 0.6V. (a) Body contact
The effect of a body contact has been simulated by allowing the source contact to extend below the level of the oxide interface to such an extent that it eventually contacts the SOI film directly, if the junction depth is less than the film thickness. Figure 9 shows the reduction in current gain and the associated increase in the holding voltage, as the distance from contact to metallurgical junction is progressively reduced. The reduction in current gain can be readily explained by the associated reduction in the diffusion length of holes[2]. Although the simulation represents a highly ideal situation not readily achievable in practice, controlled silicidation of the source can be used to achieve the same effect. Indeed, experimental results have confirmed an increase in the holding vohage[24] in such devices. However, this type of contact is only feasible when used with thicker films and the trend towards ultra-thin SO1 films will require other methods of maximising the holding voltage.
+
-
/
J
Holdin
Volta2s
currentCain
..:ii”\----_l:“” 0
0.1
0.2
contact
-
0.3
Junction
0.5
0.4
2epu.tion
(microns)
Fig. 9. Simulated variation of holding voltage and current gain with distance from the source contact to the junction for a 0.5 pm non-LDD transistor with a film thickness of 0.1 pm and a film doping of 1.1 x 10” cm-‘. (b) Lightly doped source
The bipolar current gain /.I is known(2] to depend upon the ratio of source (emitter) doping to film (base) doping. It is therefore obvious that low source and high film doping is desirable in SOI transistors. Figure 10 shows the simulated increase in holding voltage and the change in current gain which can be achieved by lowering the source implant dose, whilst keeping the drain implant dose constant. In this case there is no spacer region. By reducing the source implant from 5 x 10” to 1 x 10’) cmm2, an increase in the holding voltage of more than 1 V is predicted. The corresponding reduction in gain is partially offset by a reduction in bandgap narrowing, which is taken into account in the simulation. In practice, however, to achieve such a significant improvement, it is necessary to utilise an unrealistically low value of peak source doping i.e. less than lO’acm--‘, as opposed to a typical value of 1020cm-3. Even in a structure that employs some form of spacer, it is not possible to achieve an order of magnitude reduction in effective doping, because of the combined effect of the n + and n - regions. For example, in a device with an n - implant dose of 5 x lOI cmm2 and a 0.25 pm 4,5Holding
vo1t*ge
current
Vi-l(V)
Cain
700
-Vh 4-
+
, 1013
/
Id4
I,
I,
1015
,
Bet.
- 800 *eta
,uJ
I,,
lOI@
10IY
sourceImplant nome(crtr2)
Fig. 10. Simulated variation of holding voltage and current gain with source implant dose, with a constant drain implant dose of 5 x 1015cm-2, for a 0.5 pm non-LDD transistor.
1768
G. A. ARMSTRONG and W. D. FRENCH
spacer, simulation may be used to show [see Appendix I] that when bandgap narrowing is taken into account, the injection of carriers still occurs from an effective source doping of greater than 1 x 10” cm 3 despite the presence of the lightly doped region. (c) Light/J, doped druin The improved holding voltages with increased film doping shown in Fig. 7 can be used together with a lightly doped drain to maximise the holding voltage for ultra thin films as low as 50 nm. as shown in Fig. I I. For the two different film thicknesses, the film doping in each case has been chosen to give a threshold voltage of 0.6 V. Significantly, the thinner film with a doping of 2.5 x 10”cm-‘, has a higher maximum holding voltage than the thicker film device with a doping of 1. I x 10” cm- 3. This increase can be partially attributed to the reduction in bipolar gain associated with increased film doping. A further contributory factor, however, for an LDD transistor, concerns the effect of thinning the SOI film, which reduces the peak field strength in the n lightly doped drain. Figure 12 shows the dependence of peak lateral electric field for two film thicknesses, both with and without an LDD implant. For the non-LDD transistor shown in case (a), the higher peak field occurs for the thinner film, and increases with film doping, as reported in [25]. If these calculations are repeated, at the same gate length and bias condition, but including an LDD region, the variation of peak field with film thickness and doping exhibits a significantly different pattern, as shown by case (b). In this case the peak lateral field for both film thicknesses occurs within the depleted LDD region. As the SOI film doping is increased, the peak field associated with the thicker film increases more than the peak field associated with the thinner film, which remains independent of doping. This behaviour is a result of the thicker film becoming partially depleted for doping > 1.5 x lO”cm m3. The thinner film would also exhibit the same effect but now for doping greater than
Fig. 12. Variation in peak lateral electric field versus SO1 film doping for a 0.5pm gate length transistor. with and without a LDD, at VP = I V for a film thickness of 0. I pm (.) and 0.05 pm (+). The LDD comprised a 0.25 /urn spacer and a n implant dose of I x IO” cm ‘.
5 x 10” cmm3. This pattern is even more pronounced at a higher drain voltage, when there is now a significantly lower peak field for the thinner film, regardless of the doping level. The reduced electric field in case (c), however, now occurs because the thinner film gives rise to a much greater lateral spreading of the depletion region within the LDD, since the depletion in the transverse direction is limited by the film thickness. This point is evident from the plots of electric field contours in Fig. 13 where there is increased separation of the contour lines for the thinner film, and a corresponding reduction in the peak field from 3 x 10’ to 2.6 x lo5 V cm-‘. Finally, case (c) of Fig. 12 shows a small reduction in the electric field with increased doping. Simulations have shown that this is a result of fewer electric field lines from the drain terminating on the gate. A more uniform electric field profile is obtained and consequently a slightly lower electric field strength. CONCLUSIONS
In order to correctly estimate the bipolar holding voltage of thin film SO1 transistors with sub-micron gate lengths, it is necessary to obtain the correct balance between the bipolar current gain and impact ionisation. The bipolar current gain was found to be dependent upon bandgap narrowing in the heavily doped source, whilst impact ionisation may be accurately modelled only with a non-local ballistic model. The limitations of the model of impact ionisation, based on the “local” electric field were found to be essentially twofold:
Fig. I I. Simulated variation of holding voltage with II implant dose for a 0.5 pm transistor with a 0.25 /urn spacer and two film thicknesses. keeping the threshold voltage constant at 0.6 V.
(a) different for bulk (b) different for LDD
ionisation constants arc required and SO1 devices; ionisation constants are required and non-LDD devices.
A more generally applicable method was obtained when the non-local impact ionisation model was
Simulation
.3
of ultra thin film SO1 transistors
.4
.5
1769
.6
.7
MICRON ELECTRIC
FIELD
(LFITERAL)
(a)
-PN-JUNCTION
I
.2
.3
.5
.4
.6
.7-
MICRON ELECTRIC
FIELD
(LATERFILl
(b) Fig. 13. Lateral electric field contours in the n - region of a 0.5 pm transistor with a 0.25 pm spacer, n- implant dose of 1 x 10’3cm-’ and film thicknesses of (a) 0.1 pm and (b) 0.05 pm.
combined with an electric field dependent optical mean free path length. Simulation suggests that optimal engineering of both source and drain regions is necessary to maximise the bipolar holding voltage. The use of a symmetrical LDS/LDD structure with a spacer reduces the impact ionisation in the drain. However the presence of the spacer region in conjunction with a heavily doped source tends to limit the achievable reduction in effective emitter doping. Simulations of a lightly doped drain structure suggest that thinning the SO1 film gives rise to an unexpected reduction in the lateral electric field in the
a
n- drain region. This occurs because of increased lateral spreading of the drain depletion region when bounded by the buried oxide. Hence an ultra-thin highly doped film, with an optimised LDD, appears to be the optimum combination to maximise the bipolar holding voltage. Indeed with this combination, a maximum holding voltage in excess of 6.5 V has been simulated in a 0.5 pm gate length SOI transistor. Acknowledgemenfs-The authors support from the Procurement Defence (RSRE) and the U.K. Research Council.
acknowledge the financial Executive, Ministry of Science and Engineering
G. A. ARMSTRONG and W. D. FRENCH
1770 REFERENCES
Technology: Ma1. J. P. Colinge, Silicon-on-Insulator terials to VLSI. Kluwer Academic Publishers (1991). Devices. Wiley, 2. S. M. Sze, Physics of Semiconducfor New York (1981). 3. K. K. Young and J. A. Burns, IEEE Trans. Electron. Device ED-35, 426 (1988). 4. J. Y. Choi and J. G. Fossum, IEEE Trans. Electron. Device ED-38, 1384 (1991). 5. S. Selberherr et al., IEEE Trans. Electron Device ED-27, 1540 (1980). 6 W. Shockley, Solid-St. Electron. 2, 825 (1961). 7 T. Thuraate and N. Chan, IEEE Trans. Electron. Device ED-32,200 (1985). Bipolar Semiconductor Devices. 8 D. J. Roulston, McGraw-Hill, New York (1991). et al., IEEE Trans. Electron Device 9 G. A. Armstrong ED-38, 328 (1991). IEEE Trans. Electron. Device ED-36, 10 S. Selberherr, 1464 (1989). and W. French, Proc. INFOS, LiverII G. A. Armstrong pool, pp. 335-338 (1991). 12. J. de1 Alamo et al., IEDM Tech. Dig., pp. 290-293 (1985). and P. E. Belk, Proc. IEEE SOSjSOI 13. P. C. Karulkar Tech. Conf., Fla, pp. 139-140 (1990). and J. Kerr, GPS Marconi. Lincoln, 14. D. Kimpton private communication. et al.. Proc. IEEE SOSISOI Tech. 15. G. A. Armstrong Co& Nevada, pp. 4445 (1989). 16. J. W. Slotboom et al., IEDM Tech. Dig., pp. 494497 (1987). 17. K. Kato et al., IEEE Tram Electron. Device ED-32, 458 (1985). 18. R. Rios et al., IEEE Tram Electron. Device ED-39, 581 (1992). 19. S. Edwards et al., IEEE Tram Electron. Device ED-35, 1012 (1988). 20. T. H. Ning el al., J. uppl. Phys. 48, 286 (1977). 21. S. Tam et al., IEEE Trans. Electron. Device ED-31, 1 I16 (1984).
22. Y. Yamaguchi et al., IEDM Tech. Dig., pp. 591-594 (1990). 23. Y. Z. Chen and T. W. Tang, J. qpl. Phys. 65, 4279 (1989). 24. H. Lifka and P. H. Woerlee. Pro<,. ESSDERC. Nottingham, pp. 453 -456 ( 1990). 25. M. Yoshimi et al., IEEE Trans. Eleclron. Device ED-37, 2015 (1990). APPENDIX
I
It has been established[2] that for an abrupt junction, the bipolar current gain may be approximated by the emitter and base doping, according to: (Al) Therefore, using the values of current gain, both with and without bandgap narrowing, shown in Fig. 7. for a base doping of I x 10” cm-‘, we obtain:
It has also been shown[8] that bandgap narrowing may be viewed as introducing an “effective” doping level according to: N,,=N,exp(-AE,,kT).
(A31
Assuming therefore that injection of carriers from the emitter into the base is unaffected when bandgap narrowing is included, then equation (A2) becomes:
3 AE, = 0.0596 eV.
(.45)
Using equation (7), this value of bandgap narrowing corresponds to an effective doping in the composite emitter (comprising n + and n regions) of I .7 x 10’Ycm~’ rather than the actual doping level of 5 x lO”cm ’ in the II region.