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Fabrication of ultra-thin-film SOI transistors using the recessed channel concept
Microelectronic Engineering 78–79 (2005) 224–228 www.elsevier.com/locate/mee
Fabrication of ultra-thin-film SOI transistors using the recessed channel concept L. Dreeskornfeld *, J. Hartwich, F. Hofmann, J. Kretz, E. Landgraf, R.J. Luyken, W. Ro¨sner, R. Schro¨ter, T. Schulz, M. Specht, M. Sta¨dele, W. Weber, L. Risch Infineon Technologies AG, Corporate Research, Otto-Hahn-Ring 6, D-81730 Munich, Germany Available online 4 January 2005
Abstract In this article, ultra-thin-film SOI transistors fabricated by locally recessing the channel regions are presented. SOI MOSFETs with ultra-thin channels offer better scaling properties than bulk transistors due to suppressed short channel effects, reduced parasitic capacitance and easy lateral isolation. The objective of this work was to establish a fabrication scheme for the production of fully depleted (FD) SOI transistors with channel thicknesses of 20 nm and below. An SEM based direct write electron beam lithography was used to pattern structures in the sub 100 nm range. Special emphasis was put on the pattern transfer which is accomplished by high-density plasma etching using hard masks and subsequent resist free silicon patterning with a high density HBr/O2 plasma. This enabled transistor channels as thin as 1 nm to be produced. Together with standard CMOS production processes NMOS and PMOS transistors with gate lengths down to 48 nm have been fabricated and electrically characterized. In this way recessed channel SOI transistors with channel thicknesses below 10 nm and gate lengths smaller than 50 nm have been achieved for the first time. Ó 2004 Elsevier B.V. All rights reserved. Keywords: SOI MOSFET; Thin film SOI; Recessed channel; Reactive ion etching; Electron beam lithography
1. Introduction Ultra-thin-film SOI MOSFETs are a very promising replacement for conventional bulk transistors in the next CMOS generations [1]. SOI * Corresponding author. Tel.: +49 89 234 50022; fax: +49 89 234 955 1643. E-mail address: lars.dreeskornfeld@infineon.com (L. Dreeskornfeld).
transistors offer suppressed short channel effects, reduced parasitic capacitance and simple lateral isolation [2]. However, their integration into CMOS technology is more difficult due to the ultra-thin silicon layer that is required and gate work function engineering. To take full advantage of the SOI transistor a gate length (Lg) to silicon thickness (TSi) ratio of approximately 4:1 should be used for devices with undoped channels [3]. Consequently, channel thicknesses below 10 nm are nec-
0167-9317/$ - see front matter Ó 2004 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2004.12.030
L. Dreeskornfeld et al. / Microelectronic Engineering 78–79 (2005) 224–228
essary for future transistor generations. Further, advanced source (S) and drain (D) constructions are required to assure low series resistances. This can be accomplished by raised S/D regions using selective epitaxial growth [4]. An alternative approach is the thinning of the channel region by oxidation and wet etching techniques. This method can lead to very thin silicon layers with excellent interface properties [5–8]. SOI MOSFETs with a film thickness down to 0.7 nm and channel lengths of 500 lm have been fabricated [8]. However, due to the oxidation related ‘‘birds beak’’ this method is not well suited for very small gate lengths. The use of dry etching, on the other hand, can enable shorter gate lengths [9]. In this paper, reactive ion etching in combination with oxidation and wet etching is explored in order to fabricate SOI transistors with smaller gate lengths while maintaining good interface qualities using the recessed channel approach. A schematic drawing of this transistor concept is shown in Fig. 1. In addition to the low resistance contacts the recessed channel fabrication scheme enables the straightforward implementation of metal gates into the process flow.
2. Device fabrication The channel region and the gate were defined by electron beam lithography. For the channel layer a positive tone ZEP 520 resist with a thickness of 100 nm was used. The exposure was performed with an acceleration voltage of 15 keV and a dose of about 2000 lC/cm2. Fig. 2 shows an SEM image of the resist structure after exposure and 60 s
Fig. 1. Schematic drawing of a recessed channel SOI transistor. Nitride spacers and a nitride hardmask on top of the active area are used in this realization.
225
Fig. 2. SEM image of the resist structure after electron beam exposure and development on top of the active area.
development in ZED N50. The predefined active crystalline silicon (mesa) surrounded by TEOS spacers is visible under the resist mask. In this case in addition to the pure channel region the layout also contains the connection line and the pad area. Depending on the subsequent procedures this allows the gate layer to be processed by simply back etching without an additional high resolution lithography step. However, in order to achieve low resistivity contacts and for implantation purposes it is advantageous to apply a second high resolution lithography step to define the gate structure. Therefore, excellent alignment to the underlying layer is essential. With special alignment marks and a sophisticated analysis routine an overlay accuracy of better than 10 nm was achieved [10]. A negative tone 80 nm thick calixarene resist was used for this gate exposure, which is described in more detail in [11]. The transfer of these structures was undertaken in a high density plasma etch tool (density 1012 cm 3). Special emphasis was put on the process evaluation for the thinning of the channel area. The quality and thickness of the silicon in this region is very critical for transistor operation. Furthermore, due to the small open area, no end point detection is possible and therefore, excellent control and understanding of the process is needed. The individual process steps, including etching of the hardmask, breakthrough and silicon
226
L. Dreeskornfeld et al. / Microelectronic Engineering 78–79 (2005) 224–228
Fig. 3. TEM image of a recessed channel SOI transistor. A silicon channel as thin as 1 nm was successfully etched. Subsequently the polysilicon gate layer was deposited and back etched.
Fig. 4. TEM images of a fully processed ultra-thin-film SOI transistor using the recessed channel fabrication scheme. The lowest picture shows an enlarged view of the crystalline channel area with the gate oxide (GOX) on top.
L. Dreeskornfeld et al. / Microelectronic Engineering 78–79 (2005) 224–228
current below 1 pA was achieved. The on-current of 520 lA/lm at VDS = VG = 1.5 V shows evidence of a high quality channel surface. The electrical characteristics of a p-channel transistor with an undoped channel and a gate length of about 48 nm are given in Figs. 6(a) and (b). Even for this short gate length an excellent turn off behavior was achieved. The subthreshold slope for this transistor corresponds to 91 mV/dec. The output characteristics in Fig. 6(b) show an on-current of 102 lA/lm at VDS = VG = 1.5 V. The electrical figures of merit are summarized in Table 1. Further enhancement of the on-currents is anticipated by using a gate oxide thinner than 3 nm, spacer optimization, or reducing the contact resistance (silicidation, LDD).
1E-3 1E-4 1E-5 1E-6 1E-7
ID[A/µm]
etching, have been analyzed and optimized. A fluorine based chemistry was used to open the hardmask. By changing the mixture of C3F6, CH2F2 and CHF3 the F:C ratio can be adjusted, thereby controlling polymer formation. This is of particular importance because the electron beam resist layers are very thin. For the silicon breakthrough step a smooth but reproducible process is needed. Both Cl2/O2 and pure HBr breakthrough processes were compared. The best results were achieved with the HBr process. The reproducibility was first tested on unpatterned wafers. This analysis indicates that conditioning the chamber by applying the breakthrough process to a test wafer beforehand can limit the endpoint variation to about 5%. A more detailed description is given in [12]. For the silicon etching the influence of the process parameters on etch rates, selectivities and profiles have been extensively studied previously [13]. In combination with oxidation and wet etching these unit processes were embedded into an SOI process flow. After optimization of all process parameters transistor channels as thin as 1 nm were achieved, as can be seen in the TEM image in Fig. 3. Here, the channel as been thinned from an original layer thickness of 50 nm. After thermal oxidation for the gate oxide and spacer formation, the poly crystalline gate silicon was deposited and back etched. A minor oxidation and wet etching step was used to remove the plasma induced damage layer, thereby increasing the mobility.
VDS=0.01V VDS=0.51V VDS=1.01V
1E-8 1E-9 1E-10 1E-11 1E-12 1E-13 1E-14 -1.5
-1.0
(a)
600 550 500
ID [µA/µm]
0.0
0.5
1.0
1.5
VGS = 0.0 V VGS = 0.5 V VGS = 1.0 V VGS = 1.5 V VGS = 2.0 V
650
3. Electrical characterization
-0.5
VGS[V] 700
Operational NMOS and PMOS transistors with gate lengths down to 48 nm were fabricated. Fig. 4 shows TEM images of a fully processed SOI transistor. In this case the crystalline silicon layer has a thickness of 10 nm. A very smooth transistor channel surface with no silicon thickness variation was achieved. The gate oxide has a thickness of 3 nm. Electrical characteristics are shown in Figs. 5 and 6. The transfer and output characteristics of an n-channel transistor with an undoped channel and a gate length of about 145 nm are given in Fig. 5(a) and (b), respectively. A very low leakage
227
450 400 350 300 250 200 150 100 50 0 0.0
(b)
0.5
1.0
1.5
2.0
VDS[V]
Fig. 5. Transfer (a) and output (b) characteristics for a NMOS SOI transistor with a silicon channel thickness of 10 nm.
228
L. Dreeskornfeld et al. / Microelectronic Engineering 78–79 (2005) 224–228
in combination with oxidation and wet etching was optimized and used to fabricate transistors with small gate lengths and thin channel thicknesses at the same time. Together with standard CMOS production processes leakage currents below 1 pA were achieved. Evidence of the high quality of the channel surfaces is shown by the on-currents of 520 lA/lm for the NMOS and 102 lA/lm for the PMOS transistors with channel thicknesses of 10 nm.
1E-4
VDS = -0.01 V VDS = -0.51 V VDS = -1.01 V VDS = -1.51 V
1E-5 1E-6
ID[A/µm]
1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 -2
-1
0
1
(a)
2
3
VGS[V]
150 130 120 110 100
ID[µA/µm]
The authors thank T. Ohnemus and V. Klu¨ppel from Siemens Analytics for the TEM investigations. This work was partially performed within the EU project NanoCMOS, IST 507587.
VGS-Vth=0.0 V VGS-Vth=0.5 V VGS-Vth=1.0 V VGS-Vth=1.5 V VGS-Vth=2.0 V
140
Acknowledgements
90 80 70
References
60 50 40 30 20 10 0 -2.0
(b)
-1.5
-1.0
-0.5
0.0
VDS[V]
Fig. 6. Transfer (a) and output (b) characteristics for a PMOS SOI transistor with a gate length of 48 nm.
Table 1 Typical MOSFET characteristics
Drive current Ion (lA/lm) Threshold voltage Vth (mV) Leakage current Ileak (pA/lm) Subthreshold Slope S (mV/dec) DIBL (mV/V)
NMOS
PMOS
520 330 <1 96 223
102 38 10 91 187
The threshold voltage Vth is measured at 10
7
L/W.
4. Summary N- and p-channel SOI transistors with ultrathin channels down to 1 nm and gate lengths down to 48 nm have successfully been fabricated using the recessed channel concept. Reactive ion etching
[1] ITRS 2003 Update. Available from:
Fabrication of ultra-thin-film SOI transistors using the recessed channel concept L. Dreeskornfeld *, J. Hartwich, F. Hofmann, J. Kretz, E. Landgraf, R.J. Luyken, W. Ro¨sner, R. Schro¨ter, T. Schulz, M. Specht, M. Sta¨dele, W. Weber, L. Risch Infineon Technologies AG, Corporate Research, Otto-Hahn-Ring 6, D-81730 Munich, Germany Available online 4 January 2005
Abstract In this article, ultra-thin-film SOI transistors fabricated by locally recessing the channel regions are presented. SOI MOSFETs with ultra-thin channels offer better scaling properties than bulk transistors due to suppressed short channel effects, reduced parasitic capacitance and easy lateral isolation. The objective of this work was to establish a fabrication scheme for the production of fully depleted (FD) SOI transistors with channel thicknesses of 20 nm and below. An SEM based direct write electron beam lithography was used to pattern structures in the sub 100 nm range. Special emphasis was put on the pattern transfer which is accomplished by high-density plasma etching using hard masks and subsequent resist free silicon patterning with a high density HBr/O2 plasma. This enabled transistor channels as thin as 1 nm to be produced. Together with standard CMOS production processes NMOS and PMOS transistors with gate lengths down to 48 nm have been fabricated and electrically characterized. In this way recessed channel SOI transistors with channel thicknesses below 10 nm and gate lengths smaller than 50 nm have been achieved for the first time. Ó 2004 Elsevier B.V. All rights reserved. Keywords: SOI MOSFET; Thin film SOI; Recessed channel; Reactive ion etching; Electron beam lithography
1. Introduction Ultra-thin-film SOI MOSFETs are a very promising replacement for conventional bulk transistors in the next CMOS generations [1]. SOI * Corresponding author. Tel.: +49 89 234 50022; fax: +49 89 234 955 1643. E-mail address: lars.dreeskornfeld@infineon.com (L. Dreeskornfeld).
transistors offer suppressed short channel effects, reduced parasitic capacitance and simple lateral isolation [2]. However, their integration into CMOS technology is more difficult due to the ultra-thin silicon layer that is required and gate work function engineering. To take full advantage of the SOI transistor a gate length (Lg) to silicon thickness (TSi) ratio of approximately 4:1 should be used for devices with undoped channels [3]. Consequently, channel thicknesses below 10 nm are nec-
0167-9317/$ - see front matter Ó 2004 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2004.12.030
L. Dreeskornfeld et al. / Microelectronic Engineering 78–79 (2005) 224–228
essary for future transistor generations. Further, advanced source (S) and drain (D) constructions are required to assure low series resistances. This can be accomplished by raised S/D regions using selective epitaxial growth [4]. An alternative approach is the thinning of the channel region by oxidation and wet etching techniques. This method can lead to very thin silicon layers with excellent interface properties [5–8]. SOI MOSFETs with a film thickness down to 0.7 nm and channel lengths of 500 lm have been fabricated [8]. However, due to the oxidation related ‘‘birds beak’’ this method is not well suited for very small gate lengths. The use of dry etching, on the other hand, can enable shorter gate lengths [9]. In this paper, reactive ion etching in combination with oxidation and wet etching is explored in order to fabricate SOI transistors with smaller gate lengths while maintaining good interface qualities using the recessed channel approach. A schematic drawing of this transistor concept is shown in Fig. 1. In addition to the low resistance contacts the recessed channel fabrication scheme enables the straightforward implementation of metal gates into the process flow.
2. Device fabrication The channel region and the gate were defined by electron beam lithography. For the channel layer a positive tone ZEP 520 resist with a thickness of 100 nm was used. The exposure was performed with an acceleration voltage of 15 keV and a dose of about 2000 lC/cm2. Fig. 2 shows an SEM image of the resist structure after exposure and 60 s
Fig. 1. Schematic drawing of a recessed channel SOI transistor. Nitride spacers and a nitride hardmask on top of the active area are used in this realization.
225
Fig. 2. SEM image of the resist structure after electron beam exposure and development on top of the active area.
development in ZED N50. The predefined active crystalline silicon (mesa) surrounded by TEOS spacers is visible under the resist mask. In this case in addition to the pure channel region the layout also contains the connection line and the pad area. Depending on the subsequent procedures this allows the gate layer to be processed by simply back etching without an additional high resolution lithography step. However, in order to achieve low resistivity contacts and for implantation purposes it is advantageous to apply a second high resolution lithography step to define the gate structure. Therefore, excellent alignment to the underlying layer is essential. With special alignment marks and a sophisticated analysis routine an overlay accuracy of better than 10 nm was achieved [10]. A negative tone 80 nm thick calixarene resist was used for this gate exposure, which is described in more detail in [11]. The transfer of these structures was undertaken in a high density plasma etch tool (density 1012 cm 3). Special emphasis was put on the process evaluation for the thinning of the channel area. The quality and thickness of the silicon in this region is very critical for transistor operation. Furthermore, due to the small open area, no end point detection is possible and therefore, excellent control and understanding of the process is needed. The individual process steps, including etching of the hardmask, breakthrough and silicon
226
L. Dreeskornfeld et al. / Microelectronic Engineering 78–79 (2005) 224–228
Fig. 3. TEM image of a recessed channel SOI transistor. A silicon channel as thin as 1 nm was successfully etched. Subsequently the polysilicon gate layer was deposited and back etched.
Fig. 4. TEM images of a fully processed ultra-thin-film SOI transistor using the recessed channel fabrication scheme. The lowest picture shows an enlarged view of the crystalline channel area with the gate oxide (GOX) on top.
L. Dreeskornfeld et al. / Microelectronic Engineering 78–79 (2005) 224–228
current below 1 pA was achieved. The on-current of 520 lA/lm at VDS = VG = 1.5 V shows evidence of a high quality channel surface. The electrical characteristics of a p-channel transistor with an undoped channel and a gate length of about 48 nm are given in Figs. 6(a) and (b). Even for this short gate length an excellent turn off behavior was achieved. The subthreshold slope for this transistor corresponds to 91 mV/dec. The output characteristics in Fig. 6(b) show an on-current of 102 lA/lm at VDS = VG = 1.5 V. The electrical figures of merit are summarized in Table 1. Further enhancement of the on-currents is anticipated by using a gate oxide thinner than 3 nm, spacer optimization, or reducing the contact resistance (silicidation, LDD).
1E-3 1E-4 1E-5 1E-6 1E-7
ID[A/µm]
etching, have been analyzed and optimized. A fluorine based chemistry was used to open the hardmask. By changing the mixture of C3F6, CH2F2 and CHF3 the F:C ratio can be adjusted, thereby controlling polymer formation. This is of particular importance because the electron beam resist layers are very thin. For the silicon breakthrough step a smooth but reproducible process is needed. Both Cl2/O2 and pure HBr breakthrough processes were compared. The best results were achieved with the HBr process. The reproducibility was first tested on unpatterned wafers. This analysis indicates that conditioning the chamber by applying the breakthrough process to a test wafer beforehand can limit the endpoint variation to about 5%. A more detailed description is given in [12]. For the silicon etching the influence of the process parameters on etch rates, selectivities and profiles have been extensively studied previously [13]. In combination with oxidation and wet etching these unit processes were embedded into an SOI process flow. After optimization of all process parameters transistor channels as thin as 1 nm were achieved, as can be seen in the TEM image in Fig. 3. Here, the channel as been thinned from an original layer thickness of 50 nm. After thermal oxidation for the gate oxide and spacer formation, the poly crystalline gate silicon was deposited and back etched. A minor oxidation and wet etching step was used to remove the plasma induced damage layer, thereby increasing the mobility.
VDS=0.01V VDS=0.51V VDS=1.01V
1E-8 1E-9 1E-10 1E-11 1E-12 1E-13 1E-14 -1.5
-1.0
(a)
600 550 500
ID [µA/µm]
0.0
0.5
1.0
1.5
VGS = 0.0 V VGS = 0.5 V VGS = 1.0 V VGS = 1.5 V VGS = 2.0 V
650
3. Electrical characterization
-0.5
VGS[V] 700
Operational NMOS and PMOS transistors with gate lengths down to 48 nm were fabricated. Fig. 4 shows TEM images of a fully processed SOI transistor. In this case the crystalline silicon layer has a thickness of 10 nm. A very smooth transistor channel surface with no silicon thickness variation was achieved. The gate oxide has a thickness of 3 nm. Electrical characteristics are shown in Figs. 5 and 6. The transfer and output characteristics of an n-channel transistor with an undoped channel and a gate length of about 145 nm are given in Fig. 5(a) and (b), respectively. A very low leakage
227
450 400 350 300 250 200 150 100 50 0 0.0
(b)
0.5
1.0
1.5
2.0
VDS[V]
Fig. 5. Transfer (a) and output (b) characteristics for a NMOS SOI transistor with a silicon channel thickness of 10 nm.
228
L. Dreeskornfeld et al. / Microelectronic Engineering 78–79 (2005) 224–228
in combination with oxidation and wet etching was optimized and used to fabricate transistors with small gate lengths and thin channel thicknesses at the same time. Together with standard CMOS production processes leakage currents below 1 pA were achieved. Evidence of the high quality of the channel surfaces is shown by the on-currents of 520 lA/lm for the NMOS and 102 lA/lm for the PMOS transistors with channel thicknesses of 10 nm.
1E-4
VDS = -0.01 V VDS = -0.51 V VDS = -1.01 V VDS = -1.51 V
1E-5 1E-6
ID[A/µm]
1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 -2
-1
0
1
(a)
2
3
VGS[V]
150 130 120 110 100
ID[µA/µm]
The authors thank T. Ohnemus and V. Klu¨ppel from Siemens Analytics for the TEM investigations. This work was partially performed within the EU project NanoCMOS, IST 507587.
VGS-Vth=0.0 V VGS-Vth=0.5 V VGS-Vth=1.0 V VGS-Vth=1.5 V VGS-Vth=2.0 V
140
Acknowledgements
90 80 70
References
60 50 40 30 20 10 0 -2.0
(b)
-1.5
-1.0
-0.5
0.0
VDS[V]
Fig. 6. Transfer (a) and output (b) characteristics for a PMOS SOI transistor with a gate length of 48 nm.
Table 1 Typical MOSFET characteristics
Drive current Ion (lA/lm) Threshold voltage Vth (mV) Leakage current Ileak (pA/lm) Subthreshold Slope S (mV/dec) DIBL (mV/V)
NMOS
PMOS
520 330 <1 96 223
102 38 10 91 187
The threshold voltage Vth is measured at 10
7
L/W.
4. Summary N- and p-channel SOI transistors with ultrathin channels down to 1 nm and gate lengths down to 48 nm have successfully been fabricated using the recessed channel concept. Reactive ion etching
[1] ITRS 2003 Update. Available from: