- Email: [email protected]
Fabrication of diamond single-hole transistors using AFM anodization process
Diamond and Related Materials 11 (2002) 387–391
Fabrication of diamond single-hole transistors using AFM anodization process Tokishige Bannoa,b,*, Minoru Tachikia,b, Hokuto Seoa,b, Hitoshi Umezawaa,b, Hiroshi Kawaradaa,b a
CREST, Japan Science and Technology Corporation (JST), Japan School of Science and Engineering, Waseda University, Okubo 3-4-1, Shinjuku-ku, Tokyo 169-8555, Japan
b
Abstract By the field-assisted local anodization technique using an atomic force microscope (AFM), a single-hole transistor has been fabricated on an undoped hydrogen-terminated diamond surface where p-type conduction occurs on the subsurface region. A dual side-gated FET structure has been applied to modulate the island potential in the single-hole transistor. The island size is 230 nm=230 nm, and the width of the barrier is approximately 100 nm. Measurements of the current–gate voltage characteristic at a temperature of 4.6 K show significant non-linearities including a current oscillation suggestive of single-hole transistor behavior. The oscillation that is significantly affected by the application of the side gate potential is explained by the shrinkage of the conductive island with the expansion of the depletion region. 䊚 2002 Elsevier Science B.V. All rights reserved. Keywords: Diamond properties and applications; Single-hole transistor; Coulomb oscillation; Depletion region
1. Introduction Power dissipation and integration issues are of paramount importance for designing future ultralarge scale integrated circuits. Single-electron devices exploiting the Coulomb blockade effect are thought to have the potential to overcome these difficulties because a singleelectron transistor operates with one electron, which can reduce the power consumption and can be applied to highly integrated devices. Measurement of the Coulomb blockade effect has been made possible by continuing advances in the field of nanometer fabrication technology such as local anodization using an atomic force microscope (AFM). Local anodization using an AFM has been used to realize a variety of nanostructures on semiconductors as well as metals w1–6x. In this technique, a voltage is applied between the conductive AFM tip and the material’s surface, resulting in the formation of a narrow oxide line along the path followed by the scanning tip. This technique has the advantage of precise control of local insulator fabrication. We have previously demon*Corresponding author. Tel.yfax: q81-3-5286-3391. E-mail address: [email protected] (T. Banno).
strated local insulation on a diamond surface conductive layer using this technique, and fabrication of a metal– insulator–metal (MIM) tunnel junction w4,5x. The Fowler–Nordheim (F–N) tunneling current analysis indicates that the insulating diamond works as a tunneling barrier. Hydrogen-termination of diamond surface induces ptype surface conduction in the subsurface region without conventional doping w7–9x. For the fabrication of field effect transistors, the surface p-type layer exhibits desirable properties, such as high sheet carrier density (;1013 cmy2) w9x, low surface states density (-1011 cmy2) w10x, low Schottkey barrier heights (-0.7 eV) w11x, and thin channel thickness (-10 nm) w12x. To apply a local anodization technique for device isolation on conventional materials, a very thin conductive layer on an insulator structure such as silicon on insulator (SOI) is necessary. Since undoped diamond is basically an insulating material, we can obtain the isolation simply by eliminating the effect of hydrogen termination on the undoped diamond surface. Owing to these unique properties, a hydrogen-terminated (H-terminated) semiconducting diamond surface is favorable for nanodevice fabrication using an AFM.
0925-9635/02/$ - see front matter 䊚 2002 Elsevier Science B.V. All rights reserved. PII: S 0 9 2 5 - 9 6 3 5 Ž 0 1 . 0 0 6 5 5 - 0
388
T. Banno et al. / Diamond and Related Materials 11 (2002) 387–391
In this paper, the fabrication of single-hole transistors on H-terminated diamond surfaces using the AFM anodization process is demonstrated. To achieve this device, the insulated lines fabricated by the AFM anodization technique are applied to tunneling barriers of the island. To modulate the island potential, we also fabricated a diamond side-gated FET, which shows good lateral modulation of channel conductance at room temperature. By combining that narrow anodized lines and diamond side-gated FET, we fabricated a single-hole transistor w6 x . 2. Experimental Homoepitaxial diamond was deposited on high-pressure synthetic-type Ib diamond (001) using microwave plasma-assisted chemical vapor deposition (MPCVD). The reaction gas was CH4 (0.1%) diluted with H2. The deposition temperature was 750 8C. A dopant gas such as a boron-containing gas was not used. The deposition was completed with pure hydrogen plasma for 2–3 min followed by cooling in pure hydrogen ambient. In the surface p-type layer, a sheet carrier density of 7=1012 cmy2, a hole mobility of 100 cm2 yVs, and a sheet resistance of 9 kVyh were obtained as revealed by Hall effect measurements. The basic fabrication steps by e-beam lithography are described below. First, Au is deposited on the Hterminated diamond surface. The Au contacts are used as ohmic electrodes for the source, drain and gate. The device isolation is achieved by elimination of the surface p-type layer by the exposure of Arq ions, where Au works as a stopping mask for Arq ions. As a result, the surface conductive areas are limited to the region under the Au contact. Au is partially etched by potassium iodide (KI) solution to form a channel resulting in a bare H-terminated surface which is divided into a source, a drain and two gates. The gate region is separated from the channel and two insulator lines are added to form a conductive island by eliminating the surface p-type layer using the AFM local anodization technique where a conductive tip coated by W2C has been scanned on the H-terminated diamond surface by applying a positive sample bias w4,5x. The bias voltage of 5 V is applied during anodization for the fabrication of the gate insulator and the tunneling barrier with a scan speed of 100 nmys. 3. Results and discussion We first measured the characteristics of the dual sidegated FET to confirm the modulation of the channel potential. Fig. 1 shows the schematic and AFM image of the dual side-gated FET where the gate length is 1.4 mm, the gate insulator width is 1.5 mm and the channel width is 130 nm. Before the fabrication of the
Fig. 1. Schematic and AFM image of dual side-gated FET.
gate insulators using the AFM anodization process, current measurements are carried out at room temperature as a function of source-drain voltage. The measurement shows ohmic behavior with the sheet resistance of 15 kVyh, twice of the 9 kVyh by Hall effect measurement. The scatter of Arq ions should cause the increase of the sheet resistance when we separate the device. After the fabrication of the gate insulators, the current measurement at room temperature shows ohmic behavior with the sheet resistance of 308 kVyh. The high sheet resistance is attributed to the expanded depletion region that extends into the H-terminated region from the anodized region. The carrier density should be decreased. IDS –VDS characteristics for the dual side-gated FET measured at room temperature are shown in Fig. 2(a). Lateral modulation of channel conductance has been successfully obtained. Current saturation and pinch-off characteristics are also observed. The maximum transconductance of the FET is 0.8 mS. The threshold voltage of the FET is approximately q2 V. In the linear operation region, minimum sheet resistance was calculated to be 35 kVyh. The gate leakage current is 34 nA at VGSsy20 V. The IDS –VDS characteristics for the same dual side-
T. Banno et al. / Diamond and Related Materials 11 (2002) 387–391
389
as the negative gate voltage increases, and it can be attributed to the reduction of the lateral electric field because of the expanded depletion region on the Hterminated diamond surface in the gate area. We fabricate a single-hole transistor structure on an H-terminated diamond surface by combining the dual side-gated FET with the AFM anodized lines as tunneling barriers to control the island potential. Fig. 3 shows a schematic and AFM images of the diamond singlehole transistor structure. The width of tunnel barriers is 100 nm and the island size is 230 nm=230 nm. The IDS –VGS characteristics at 4.6 K are shown in Fig. 4 where the VDS is y15 V. There are several equally spaced current peaks indicated by arrows in Fig. 4. The peak interval (DVGS) is approximately 0.07 V. Generally, the peak intervals tend to appear periodically and the heights of the peaks tend to be irregular in the Coulomb oscillations of a semiconductor quantum dot when there is no magnetic field w14x. The current oscillations shown in Fig. 4 can be interpreted as a Coulomb blockade effect. First, the nature of the depletion region within the island has to be considered. The sheet resistance of the channel of a side-gated FET was found to increase after fabrication of gate insulators using the AFM anodization technique. This result suggests the existence of a depletion region
Fig. 2. IDS –VDS characteristics of a side-gated FET. (a) Measured at room temperature. (b) Measured at 4.4 K.
gated FET measured at a temperature of 4.4 K are shown in Fig. 2(b). The maximum transconductance of the FET is 0.89 S. The threshold voltage of the FET is approximately 2 V. The gate leakage current is 110 pA at VGSsy20 V. Compared with the IDS –VDS characteristics measured at room temperature, the IDS is suppressed to less than 10 nA in a lower negative drain voltage range. This current suppression increases at lower temperature. These phenomena can be attributed to a contact resistance. Between the H-terminated diamond surface and Au, the relatively low barrier height (0.4 eV or less) w11,13x which is not effective in room temperature cannot be negligible under the low temperature condition, because the thermoelectron energy is not large enough to surpass the barrier height. However, there is little effect of the contact resistance at VDSy5 V and VGS-y5 V. If a single-hole transistor is based on the same side-gated FET structure, the modulation of island potential at a temperature of 4.4 K is possible at VDS-y5 V and VGS-y5 V. The dual sidegated FET structure can be applied to a single-hole transistor to modulate island potential at approximately 4 K. The effect of potential modulation becomes smaller
Fig. 3. Schematic and AFM image of a diamond single-hole transistor.
390
T. Banno et al. / Diamond and Related Materials 11 (2002) 387–391
Fig. 4. IDS –VGS characteristics measured at 4.6 K. VDS is y15 V.
which extends from the boundary between the Hterminated diamond surface and the anodized region. On an oxygen-terminated diamond surface there is pinning of the Fermi energy at ;1.7 eV above the valence band edge w15x. Because of the continuity of the band, the band of the island is bent under Fermi level, producing a depletion region. To interpret current oscillations shown in Fig. 4, we must consider the fact that the depletion region is withdrawn as the gate bias is applied. In other words, the island size becomes larger. The IDS at VDSsy15 V was measured using the same device as a function of the gate bias from 0 to y 30 V. The oscillations are suppressed at 0)VGS)y11 V where the conductive island disappears because of the expansion of the depletion region. The oscillations are observed at VGS-y11 V where the island emerges. Consideration of the depletion region within the island is not sufficient to interpret the behavior of oscillations shown in Fig. 4. The depletion region should expand from the gate-electrode-side boundary (see Fig. 3) of the gate insulator toward the gate electrode. This depletion region prevents the lateral electric field due to the gate bias from reaching the island significantly. The widths of peak intervals in current oscillations do not correspond to the actual potential intervals. The actual potential intervals must be a few times smaller than the width of peak intervals shown in Fig. 4 because only a part of the gate voltage affects the island potential. The reduction of transconductance at VGS-y10 V of Fig. 2(b) must be considered in the analysis of current oscillations for gate voltage at approximately y25 V shown in Fig. 4. The measurement of the dual side-gated FET carried out at room temperature shows ohmic contact, but at a temperature of 4.4 K there was contact resistance between the Au electrode and H-terminated diamond surface. The source–drain voltage of y15 V for current oscillations shown in Fig. 4 is relatively high, but the
voltage drop attributed to contact resistance may make the value consistent. The current oscillations shown in Fig. 4 are evidence of single-hole tunneling. The peak interval (DVGS) should have a spacing of eyCG. In Fig. 4 the peak interval (DVGS) is 0.07 V, which gives an estimate of CG of 2.3=10y18 F. Meanwhile, the island size of 230 nm=230 nm gives an estimate of C8 of 4.6=10y17 F where C8 is the sum of source, drain and gate capacitances. Total capacitance C8 is 20 times larger than the gate capacitance C8. If we consider the shrinkage of the conductive island with the expansion of the depletion region and the fact that only a part of the gate voltage affects the island potential, the total capacitance CS estimated from island size becomes compatible with the gate capacitance C8 calculated from the oscillation peak intervals. Here we neglect the capacitances of source and drain and we obtain the total capacitance as C8CG w16x. We can say that the observed peaks in Fig. 4 are Coulomb oscillations due to single-hole transistor action. 4. Conclusion The results indicate that the fabricated device is single-hole transistor. Fig. 4 reveals the occurrence of oscillations but no zero conductance regions even at 4.6 K. This can be explained by low charging energy. If we fabricate a smaller island, the current oscillations will be clearer, having periodic zero conductance regions. Acknowledgments This work is supported by a grant-in-aid for Center of Excellence (COE) Research from the Ministry of Education, Culture, Sports, Science and Technology. This work is also supported in part by Advanced Research Institute for Science and Engineering, Waseda University. References w1x J.A. Dagata, J. Schneir, H.H. Harary, C.J. Evans, M.Y. Postek, J. Bennet, Appl. Phys. Lett. 56 (1990) 2001. w2x P.M. Campell, E.S. Snow, P.J. McMarr, Appl. Phys. Lett. 66 (1995) 1388. w3x K. Matsumoto, S. Takahashi, M. Ishii, M. Hoshi, A. Kurokawa, S. Ichimura, A. Ando, Jpn. J. Appl. Phys. 34 (Part 1) (1995) 1387. w4x M. Tachiki, T. Fukuda, K. Sugata, H. Seo, H. Umezawa, H. Kawarada, Appl. Surf. Sci. 159-160 (2000) 578. w5x M. Tachiki, T. Fukuda, K. Sugata, H. Seo, H. Umezawa, H. Kawarada, Jpn. J. Appl. Phys. 39 (2000) 4631. w6x K. Matsumoto, M. Ishii, K. Segawa, Y. Oka, B.J. Vartanian, J.S. Hariss, Appl. Phys. Lett. 68 (1996) 34. w7x T. Maki, S. Shikama, M. Komori, Y. Sakaguchi, K. Sakuta, T. Kobayashi, Jpn. J. Appl. Phys. 31 (1992) L1446. w8x H. Kawarada, Surf. Sci. Rep. 26 (1996) 205. w9x K. Hayashi, S. Yamanaka, H. Watanabe, T. Sekiguchi, H. Okushi, K. Kajimura, J. Appl. Phys. 81 (1997) 744.
T. Banno et al. / Diamond and Related Materials 11 (2002) 387–391 w10x Y. Yun, T. Maki, T. Kobayashi, J. Appl. Phys. 82 (1997) 3422. w11x M. Aoki, H. Kawarada, Jpn. J. Appl. Phys. 33 (1994) 708. w12x H. Noda, A. Hokazono, H. Kawarada, Diam. Relat. Mater. 6 (1997) 865. w13x H.J. Looi, L.Y.S. Pang, M.D. Whitfield, J.S. Foord, R.B. Jackman, Diam. Relat. Mater. 9 (2000) 975.
391
w14x R.E. Prange, S.M. Girvin (Eds.), The Quantum Hall Effect, Springer, 1987. w15x J.C. Zheng, X.N. Xie, A.T.S. Wee, K.P. Loh, Diam. Relat. Mater. 10 (2001) 500. w16x L.P. Kouwenhoven, N.C. van der Vaart, A.T. Johnson, W. Kool, C.J.P.M. Harmans, J.G. Williamson, A.A.M. Staring, C.T. Foxon, Z. Phys. B, Condens. Matter 85 (1991) 367.
Fabrication of diamond single-hole transistors using AFM anodization process Tokishige Bannoa,b,*, Minoru Tachikia,b, Hokuto Seoa,b, Hitoshi Umezawaa,b, Hiroshi Kawaradaa,b a
CREST, Japan Science and Technology Corporation (JST), Japan School of Science and Engineering, Waseda University, Okubo 3-4-1, Shinjuku-ku, Tokyo 169-8555, Japan
b
Abstract By the field-assisted local anodization technique using an atomic force microscope (AFM), a single-hole transistor has been fabricated on an undoped hydrogen-terminated diamond surface where p-type conduction occurs on the subsurface region. A dual side-gated FET structure has been applied to modulate the island potential in the single-hole transistor. The island size is 230 nm=230 nm, and the width of the barrier is approximately 100 nm. Measurements of the current–gate voltage characteristic at a temperature of 4.6 K show significant non-linearities including a current oscillation suggestive of single-hole transistor behavior. The oscillation that is significantly affected by the application of the side gate potential is explained by the shrinkage of the conductive island with the expansion of the depletion region. 䊚 2002 Elsevier Science B.V. All rights reserved. Keywords: Diamond properties and applications; Single-hole transistor; Coulomb oscillation; Depletion region
1. Introduction Power dissipation and integration issues are of paramount importance for designing future ultralarge scale integrated circuits. Single-electron devices exploiting the Coulomb blockade effect are thought to have the potential to overcome these difficulties because a singleelectron transistor operates with one electron, which can reduce the power consumption and can be applied to highly integrated devices. Measurement of the Coulomb blockade effect has been made possible by continuing advances in the field of nanometer fabrication technology such as local anodization using an atomic force microscope (AFM). Local anodization using an AFM has been used to realize a variety of nanostructures on semiconductors as well as metals w1–6x. In this technique, a voltage is applied between the conductive AFM tip and the material’s surface, resulting in the formation of a narrow oxide line along the path followed by the scanning tip. This technique has the advantage of precise control of local insulator fabrication. We have previously demon*Corresponding author. Tel.yfax: q81-3-5286-3391. E-mail address: [email protected] (T. Banno).
strated local insulation on a diamond surface conductive layer using this technique, and fabrication of a metal– insulator–metal (MIM) tunnel junction w4,5x. The Fowler–Nordheim (F–N) tunneling current analysis indicates that the insulating diamond works as a tunneling barrier. Hydrogen-termination of diamond surface induces ptype surface conduction in the subsurface region without conventional doping w7–9x. For the fabrication of field effect transistors, the surface p-type layer exhibits desirable properties, such as high sheet carrier density (;1013 cmy2) w9x, low surface states density (-1011 cmy2) w10x, low Schottkey barrier heights (-0.7 eV) w11x, and thin channel thickness (-10 nm) w12x. To apply a local anodization technique for device isolation on conventional materials, a very thin conductive layer on an insulator structure such as silicon on insulator (SOI) is necessary. Since undoped diamond is basically an insulating material, we can obtain the isolation simply by eliminating the effect of hydrogen termination on the undoped diamond surface. Owing to these unique properties, a hydrogen-terminated (H-terminated) semiconducting diamond surface is favorable for nanodevice fabrication using an AFM.
0925-9635/02/$ - see front matter 䊚 2002 Elsevier Science B.V. All rights reserved. PII: S 0 9 2 5 - 9 6 3 5 Ž 0 1 . 0 0 6 5 5 - 0
388
T. Banno et al. / Diamond and Related Materials 11 (2002) 387–391
In this paper, the fabrication of single-hole transistors on H-terminated diamond surfaces using the AFM anodization process is demonstrated. To achieve this device, the insulated lines fabricated by the AFM anodization technique are applied to tunneling barriers of the island. To modulate the island potential, we also fabricated a diamond side-gated FET, which shows good lateral modulation of channel conductance at room temperature. By combining that narrow anodized lines and diamond side-gated FET, we fabricated a single-hole transistor w6 x . 2. Experimental Homoepitaxial diamond was deposited on high-pressure synthetic-type Ib diamond (001) using microwave plasma-assisted chemical vapor deposition (MPCVD). The reaction gas was CH4 (0.1%) diluted with H2. The deposition temperature was 750 8C. A dopant gas such as a boron-containing gas was not used. The deposition was completed with pure hydrogen plasma for 2–3 min followed by cooling in pure hydrogen ambient. In the surface p-type layer, a sheet carrier density of 7=1012 cmy2, a hole mobility of 100 cm2 yVs, and a sheet resistance of 9 kVyh were obtained as revealed by Hall effect measurements. The basic fabrication steps by e-beam lithography are described below. First, Au is deposited on the Hterminated diamond surface. The Au contacts are used as ohmic electrodes for the source, drain and gate. The device isolation is achieved by elimination of the surface p-type layer by the exposure of Arq ions, where Au works as a stopping mask for Arq ions. As a result, the surface conductive areas are limited to the region under the Au contact. Au is partially etched by potassium iodide (KI) solution to form a channel resulting in a bare H-terminated surface which is divided into a source, a drain and two gates. The gate region is separated from the channel and two insulator lines are added to form a conductive island by eliminating the surface p-type layer using the AFM local anodization technique where a conductive tip coated by W2C has been scanned on the H-terminated diamond surface by applying a positive sample bias w4,5x. The bias voltage of 5 V is applied during anodization for the fabrication of the gate insulator and the tunneling barrier with a scan speed of 100 nmys. 3. Results and discussion We first measured the characteristics of the dual sidegated FET to confirm the modulation of the channel potential. Fig. 1 shows the schematic and AFM image of the dual side-gated FET where the gate length is 1.4 mm, the gate insulator width is 1.5 mm and the channel width is 130 nm. Before the fabrication of the
Fig. 1. Schematic and AFM image of dual side-gated FET.
gate insulators using the AFM anodization process, current measurements are carried out at room temperature as a function of source-drain voltage. The measurement shows ohmic behavior with the sheet resistance of 15 kVyh, twice of the 9 kVyh by Hall effect measurement. The scatter of Arq ions should cause the increase of the sheet resistance when we separate the device. After the fabrication of the gate insulators, the current measurement at room temperature shows ohmic behavior with the sheet resistance of 308 kVyh. The high sheet resistance is attributed to the expanded depletion region that extends into the H-terminated region from the anodized region. The carrier density should be decreased. IDS –VDS characteristics for the dual side-gated FET measured at room temperature are shown in Fig. 2(a). Lateral modulation of channel conductance has been successfully obtained. Current saturation and pinch-off characteristics are also observed. The maximum transconductance of the FET is 0.8 mS. The threshold voltage of the FET is approximately q2 V. In the linear operation region, minimum sheet resistance was calculated to be 35 kVyh. The gate leakage current is 34 nA at VGSsy20 V. The IDS –VDS characteristics for the same dual side-
T. Banno et al. / Diamond and Related Materials 11 (2002) 387–391
389
as the negative gate voltage increases, and it can be attributed to the reduction of the lateral electric field because of the expanded depletion region on the Hterminated diamond surface in the gate area. We fabricate a single-hole transistor structure on an H-terminated diamond surface by combining the dual side-gated FET with the AFM anodized lines as tunneling barriers to control the island potential. Fig. 3 shows a schematic and AFM images of the diamond singlehole transistor structure. The width of tunnel barriers is 100 nm and the island size is 230 nm=230 nm. The IDS –VGS characteristics at 4.6 K are shown in Fig. 4 where the VDS is y15 V. There are several equally spaced current peaks indicated by arrows in Fig. 4. The peak interval (DVGS) is approximately 0.07 V. Generally, the peak intervals tend to appear periodically and the heights of the peaks tend to be irregular in the Coulomb oscillations of a semiconductor quantum dot when there is no magnetic field w14x. The current oscillations shown in Fig. 4 can be interpreted as a Coulomb blockade effect. First, the nature of the depletion region within the island has to be considered. The sheet resistance of the channel of a side-gated FET was found to increase after fabrication of gate insulators using the AFM anodization technique. This result suggests the existence of a depletion region
Fig. 2. IDS –VDS characteristics of a side-gated FET. (a) Measured at room temperature. (b) Measured at 4.4 K.
gated FET measured at a temperature of 4.4 K are shown in Fig. 2(b). The maximum transconductance of the FET is 0.89 S. The threshold voltage of the FET is approximately 2 V. The gate leakage current is 110 pA at VGSsy20 V. Compared with the IDS –VDS characteristics measured at room temperature, the IDS is suppressed to less than 10 nA in a lower negative drain voltage range. This current suppression increases at lower temperature. These phenomena can be attributed to a contact resistance. Between the H-terminated diamond surface and Au, the relatively low barrier height (0.4 eV or less) w11,13x which is not effective in room temperature cannot be negligible under the low temperature condition, because the thermoelectron energy is not large enough to surpass the barrier height. However, there is little effect of the contact resistance at VDSy5 V and VGS-y5 V. If a single-hole transistor is based on the same side-gated FET structure, the modulation of island potential at a temperature of 4.4 K is possible at VDS-y5 V and VGS-y5 V. The dual sidegated FET structure can be applied to a single-hole transistor to modulate island potential at approximately 4 K. The effect of potential modulation becomes smaller
Fig. 3. Schematic and AFM image of a diamond single-hole transistor.
390
T. Banno et al. / Diamond and Related Materials 11 (2002) 387–391
Fig. 4. IDS –VGS characteristics measured at 4.6 K. VDS is y15 V.
which extends from the boundary between the Hterminated diamond surface and the anodized region. On an oxygen-terminated diamond surface there is pinning of the Fermi energy at ;1.7 eV above the valence band edge w15x. Because of the continuity of the band, the band of the island is bent under Fermi level, producing a depletion region. To interpret current oscillations shown in Fig. 4, we must consider the fact that the depletion region is withdrawn as the gate bias is applied. In other words, the island size becomes larger. The IDS at VDSsy15 V was measured using the same device as a function of the gate bias from 0 to y 30 V. The oscillations are suppressed at 0)VGS)y11 V where the conductive island disappears because of the expansion of the depletion region. The oscillations are observed at VGS-y11 V where the island emerges. Consideration of the depletion region within the island is not sufficient to interpret the behavior of oscillations shown in Fig. 4. The depletion region should expand from the gate-electrode-side boundary (see Fig. 3) of the gate insulator toward the gate electrode. This depletion region prevents the lateral electric field due to the gate bias from reaching the island significantly. The widths of peak intervals in current oscillations do not correspond to the actual potential intervals. The actual potential intervals must be a few times smaller than the width of peak intervals shown in Fig. 4 because only a part of the gate voltage affects the island potential. The reduction of transconductance at VGS-y10 V of Fig. 2(b) must be considered in the analysis of current oscillations for gate voltage at approximately y25 V shown in Fig. 4. The measurement of the dual side-gated FET carried out at room temperature shows ohmic contact, but at a temperature of 4.4 K there was contact resistance between the Au electrode and H-terminated diamond surface. The source–drain voltage of y15 V for current oscillations shown in Fig. 4 is relatively high, but the
voltage drop attributed to contact resistance may make the value consistent. The current oscillations shown in Fig. 4 are evidence of single-hole tunneling. The peak interval (DVGS) should have a spacing of eyCG. In Fig. 4 the peak interval (DVGS) is 0.07 V, which gives an estimate of CG of 2.3=10y18 F. Meanwhile, the island size of 230 nm=230 nm gives an estimate of C8 of 4.6=10y17 F where C8 is the sum of source, drain and gate capacitances. Total capacitance C8 is 20 times larger than the gate capacitance C8. If we consider the shrinkage of the conductive island with the expansion of the depletion region and the fact that only a part of the gate voltage affects the island potential, the total capacitance CS estimated from island size becomes compatible with the gate capacitance C8 calculated from the oscillation peak intervals. Here we neglect the capacitances of source and drain and we obtain the total capacitance as C8CG w16x. We can say that the observed peaks in Fig. 4 are Coulomb oscillations due to single-hole transistor action. 4. Conclusion The results indicate that the fabricated device is single-hole transistor. Fig. 4 reveals the occurrence of oscillations but no zero conductance regions even at 4.6 K. This can be explained by low charging energy. If we fabricate a smaller island, the current oscillations will be clearer, having periodic zero conductance regions. Acknowledgments This work is supported by a grant-in-aid for Center of Excellence (COE) Research from the Ministry of Education, Culture, Sports, Science and Technology. This work is also supported in part by Advanced Research Institute for Science and Engineering, Waseda University. References w1x J.A. Dagata, J. Schneir, H.H. Harary, C.J. Evans, M.Y. Postek, J. Bennet, Appl. Phys. Lett. 56 (1990) 2001. w2x P.M. Campell, E.S. Snow, P.J. McMarr, Appl. Phys. Lett. 66 (1995) 1388. w3x K. Matsumoto, S. Takahashi, M. Ishii, M. Hoshi, A. Kurokawa, S. Ichimura, A. Ando, Jpn. J. Appl. Phys. 34 (Part 1) (1995) 1387. w4x M. Tachiki, T. Fukuda, K. Sugata, H. Seo, H. Umezawa, H. Kawarada, Appl. Surf. Sci. 159-160 (2000) 578. w5x M. Tachiki, T. Fukuda, K. Sugata, H. Seo, H. Umezawa, H. Kawarada, Jpn. J. Appl. Phys. 39 (2000) 4631. w6x K. Matsumoto, M. Ishii, K. Segawa, Y. Oka, B.J. Vartanian, J.S. Hariss, Appl. Phys. Lett. 68 (1996) 34. w7x T. Maki, S. Shikama, M. Komori, Y. Sakaguchi, K. Sakuta, T. Kobayashi, Jpn. J. Appl. Phys. 31 (1992) L1446. w8x H. Kawarada, Surf. Sci. Rep. 26 (1996) 205. w9x K. Hayashi, S. Yamanaka, H. Watanabe, T. Sekiguchi, H. Okushi, K. Kajimura, J. Appl. Phys. 81 (1997) 744.
T. Banno et al. / Diamond and Related Materials 11 (2002) 387–391 w10x Y. Yun, T. Maki, T. Kobayashi, J. Appl. Phys. 82 (1997) 3422. w11x M. Aoki, H. Kawarada, Jpn. J. Appl. Phys. 33 (1994) 708. w12x H. Noda, A. Hokazono, H. Kawarada, Diam. Relat. Mater. 6 (1997) 865. w13x H.J. Looi, L.Y.S. Pang, M.D. Whitfield, J.S. Foord, R.B. Jackman, Diam. Relat. Mater. 9 (2000) 975.
391
w14x R.E. Prange, S.M. Girvin (Eds.), The Quantum Hall Effect, Springer, 1987. w15x J.C. Zheng, X.N. Xie, A.T.S. Wee, K.P. Loh, Diam. Relat. Mater. 10 (2001) 500. w16x L.P. Kouwenhoven, N.C. van der Vaart, A.T. Johnson, W. Kool, C.J.P.M. Harmans, J.G. Williamson, A.A.M. Staring, C.T. Foxon, Z. Phys. B, Condens. Matter 85 (1991) 367.