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Fabrication of diamond in-plane-gated field effect transistors using oxygen plasma etching
Diamond and Related Materials 12 (2003) 408–412
Fabrication of diamond in-plane-gated field effect transistors using oxygen plasma etching Tokishige Bannoa,b,*, Minoru Tachikia,b, Kazushi Nakazawaa,b, Yu Sumikawaa,b, Hitoshi Umezawaa,b, Hiroshi Kawaradaa,b,c a
b
CREST, JST (Japan Science and Technology Corporation), Tsukuba, Japan School of Science and Engineering, Waseda University, Okubo 3-4-1, Shinjuku-ku, Tokyo 169-8555, Japan c FCT ProjectyJFCC, Tokyo, Japan
Abstract Diamond dual in-plane-gated field effect transistors with very low gate leakage current have been fabricated on an undoped hydrogen-terminated diamond p-type surface using oxygen plasma etching. Adjusting the threshold voltage optimally by one side gate, lateral electric field from the other side gate modulates the channel conductance. The oxygen plasma etching of 60 nm in depth fully isolated the channel of the hydrogen-terminated diamond surface conductive layer from the side gates resulting very low gate leakage current (-1 pA at y60 V) at room temperature. This feature provides a necessary condition for the fabrication of diamond single-hole transistors operated at room temperature. 䊚 2003 Elsevier Science B.V. All rights reserved. Keywords: Diamond properties applications; In-plane-gate; Oxygen plasma; Gate leakage
1. Introduction Single-electronyhole devices exploiting the Coulomb blockade effect are thought to have the potential to overcome difficulties of power dissipation and integration issues because a single-electronyhole transistor operates with one electronyhole. The device can reduce the power consumption and can be applied to highly integrated devices w1–6x. But single-electronyhole devices must operate at room temperature to realize the commercial use. For room temperature operation of diamond single-hole transistors, small conductive islands of less than 10 nm in radius and very low gate leakage current are necessary w1,2x. We have previously demonstrated diamond singlehole transistors at 4.6 K w7x and 77 K w8x on the hydrogen-terminated diamond surface conductive layer fabricated by local anodization technique using an atomic force microscope (AFM) and clear Coulomb oscillations have been observed successfully. To achieve those devices, an in-plane-gated FET structure which shows good lateral modulation of channel conductance has *Corresponding author. Tel.yfax: q81-3-5286-3391. E-mail address: [email protected] (T. Banno).
been applied to modulate the island potential in the diamond single-hole transistors. However, a diamond in-plane-gated FET structure using the AFM anodized area for gate insulators has the gate leakage current large enough to disturb the Coulomb blockade effect at room temperature. This time, we fabricate a new type diamond in-plane-gated FET structure using oxygen plasma etching to separate the side gates and the channel by grooves terminated by oxygen to reduce the gate leakage current at room temperature. The gate leakage current has been decreased less than 1 pA even VGSsy60 V at room temperature as a result. In this paper, two types of new diamond in-planegated FETs with a wide channel of 3.2 mm in width and a narrow channel of 200 nm in width are demonstrated. Both types of new diamond in-plane-gated FETs have dual side gates. The one side gate fixes the threshold voltage, and the other side gate modulates the channel conductance. 2. Material and fabrication Homoepitaxial diamond was deposited on high-pressure synthetic-type Ib diamond (0 0 1) using microwave
0925-9635/03/$ - see front matter 䊚 2003 Elsevier Science B.V. All rights reserved. PII: S 0 9 2 5 - 9 6 3 5 Ž 0 3 . 0 0 0 3 9 - 6
T. Banno et al. / Diamond and Related Materials 12 (2003) 408–412
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3. Results and discussion We measured the characteristics of the diamond inplane-gated FET with the channel of 3.2 mm in width at room temperature. Fig. 1 shows the AFM image of that diamond in-plane-gated FET where the gate length is 4.8 mm, the channel width is 3.2 mm and the distance between the channel and the gate is 700 nm. Current measurements are carried out at room temperature as a function of source–drain voltage without applying the side-gate voltages. The measurement shows ohmic behavior with the sheet resistance of 12 kVyh, which is twice of that value by Hall effect measurement (5.5
Fig. 1. AFM image of the diamond in-plane-gated FET. The channel and side gates are bare hydrogen-terminated diamond p-type surface. The dark areas are oxygen plasma etched regions. The depth is 60 nm.
plasma-assisted chemical vapor deposition. The reaction gas was CH4 (0.1%) diluted with H2. The deposition temperature was 750 8C. A dopant gas such as a boroncontaining gas was not used. The deposition was completed with pure hydrogen plasma for 2–3 min followed by cooling in pure hydrogen ambient. Hydrogen-termination of diamond surface induces p-type surface conduction in the subsurface region without conventional doping w9–14x. In the surface p-type layer of diamond, a sheet carrier density of 1.5=1013 ycm2, a hole mobility of 73 cm2 yV s, and a sheet resistance of 5.5 kVyh were obtained by Hall effect measurements. The in-plane-gated FET with a wide channel of 3.2 mm in width is shown in Fig. 1. Another device with a narrow channel of 200 nm in width is shown in Fig. 2. Au is deposited on the hydrogen-terminated diamond surface. Electron-beam lithography using ZEP 520 resist and potassium iodide (KI) wet etch were used to define the channel and two side-gates. The Au is patterned into a source–channel–drain-pad area and two side-gate-pad areas. The Au contacts are used as ohmic electrodes for the source, drain and gate. The device isolation and gate–channel insulating are formed by oxygen plasma etching of 60 nm in depth, where Au works as a stopping mask for oxygen plasma. The surface conductive areas are limited to the region under the Au contact as a result. Au is partially etched by potassium iodide solution to form a channel with bare hydrogen-terminated surface. The channel is separated from two side gates by grooves.
Fig. 2. Schematic and AFM image of the narrow diamond in-planegated FET.
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T. Banno et al. / Diamond and Related Materials 12 (2003) 408–412
Fig. 3. IDS –VDS characteristics of the diamond in-plane-gated FET with the channel of 3.2 mm width measured at room temperature. The right side gate voltage is fixed at 50 V.
kVyh). The relatively high sheet resistance is attributed to the depletion region expanding into the hydrogenterminated region from the oxygen-terminated side wall by oxygen plasma etching. IDS –VDS characteristics for that diamond in-plane-gated FET measured at room temperature are shown in Fig. 3. Lateral modulation of channel conductance has been successfully obtained. The minimum sheet resistance was estimated to be 31 kVyh. The threshold voltage is variable as a function of the right-side-gate voltage and left-side-gate voltage modulates the channel conductance. In this case, the right-side-gate voltage is 50 V. Because of the wide channel, the ranges of side-gate voltages are high. The pinch-off characteristic is observed and the threshold voltage is 80 V. When the right-side-gate voltage is less than 50 V, the pinch-off characteristic cannot be obtained through the same range of left-side-gate voltage of 0– 80 V. The maximum transconductance of the FET is 5 mS. Here is the operation mechanism for the diamond inplane-gated FET fabricated by the oxygen plasma etching. The depletion region expands to the channel of the hydrogen-terminated diamond surface from the side wall of the oxygen-terminated diamond surface. On oxygenterminated diamond surfaces, there is pinning of the Fermi level at ;1.7 eV above the valence band edge w15x. Because of the band continuity, the band of the channel is bent under Fermi level, producing a depletion region. The fixed right-side-gate voltage causes the corresponded distance of the depletion region and reduces the channel width from right side of the channel. The
left end of the depletion region is the pinch-off point. This point can be varied as a function of the right-sidegate voltage. It is easy to change the threshold voltage. This diamond in-plane-gated FET with the channel of 3.2 mm operates as normally on because the depletion region can not cover the full width of the channel. Leftside-gate voltage modulates the channel conductance by extending the depletion region in the left-side of the channel. That device is also measured with the both side-gates functioned simultaneously. The maximum transconductance is 8 mS, almost twice of the value of former measurement with fixed right-side-gate voltage. The pinch-off is observed and the threshold voltage is 42 V. For the top-gated type devices, this simultaneously functioned dual side gates would be useful to change the threshold voltage w6x. The threshold voltage characteristics of the diamond in-plane-gated FET with the channel of 3.2 mm in width are also measured at room temperature as shown in Fig. 4. Variety of the threshold voltage characteristics corresponding to the each right-side-gate voltage is shown. The drain voltage is applied at y100 mV. The threshold voltage is changed easily with a function of the rightside-gate voltage. The gate leakage current of the diamond in-planegated FET with the channel of 3.2 mm is also measured at room temperature as shown in Fig. 5. The gate leakage current is less than 1 pA at room temperature even if the left-side-gate is at the high bias of y60 V. The oxygen plasma etching of 60 nm in depth fully
Fig. 4. IDS –VGS characteristics of the diamond in-plane-gated FET with the channel of 3.2 mm width measured at room temperature. The right side gate voltage is varied to control the pinch-off point.
T. Banno et al. / Diamond and Related Materials 12 (2003) 408–412
Fig. 5. Gate leakage current of the diamond in-plane-gated FET with the channel of 3.2 mm in width measured at room temperature. The trench of 700 nm in width and 60 nm in depth as the vacuum gate insulator separates the channel and side gates well and the gate leakage current is less than 1 pA even if the side gate is biased at y60 V at room temperature.
isolated the channel of the hydrogen-terminated diamond surface conductive layer from the two side gates. The diamond in-plane-gated FET with a relatively narrow channel of 200 nm is also fabricated by oxygen plasma etching of 60 nm in depth. Fig. 2 shows the schematic and AFM image of that diamond in-planegated FET where the gate length is 2 mm, the channel
411
width is 200 nm and the distance between the channel and the gate is 700 nm. The IDS –VDS characteristics for that diamond in-plane-gated FET measured at room temperature are shown in Fig. 6. The range of side gate voltage is smaller than wide channel version of 3.2 mm. Lateral modulation of channel conductance is obtained. The minimum sheet resistance was calculated to be 300 kVyh. When the right-side-gate voltage is 0 V, the pinch-off characteristic is observed and the threshold voltage is 9 V. The maximum transconductance of that FET is 0.2 mS. The gate leakage current is less than 1 pA at room temperature when the left-side-gate is at the bias of y10 V. This narrow diamond in-plane-gated FET operates as normally on, too. This fact suggests that the depletion region caused by the oxygen-terminated diamond surface of channel side wall extends less than 100 nm when the side gate is at the bias of 0 V. The high sheet resistance of 300 kVyh is explained by the large proportion of the depletion region width in the channel. If two tunneling barriers are added to that narrowed channel by AFM anodization process w16x to fabricate the diamond conductive island which is shrank by the adjustment of the right-side-gate voltage to increase island charging energy large enough to overcome the thermal energy at room temperature w7x, the diamond single-hole transistors could be realized and would operate at higher temperature than previous works w7,8x because the gate leakage current is very low. 4. Conclusion We have succeeded to reduce the gate leakage current of the diamond in-plane-gated FET using oxygen plasma etching which electrically full-separates hydrogen-terminated diamond surface conductive regions. Acknowledgments This work is supported by a Grant-in-Aid for Center of Excellence (COE) Research from the Ministry of Education, Culture, Sports, Science and Technology. This work is also supported in part by Advanced Research Institute for Science and Engineering, Waseda University. References
Fig. 6. IDS –VDS characteristics of the diamond in-plane-gated FET with the narrow channel of 200 nm width measured at room temperature. The right side gate voltage is fixed at 0 V.
w1x K. Matsumoto, M. Ishii, K. Segawa, Y. Oka, B.J. Vartanian, J.S. Hariss, Appl. Phys. Lett. 68 (1996) 34. w2x K. Yano, T. Ishii, T. Hashimoto, T. Kobayashi, F. Murai, K. Seki, Appl. Phys. Lett. 67 (1995) 828. w3x P.M. Campell, E.S. Snow, P.J. McMarr, Appl. Phys. Lett. 66 (1995) 1388. w4x S. Kasai, H. Hasegawa, Jpn. J. Appl. Phys. 40 (2001) 2029.
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T. Banno et al. / Diamond and Related Materials 12 (2003) 408–412
w5x R.A. Smith, H. Ahmed, J. Appl. Phys. 81 (1997) 2699. w6x T. Tsutsumi, K. Ishii, H. Hiroshima, S. Kanemaru, E. Suzuki, K. Tomizawa, Jpn. J. Appl. Phys. 41 (2002) 4419. w7x T. Banno, M. Tachiki, H. Seo, H. Umezawa, H. Kawarada, Diam. Relat. Mater. 11 (2002) 387. w8x M. Tachiki, H. Seo, T. Banno, Y. Sumikawa, H. Umezawa, H. Kawarada, Appl. Phys. Lett. 81 (2002) 2854. w9x T. Maki, S. Shikama, M. Komori, Y. Sakaguchi, K. Sakuta, T. Kobayashi, Jpn. J. Appl. Phys. 31 (1992) L1446. w10x H. Kawarada, Surf. Sci. Rep. 26 (1996) 205.
w11x K. Hayashi, S. Yamanaka, H. Watanabe, T. Sekiguchi, H. Okushi, K. Kajimura, J. Appl. Phys. 81 (1997) 744. w12x Y. Yun, T. Maki, T. Kobayashi, J. Appl. Phys. 82 (1997) 3422. w13x M. Aoki, H. Kawarada, Jpn. J. Appl. Phys. 33 (1994) 708. w14x H. Noda, A. Hokazono, H. Kawarada, Diam. Relat. Mater. 6 (1997) 865. w15x J.C. Zheng, X.N. Xie, A.T.S. Wee, K.P. Loh, Diam. Relat. Mater. 10 (2001) 500. w16x H. Seo, M. Tachiki, T. Banno, Y. Sumikawa, H. Umezawa, H. Kawarada, Jpn. J. Appl. Phys. 41 (2002) 4980.
Fabrication of diamond in-plane-gated field effect transistors using oxygen plasma etching Tokishige Bannoa,b,*, Minoru Tachikia,b, Kazushi Nakazawaa,b, Yu Sumikawaa,b, Hitoshi Umezawaa,b, Hiroshi Kawaradaa,b,c a
b
CREST, JST (Japan Science and Technology Corporation), Tsukuba, Japan School of Science and Engineering, Waseda University, Okubo 3-4-1, Shinjuku-ku, Tokyo 169-8555, Japan c FCT ProjectyJFCC, Tokyo, Japan
Abstract Diamond dual in-plane-gated field effect transistors with very low gate leakage current have been fabricated on an undoped hydrogen-terminated diamond p-type surface using oxygen plasma etching. Adjusting the threshold voltage optimally by one side gate, lateral electric field from the other side gate modulates the channel conductance. The oxygen plasma etching of 60 nm in depth fully isolated the channel of the hydrogen-terminated diamond surface conductive layer from the side gates resulting very low gate leakage current (-1 pA at y60 V) at room temperature. This feature provides a necessary condition for the fabrication of diamond single-hole transistors operated at room temperature. 䊚 2003 Elsevier Science B.V. All rights reserved. Keywords: Diamond properties applications; In-plane-gate; Oxygen plasma; Gate leakage
1. Introduction Single-electronyhole devices exploiting the Coulomb blockade effect are thought to have the potential to overcome difficulties of power dissipation and integration issues because a single-electronyhole transistor operates with one electronyhole. The device can reduce the power consumption and can be applied to highly integrated devices w1–6x. But single-electronyhole devices must operate at room temperature to realize the commercial use. For room temperature operation of diamond single-hole transistors, small conductive islands of less than 10 nm in radius and very low gate leakage current are necessary w1,2x. We have previously demonstrated diamond singlehole transistors at 4.6 K w7x and 77 K w8x on the hydrogen-terminated diamond surface conductive layer fabricated by local anodization technique using an atomic force microscope (AFM) and clear Coulomb oscillations have been observed successfully. To achieve those devices, an in-plane-gated FET structure which shows good lateral modulation of channel conductance has *Corresponding author. Tel.yfax: q81-3-5286-3391. E-mail address: [email protected] (T. Banno).
been applied to modulate the island potential in the diamond single-hole transistors. However, a diamond in-plane-gated FET structure using the AFM anodized area for gate insulators has the gate leakage current large enough to disturb the Coulomb blockade effect at room temperature. This time, we fabricate a new type diamond in-plane-gated FET structure using oxygen plasma etching to separate the side gates and the channel by grooves terminated by oxygen to reduce the gate leakage current at room temperature. The gate leakage current has been decreased less than 1 pA even VGSsy60 V at room temperature as a result. In this paper, two types of new diamond in-planegated FETs with a wide channel of 3.2 mm in width and a narrow channel of 200 nm in width are demonstrated. Both types of new diamond in-plane-gated FETs have dual side gates. The one side gate fixes the threshold voltage, and the other side gate modulates the channel conductance. 2. Material and fabrication Homoepitaxial diamond was deposited on high-pressure synthetic-type Ib diamond (0 0 1) using microwave
0925-9635/03/$ - see front matter 䊚 2003 Elsevier Science B.V. All rights reserved. PII: S 0 9 2 5 - 9 6 3 5 Ž 0 3 . 0 0 0 3 9 - 6
T. Banno et al. / Diamond and Related Materials 12 (2003) 408–412
409
3. Results and discussion We measured the characteristics of the diamond inplane-gated FET with the channel of 3.2 mm in width at room temperature. Fig. 1 shows the AFM image of that diamond in-plane-gated FET where the gate length is 4.8 mm, the channel width is 3.2 mm and the distance between the channel and the gate is 700 nm. Current measurements are carried out at room temperature as a function of source–drain voltage without applying the side-gate voltages. The measurement shows ohmic behavior with the sheet resistance of 12 kVyh, which is twice of that value by Hall effect measurement (5.5
Fig. 1. AFM image of the diamond in-plane-gated FET. The channel and side gates are bare hydrogen-terminated diamond p-type surface. The dark areas are oxygen plasma etched regions. The depth is 60 nm.
plasma-assisted chemical vapor deposition. The reaction gas was CH4 (0.1%) diluted with H2. The deposition temperature was 750 8C. A dopant gas such as a boroncontaining gas was not used. The deposition was completed with pure hydrogen plasma for 2–3 min followed by cooling in pure hydrogen ambient. Hydrogen-termination of diamond surface induces p-type surface conduction in the subsurface region without conventional doping w9–14x. In the surface p-type layer of diamond, a sheet carrier density of 1.5=1013 ycm2, a hole mobility of 73 cm2 yV s, and a sheet resistance of 5.5 kVyh were obtained by Hall effect measurements. The in-plane-gated FET with a wide channel of 3.2 mm in width is shown in Fig. 1. Another device with a narrow channel of 200 nm in width is shown in Fig. 2. Au is deposited on the hydrogen-terminated diamond surface. Electron-beam lithography using ZEP 520 resist and potassium iodide (KI) wet etch were used to define the channel and two side-gates. The Au is patterned into a source–channel–drain-pad area and two side-gate-pad areas. The Au contacts are used as ohmic electrodes for the source, drain and gate. The device isolation and gate–channel insulating are formed by oxygen plasma etching of 60 nm in depth, where Au works as a stopping mask for oxygen plasma. The surface conductive areas are limited to the region under the Au contact as a result. Au is partially etched by potassium iodide solution to form a channel with bare hydrogen-terminated surface. The channel is separated from two side gates by grooves.
Fig. 2. Schematic and AFM image of the narrow diamond in-planegated FET.
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T. Banno et al. / Diamond and Related Materials 12 (2003) 408–412
Fig. 3. IDS –VDS characteristics of the diamond in-plane-gated FET with the channel of 3.2 mm width measured at room temperature. The right side gate voltage is fixed at 50 V.
kVyh). The relatively high sheet resistance is attributed to the depletion region expanding into the hydrogenterminated region from the oxygen-terminated side wall by oxygen plasma etching. IDS –VDS characteristics for that diamond in-plane-gated FET measured at room temperature are shown in Fig. 3. Lateral modulation of channel conductance has been successfully obtained. The minimum sheet resistance was estimated to be 31 kVyh. The threshold voltage is variable as a function of the right-side-gate voltage and left-side-gate voltage modulates the channel conductance. In this case, the right-side-gate voltage is 50 V. Because of the wide channel, the ranges of side-gate voltages are high. The pinch-off characteristic is observed and the threshold voltage is 80 V. When the right-side-gate voltage is less than 50 V, the pinch-off characteristic cannot be obtained through the same range of left-side-gate voltage of 0– 80 V. The maximum transconductance of the FET is 5 mS. Here is the operation mechanism for the diamond inplane-gated FET fabricated by the oxygen plasma etching. The depletion region expands to the channel of the hydrogen-terminated diamond surface from the side wall of the oxygen-terminated diamond surface. On oxygenterminated diamond surfaces, there is pinning of the Fermi level at ;1.7 eV above the valence band edge w15x. Because of the band continuity, the band of the channel is bent under Fermi level, producing a depletion region. The fixed right-side-gate voltage causes the corresponded distance of the depletion region and reduces the channel width from right side of the channel. The
left end of the depletion region is the pinch-off point. This point can be varied as a function of the right-sidegate voltage. It is easy to change the threshold voltage. This diamond in-plane-gated FET with the channel of 3.2 mm operates as normally on because the depletion region can not cover the full width of the channel. Leftside-gate voltage modulates the channel conductance by extending the depletion region in the left-side of the channel. That device is also measured with the both side-gates functioned simultaneously. The maximum transconductance is 8 mS, almost twice of the value of former measurement with fixed right-side-gate voltage. The pinch-off is observed and the threshold voltage is 42 V. For the top-gated type devices, this simultaneously functioned dual side gates would be useful to change the threshold voltage w6x. The threshold voltage characteristics of the diamond in-plane-gated FET with the channel of 3.2 mm in width are also measured at room temperature as shown in Fig. 4. Variety of the threshold voltage characteristics corresponding to the each right-side-gate voltage is shown. The drain voltage is applied at y100 mV. The threshold voltage is changed easily with a function of the rightside-gate voltage. The gate leakage current of the diamond in-planegated FET with the channel of 3.2 mm is also measured at room temperature as shown in Fig. 5. The gate leakage current is less than 1 pA at room temperature even if the left-side-gate is at the high bias of y60 V. The oxygen plasma etching of 60 nm in depth fully
Fig. 4. IDS –VGS characteristics of the diamond in-plane-gated FET with the channel of 3.2 mm width measured at room temperature. The right side gate voltage is varied to control the pinch-off point.
T. Banno et al. / Diamond and Related Materials 12 (2003) 408–412
Fig. 5. Gate leakage current of the diamond in-plane-gated FET with the channel of 3.2 mm in width measured at room temperature. The trench of 700 nm in width and 60 nm in depth as the vacuum gate insulator separates the channel and side gates well and the gate leakage current is less than 1 pA even if the side gate is biased at y60 V at room temperature.
isolated the channel of the hydrogen-terminated diamond surface conductive layer from the two side gates. The diamond in-plane-gated FET with a relatively narrow channel of 200 nm is also fabricated by oxygen plasma etching of 60 nm in depth. Fig. 2 shows the schematic and AFM image of that diamond in-planegated FET where the gate length is 2 mm, the channel
411
width is 200 nm and the distance between the channel and the gate is 700 nm. The IDS –VDS characteristics for that diamond in-plane-gated FET measured at room temperature are shown in Fig. 6. The range of side gate voltage is smaller than wide channel version of 3.2 mm. Lateral modulation of channel conductance is obtained. The minimum sheet resistance was calculated to be 300 kVyh. When the right-side-gate voltage is 0 V, the pinch-off characteristic is observed and the threshold voltage is 9 V. The maximum transconductance of that FET is 0.2 mS. The gate leakage current is less than 1 pA at room temperature when the left-side-gate is at the bias of y10 V. This narrow diamond in-plane-gated FET operates as normally on, too. This fact suggests that the depletion region caused by the oxygen-terminated diamond surface of channel side wall extends less than 100 nm when the side gate is at the bias of 0 V. The high sheet resistance of 300 kVyh is explained by the large proportion of the depletion region width in the channel. If two tunneling barriers are added to that narrowed channel by AFM anodization process w16x to fabricate the diamond conductive island which is shrank by the adjustment of the right-side-gate voltage to increase island charging energy large enough to overcome the thermal energy at room temperature w7x, the diamond single-hole transistors could be realized and would operate at higher temperature than previous works w7,8x because the gate leakage current is very low. 4. Conclusion We have succeeded to reduce the gate leakage current of the diamond in-plane-gated FET using oxygen plasma etching which electrically full-separates hydrogen-terminated diamond surface conductive regions. Acknowledgments This work is supported by a Grant-in-Aid for Center of Excellence (COE) Research from the Ministry of Education, Culture, Sports, Science and Technology. This work is also supported in part by Advanced Research Institute for Science and Engineering, Waseda University. References
Fig. 6. IDS –VDS characteristics of the diamond in-plane-gated FET with the narrow channel of 200 nm width measured at room temperature. The right side gate voltage is fixed at 0 V.
w1x K. Matsumoto, M. Ishii, K. Segawa, Y. Oka, B.J. Vartanian, J.S. Hariss, Appl. Phys. Lett. 68 (1996) 34. w2x K. Yano, T. Ishii, T. Hashimoto, T. Kobayashi, F. Murai, K. Seki, Appl. Phys. Lett. 67 (1995) 828. w3x P.M. Campell, E.S. Snow, P.J. McMarr, Appl. Phys. Lett. 66 (1995) 1388. w4x S. Kasai, H. Hasegawa, Jpn. J. Appl. Phys. 40 (2001) 2029.
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T. Banno et al. / Diamond and Related Materials 12 (2003) 408–412
w5x R.A. Smith, H. Ahmed, J. Appl. Phys. 81 (1997) 2699. w6x T. Tsutsumi, K. Ishii, H. Hiroshima, S. Kanemaru, E. Suzuki, K. Tomizawa, Jpn. J. Appl. Phys. 41 (2002) 4419. w7x T. Banno, M. Tachiki, H. Seo, H. Umezawa, H. Kawarada, Diam. Relat. Mater. 11 (2002) 387. w8x M. Tachiki, H. Seo, T. Banno, Y. Sumikawa, H. Umezawa, H. Kawarada, Appl. Phys. Lett. 81 (2002) 2854. w9x T. Maki, S. Shikama, M. Komori, Y. Sakaguchi, K. Sakuta, T. Kobayashi, Jpn. J. Appl. Phys. 31 (1992) L1446. w10x H. Kawarada, Surf. Sci. Rep. 26 (1996) 205.
w11x K. Hayashi, S. Yamanaka, H. Watanabe, T. Sekiguchi, H. Okushi, K. Kajimura, J. Appl. Phys. 81 (1997) 744. w12x Y. Yun, T. Maki, T. Kobayashi, J. Appl. Phys. 82 (1997) 3422. w13x M. Aoki, H. Kawarada, Jpn. J. Appl. Phys. 33 (1994) 708. w14x H. Noda, A. Hokazono, H. Kawarada, Diam. Relat. Mater. 6 (1997) 865. w15x J.C. Zheng, X.N. Xie, A.T.S. Wee, K.P. Loh, Diam. Relat. Mater. 10 (2001) 500. w16x H. Seo, M. Tachiki, T. Banno, Y. Sumikawa, H. Umezawa, H. Kawarada, Jpn. J. Appl. Phys. 41 (2002) 4980.