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Stress-induced leakage current at low field in NMOS and PMOS devices with ultra-thin nitrided gate oxide
Microelectronic Engineering 72 (2004) 241–246 www.elsevier.com/locate/mee
Stress-induced leakage current at low field in NMOS and PMOS devices with ultra-thin nitrided gate oxide M. Fadlallah a
a,*
, G. Ghibaudo b, M. Bidaud c, O. Simonetti d, F. Guyader
d
LAM UFR Sciences, Moulin de la Housse, BP 1039, Reims cedex 2 51687, France b IMEP, UMR CNRS/INPG, ENSERG, BP 257, Grenoble 38016, France c Philips Semiconductors 850, rue Jean Monnet, Crolles Cedex F-38926, France d ST Microelectronics 850, rue Jean Monnet, Crolles Cedex F-38926, France
Abstract To support the International Technology Roadmap for Semiconductors, equivalent thickness of the gate dielectric will need to be 1.0–1.5 nm by 2004. Due to increased power consumption, intrinsic device reliability, and circuit instabilities associated with SiO2 of this thickness, a high-permittivity gate dielectric (e.g., Si3 N4 , HfSix Oy , ZrO2 ) with low leakage current and at least equivalent capacitance, performance, and reliability will be required. In this work, we investigate the stress-induced leakage current (SILC) at low field for both PMOS and NMOS with ultra-thin nitrided gate oxide with thickness of 1.6 nm. C–V measurements are used to extract the oxide thickness (Tox ) and the substrate doping (NP ), which must be corrected for this range of oxide thickness. The SILC generation kinetics after constant voltage stress is shown to be related to that of interface or near-interface oxide traps and to the concentration of the atoms of nitrogen near to the interface. Moreover, the situation in PMOS is just contrary to the NMOS. We attribute this to the different barrier lowering in conduction band and valence band. Ó 2004 Elsevier B.V. All rights reserved.
1. Introduction The aggressive gate leakage current due to the carrier direct tunneling has become an ultimate limit for gate oxide down scaling. Nitrided oxide has emerged as one of the most promising candidate to overcome this obstacle. Stress-induced leakage current (SILC) can be regarded as a major * Corresponding author. Tel.: +33-326-918-222; fax: +33-326913-106. E-mail address: [email protected] (M. Fadlallah).
gate dielectric reliability concern, especially for non-volatile memory application because the leakage current thorough the gate can erase the information after some time and can lead to a permanent power waste problem [3–7]. The SILC at high or medium fields has been shown to increase exponentially with the oxide scaling down to 4–4.5 nm [8–10]. However, the SILC is found to diminish significantly below this limit and even becomes negligible in accumulation or inversion for 2 nm thin oxides [11]. In this situation, the SILC at low field, i.e., in depletion and weak inversion regions is increasing due to enhanced
0167-9317/$ - see front matter Ó 2004 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2003.12.044
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direct tunneling of electron from the gate towards the substrate (or vice versa) via interfacial or nearinterfacial oxide states [11–13]. Table 1 DPN process conditions ID DPN-1 DPN-2
Gas N2 , He N2
P (Torr) 3
20 10 5 103
RF (W)
Time (s)
500 300
35 10
Therefore, in this work, we have investigated in details the SILC at low field in ultra-thin nitrided gate oxides with thickness of 1.6 nm for both PMOS and NMOS. The results obtained are shown to be related to that of interface or near-interface oxide traps and to the concentration of the nitrogen atoms near to the interface. Moreover, the situation in PMOS is just contrary to the NMOS.
2. Experimental The CMOS devices used in this study have been fabricated at STM/Crolles with a nominal gate length of 120 nm, Table 1. Wafers were first oxidized in a single wafer equipment to grow 1.4–1.6 nm pure
Fig. 2. Small-signal equivalent scheme of the MOS capacitor (a) used by the LCR meter in the parallel configuration and (b) proposed for the C–V correction.
Fig. 1. Typical transfer characteristics Id Ig ðVg Þ measured in ohmic regime (Vd ¼ 0:05 V) for NMOS and PMOS devices (DPN-1).
Fig. 3. Results of C–V measurements on NMOS devices (DPN1) for different combinations of dual-frequency correction obtained with the method of Yang et al.
M. Fadlallah et al. / Microelectronic Engineering 72 (2004) 241–246
243
quired to stabilize the nitrogen incorporation. Next, 150-nm polysilicon was deposited. Rapid thermal nitrided (RTN) oxy-nitridation was considered as our reference process (950 °C, 30 s, NO) [14]. 3. Results and discussion
Fig. 4. Ig ðVg Þ, characteristics for a large area NMOS device (Vd ¼ 0).
RTO pre-oxides. Subsequently, oxidized samples were nitrided in a separate DPN chamber. An additional high temperature oxidizing anneal was re-
Typical Id ðVg Þ transfer characteristic in ohmic regime (Vd ¼ 50 mV) on PMOS and NMOS with ultra-thin nitrided gate oxide samples with channel length down to 0.12 lm are shown in Fig. 1, demonstrating the overall good behavior of the technology in terms of short channel effect. The C–V measurements were performed with a HP4284A LCR meter and the I–V measurements with a HP4140B pA meter/DC voltage source.
Fig. 5. Evolution of Ig ðVg Þ characteristics after CVS stress for NMOS and PMOS devices (Vg ¼ þ3 V (a) and )3 V (b), DPN-1).
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M. Fadlallah et al. / Microelectronic Engineering 72 (2004) 241–246
The C–V measurements were performed in the parallel configuration of the LCR meter (Fig. 2(a)). For the MOS structures, this twoelement scheme neglects the series resistance RS that models the gate, the substrate and the interconnections potential drop in the presence of tunneling current (Fig. 2(b)). For ‘‘thick’’ oxides (Tox > 3 nm), the influence of RS is negligible and Ck well describes the MOS capacitance C. In presence of a large tunneling current, the Ck values must be corrected for to take RS into account [2]. As long as the C–V correction method allows the accumulation and inversion regimes to be obtained, the main physical parameters of the MOS structure (Tox , NS ðxÞ and NP ) are extracted by C–V characterization. Tox is obtained in strong accu-
mulation regime with an error, DTox , due to the choice of the two frequencies used for the C–V correction method. The polysilicon gate doping NP is obtained in the strong inversion regime. The substrate doping profile NS ðxÞ is obtained in the depletion regime, which is not affected by the tunneling current; the doping at the Si/SiO2 interface influences the C–V behavior near the flatband condition and the doping in the bulk influences the C–V behavior near the minimum capacitance value. In Fig. 3, we show the C–V measurements for different frequencies using the method [1,2] to extract the main physical parameters of the MOS structure (Tox , NS ðxÞ and NP ) found approximately for the different technologies RTN, DPN-1 and
Fig. 6. Evolution of normalized SILC characteristics DJg =Jg0 after CVS stress for stress for NMOS and PMOS devices (Vg ¼ þ3 V (a) and )3 V (b), DPN-1).
M. Fadlallah et al. / Microelectronic Engineering 72 (2004) 241–246
DPN-2: NS ¼ 7 1017 cm3 , NP ¼ 1 1020 cm3 and Tox ¼ 1:6 nm. Typical gate current Ig , versus gate voltage characteristics are shown in Fig. 4 for a large area MOS device (W ¼ 100 lm and L ¼ 100 lm) with ultra-thin nitrided gate oxide (DPN-1). The humps in the Ig ðVg Þ curves observed in depletion and inversion regions (Vg > 1 V) can likely be attributed to a trap-assisted tunneling process in near-interface or interfacial oxide traps [11,12]. Indeed, for Vg < 0, electrons from the polygate tunnel into interface oxide traps where they are recombined by substrate hole capture forming a bulk current. Conversely, for Vg > 0, electrons trapped in the interfacial oxide states are emitted towards the gate, leaving behind a hole which is by turn emitted to the substrate valence band. This trap-assisted leakage mechanism has been further investigated after application of constant voltage stress (CVS) of various amplitudes up to a total duration of 1000 s. To this end, the CVS stress have been periodically interrupted as a function of stress time (in log scale, 4 points/decade) in order to record successively the Ig ðVg Þ characteristics after each intermediate stressing period. Typical results showing the evolution of the Ig ðVg Þ characteristics as a function of stress time are displayed in Figs. 5 and 6 for different CVS (Vg ¼ þ3 V and Vg ¼ 3 V). As can be seen from Fig. 6, the normalized SILC characteristics DJg =Jg0 ðVg Þ clearly demonstrate that interfacial oxides traps generated after stress are responsible for both humps in depletion and inversion since the SILC behavior is continuous over the whole gate voltage range 1 V > Vg > 1 V, irrespectively of the degradation level. The SILC generation kinetics, shown in Figs. 7(a) and (b) for both P and N channel and different charge injection (tmax 1000 s, Vg ¼ 3) and for the three different technologies (RTN, DPN-1 and DPN-2), is clearly found to follow a usual power law with injected dose Qa with a 0:3, which likely corresponds to interface or near-interface oxide trap creation and seems to be proportional to the concentration of the nitrogen atoms near to the interface at least for NMOS (see Fig. 8), independently of the thickness [7,11]. It should also be noted that this generation kinetics is indepen-
245
Fig. 7. Variation of normalized SILC DJ =J0 with charge injection for (a) NMOS different technologies (Vg stress ¼ 3 V) and (b) PMOS different technologies (Vg stress ¼ 3 V).
dent of the sensing gate voltage at which the current is measured (depletion or inversion) as well as of the stressing voltage. These features are consistent with a trapassisted tunneling-recombination model in which
Fig. 8. SIMS N depth profiles for DPN and RTN films [14].
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M. Fadlallah et al. / Microelectronic Engineering 72 (2004) 241–246
the gate current is related to the pure tunnel current, It ¼ I0 rNit , and the hole capture/emission current, Ihc ¼ qNit =shc , as [10–12], Ig ¼
It Ihc ; It þ Ihc
ð1Þ
where Nit being the interface or near-interface oxide trap density, r the trap cross-section and shc the hole capture/emission time. Indeed, from this model, the SILC can be equated to, DJg DNit ¼ : Jg Nit
ð2Þ
Therefore, according to this mechanism, the tunneling-recombination current being proportional to Nit , the normalized SILC generation kinetics appears by turn directly related to that of the stress-induced interface or near-interface oxide traps. The stress voltage or stress field acceleration of the SILC generation kinetics has also been studied and is reported in Fig. 9 for DPN-1 technologies, the others are studied but not shown here. As can be seen from this figure, the normalized SILC is found to follow preferentially gate voltage acceleration. This observation suggests that the anode hole injection or hydrogen release process could be the most probable oxide trap creation mechanism [15] as in the case of high field SILC [8].
Fig. 9. Variation of normalized SILC (DJ =J0 Þ=Qainj as a function of the stress voltage Vg stress for various injected charges Qinj .
4. Summary and conclusion We have investigated the SILC at low field for both PMOS and NMOS devices with nitrided gate oxide. The SILC generation kinetics after constant voltage stress has been shown to be related to the creation of interface or near-interface oxide traps and to the concentration of the nitrogen atoms near to the interface for NMOS devices. Moreover, the field acceleration of the SILC generation has been found to follow a gate voltage Vg model, in accordance with the anode hole injection or hydrogen release process considered as the most probable mechanism for oxide trap creation. Besides the output transfer characteristic demonstrating the overall good behavior of the technology in terms of short channel effect.
References [1] K.J. Yang, C. Hu, IEEE Trans. Electron Dev. 46 (1999) 1500. [2] O. Simonetti et al., J. Appl. Phys. 92 (2002) 4449. [3] C.W. Yang et al., Solid-State-Electronics 47 (2003) 751–754. [4] P. Olivo, T.N. Nguyen, B. Ricco, IEEE Trans. Electron Dev. ED-35 (1988) 2259. [5] D.J. Dumin, J.R. Maddux, IEEE Trans. Electron Dev. ED-40 (1993) 986. [6] H. Satake, A. Toriumi, in: Proceedings of the International Conference on Solid State Devices and Materials, Yokohama, Japan, 1994, p. 562. [7] D.J. DiMaria, E. Cartier, J. Appl. Phys. 78 (1995) 3883. [8] C. Jahan, S. Bruyere, G. Ghibaudo, E. Vincent, K. Barla, Microelectron. Reliab. 39 (1999) 791. [9] G. Ghibaudo, P. Riess, S. Bruyere, B. DeSalvo, C. Jahan, A. Scarpa, G. Pananakakis, E. Vincent, Microelectron. Eng. 49 (1999) 41. [10] A. Meinerttzhagen et al., J. Appl. Phys. 91 (2002) 2123. [11] A. Ghetti, E. Sangiorgi, J. Bude, T.W. Sorsch, G. Weber, IEEE TED-47 2358 (2000). [12] R. Clerc, A. Spinelli, G. Ghibaudo, C. Leroux, G. Pananakakis, Proc. WODIM (2000) 50. [13] D. Ielmini, A.S. Spinelli, M.A. Rigamonti, A.L. Lacaita, IEEE Trans. Electron Dev. 47 (2000) 1258. [14] M. Bidaud et al., ECS Proceedings, 2003. [15] D.J. Bude, B. Weir, P. Silverman, Proc. IEEE/IEDM (1998) 179.
Stress-induced leakage current at low field in NMOS and PMOS devices with ultra-thin nitrided gate oxide M. Fadlallah a
a,*
, G. Ghibaudo b, M. Bidaud c, O. Simonetti d, F. Guyader
d
LAM UFR Sciences, Moulin de la Housse, BP 1039, Reims cedex 2 51687, France b IMEP, UMR CNRS/INPG, ENSERG, BP 257, Grenoble 38016, France c Philips Semiconductors 850, rue Jean Monnet, Crolles Cedex F-38926, France d ST Microelectronics 850, rue Jean Monnet, Crolles Cedex F-38926, France
Abstract To support the International Technology Roadmap for Semiconductors, equivalent thickness of the gate dielectric will need to be 1.0–1.5 nm by 2004. Due to increased power consumption, intrinsic device reliability, and circuit instabilities associated with SiO2 of this thickness, a high-permittivity gate dielectric (e.g., Si3 N4 , HfSix Oy , ZrO2 ) with low leakage current and at least equivalent capacitance, performance, and reliability will be required. In this work, we investigate the stress-induced leakage current (SILC) at low field for both PMOS and NMOS with ultra-thin nitrided gate oxide with thickness of 1.6 nm. C–V measurements are used to extract the oxide thickness (Tox ) and the substrate doping (NP ), which must be corrected for this range of oxide thickness. The SILC generation kinetics after constant voltage stress is shown to be related to that of interface or near-interface oxide traps and to the concentration of the atoms of nitrogen near to the interface. Moreover, the situation in PMOS is just contrary to the NMOS. We attribute this to the different barrier lowering in conduction band and valence band. Ó 2004 Elsevier B.V. All rights reserved.
1. Introduction The aggressive gate leakage current due to the carrier direct tunneling has become an ultimate limit for gate oxide down scaling. Nitrided oxide has emerged as one of the most promising candidate to overcome this obstacle. Stress-induced leakage current (SILC) can be regarded as a major * Corresponding author. Tel.: +33-326-918-222; fax: +33-326913-106. E-mail address: [email protected] (M. Fadlallah).
gate dielectric reliability concern, especially for non-volatile memory application because the leakage current thorough the gate can erase the information after some time and can lead to a permanent power waste problem [3–7]. The SILC at high or medium fields has been shown to increase exponentially with the oxide scaling down to 4–4.5 nm [8–10]. However, the SILC is found to diminish significantly below this limit and even becomes negligible in accumulation or inversion for 2 nm thin oxides [11]. In this situation, the SILC at low field, i.e., in depletion and weak inversion regions is increasing due to enhanced
0167-9317/$ - see front matter Ó 2004 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2003.12.044
242
M. Fadlallah et al. / Microelectronic Engineering 72 (2004) 241–246
direct tunneling of electron from the gate towards the substrate (or vice versa) via interfacial or nearinterfacial oxide states [11–13]. Table 1 DPN process conditions ID DPN-1 DPN-2
Gas N2 , He N2
P (Torr) 3
20 10 5 103
RF (W)
Time (s)
500 300
35 10
Therefore, in this work, we have investigated in details the SILC at low field in ultra-thin nitrided gate oxides with thickness of 1.6 nm for both PMOS and NMOS. The results obtained are shown to be related to that of interface or near-interface oxide traps and to the concentration of the nitrogen atoms near to the interface. Moreover, the situation in PMOS is just contrary to the NMOS.
2. Experimental The CMOS devices used in this study have been fabricated at STM/Crolles with a nominal gate length of 120 nm, Table 1. Wafers were first oxidized in a single wafer equipment to grow 1.4–1.6 nm pure
Fig. 2. Small-signal equivalent scheme of the MOS capacitor (a) used by the LCR meter in the parallel configuration and (b) proposed for the C–V correction.
Fig. 1. Typical transfer characteristics Id Ig ðVg Þ measured in ohmic regime (Vd ¼ 0:05 V) for NMOS and PMOS devices (DPN-1).
Fig. 3. Results of C–V measurements on NMOS devices (DPN1) for different combinations of dual-frequency correction obtained with the method of Yang et al.
M. Fadlallah et al. / Microelectronic Engineering 72 (2004) 241–246
243
quired to stabilize the nitrogen incorporation. Next, 150-nm polysilicon was deposited. Rapid thermal nitrided (RTN) oxy-nitridation was considered as our reference process (950 °C, 30 s, NO) [14]. 3. Results and discussion
Fig. 4. Ig ðVg Þ, characteristics for a large area NMOS device (Vd ¼ 0).
RTO pre-oxides. Subsequently, oxidized samples were nitrided in a separate DPN chamber. An additional high temperature oxidizing anneal was re-
Typical Id ðVg Þ transfer characteristic in ohmic regime (Vd ¼ 50 mV) on PMOS and NMOS with ultra-thin nitrided gate oxide samples with channel length down to 0.12 lm are shown in Fig. 1, demonstrating the overall good behavior of the technology in terms of short channel effect. The C–V measurements were performed with a HP4284A LCR meter and the I–V measurements with a HP4140B pA meter/DC voltage source.
Fig. 5. Evolution of Ig ðVg Þ characteristics after CVS stress for NMOS and PMOS devices (Vg ¼ þ3 V (a) and )3 V (b), DPN-1).
244
M. Fadlallah et al. / Microelectronic Engineering 72 (2004) 241–246
The C–V measurements were performed in the parallel configuration of the LCR meter (Fig. 2(a)). For the MOS structures, this twoelement scheme neglects the series resistance RS that models the gate, the substrate and the interconnections potential drop in the presence of tunneling current (Fig. 2(b)). For ‘‘thick’’ oxides (Tox > 3 nm), the influence of RS is negligible and Ck well describes the MOS capacitance C. In presence of a large tunneling current, the Ck values must be corrected for to take RS into account [2]. As long as the C–V correction method allows the accumulation and inversion regimes to be obtained, the main physical parameters of the MOS structure (Tox , NS ðxÞ and NP ) are extracted by C–V characterization. Tox is obtained in strong accu-
mulation regime with an error, DTox , due to the choice of the two frequencies used for the C–V correction method. The polysilicon gate doping NP is obtained in the strong inversion regime. The substrate doping profile NS ðxÞ is obtained in the depletion regime, which is not affected by the tunneling current; the doping at the Si/SiO2 interface influences the C–V behavior near the flatband condition and the doping in the bulk influences the C–V behavior near the minimum capacitance value. In Fig. 3, we show the C–V measurements for different frequencies using the method [1,2] to extract the main physical parameters of the MOS structure (Tox , NS ðxÞ and NP ) found approximately for the different technologies RTN, DPN-1 and
Fig. 6. Evolution of normalized SILC characteristics DJg =Jg0 after CVS stress for stress for NMOS and PMOS devices (Vg ¼ þ3 V (a) and )3 V (b), DPN-1).
M. Fadlallah et al. / Microelectronic Engineering 72 (2004) 241–246
DPN-2: NS ¼ 7 1017 cm3 , NP ¼ 1 1020 cm3 and Tox ¼ 1:6 nm. Typical gate current Ig , versus gate voltage characteristics are shown in Fig. 4 for a large area MOS device (W ¼ 100 lm and L ¼ 100 lm) with ultra-thin nitrided gate oxide (DPN-1). The humps in the Ig ðVg Þ curves observed in depletion and inversion regions (Vg > 1 V) can likely be attributed to a trap-assisted tunneling process in near-interface or interfacial oxide traps [11,12]. Indeed, for Vg < 0, electrons from the polygate tunnel into interface oxide traps where they are recombined by substrate hole capture forming a bulk current. Conversely, for Vg > 0, electrons trapped in the interfacial oxide states are emitted towards the gate, leaving behind a hole which is by turn emitted to the substrate valence band. This trap-assisted leakage mechanism has been further investigated after application of constant voltage stress (CVS) of various amplitudes up to a total duration of 1000 s. To this end, the CVS stress have been periodically interrupted as a function of stress time (in log scale, 4 points/decade) in order to record successively the Ig ðVg Þ characteristics after each intermediate stressing period. Typical results showing the evolution of the Ig ðVg Þ characteristics as a function of stress time are displayed in Figs. 5 and 6 for different CVS (Vg ¼ þ3 V and Vg ¼ 3 V). As can be seen from Fig. 6, the normalized SILC characteristics DJg =Jg0 ðVg Þ clearly demonstrate that interfacial oxides traps generated after stress are responsible for both humps in depletion and inversion since the SILC behavior is continuous over the whole gate voltage range 1 V > Vg > 1 V, irrespectively of the degradation level. The SILC generation kinetics, shown in Figs. 7(a) and (b) for both P and N channel and different charge injection (tmax 1000 s, Vg ¼ 3) and for the three different technologies (RTN, DPN-1 and DPN-2), is clearly found to follow a usual power law with injected dose Qa with a 0:3, which likely corresponds to interface or near-interface oxide trap creation and seems to be proportional to the concentration of the nitrogen atoms near to the interface at least for NMOS (see Fig. 8), independently of the thickness [7,11]. It should also be noted that this generation kinetics is indepen-
245
Fig. 7. Variation of normalized SILC DJ =J0 with charge injection for (a) NMOS different technologies (Vg stress ¼ 3 V) and (b) PMOS different technologies (Vg stress ¼ 3 V).
dent of the sensing gate voltage at which the current is measured (depletion or inversion) as well as of the stressing voltage. These features are consistent with a trapassisted tunneling-recombination model in which
Fig. 8. SIMS N depth profiles for DPN and RTN films [14].
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M. Fadlallah et al. / Microelectronic Engineering 72 (2004) 241–246
the gate current is related to the pure tunnel current, It ¼ I0 rNit , and the hole capture/emission current, Ihc ¼ qNit =shc , as [10–12], Ig ¼
It Ihc ; It þ Ihc
ð1Þ
where Nit being the interface or near-interface oxide trap density, r the trap cross-section and shc the hole capture/emission time. Indeed, from this model, the SILC can be equated to, DJg DNit ¼ : Jg Nit
ð2Þ
Therefore, according to this mechanism, the tunneling-recombination current being proportional to Nit , the normalized SILC generation kinetics appears by turn directly related to that of the stress-induced interface or near-interface oxide traps. The stress voltage or stress field acceleration of the SILC generation kinetics has also been studied and is reported in Fig. 9 for DPN-1 technologies, the others are studied but not shown here. As can be seen from this figure, the normalized SILC is found to follow preferentially gate voltage acceleration. This observation suggests that the anode hole injection or hydrogen release process could be the most probable oxide trap creation mechanism [15] as in the case of high field SILC [8].
Fig. 9. Variation of normalized SILC (DJ =J0 Þ=Qainj as a function of the stress voltage Vg stress for various injected charges Qinj .
4. Summary and conclusion We have investigated the SILC at low field for both PMOS and NMOS devices with nitrided gate oxide. The SILC generation kinetics after constant voltage stress has been shown to be related to the creation of interface or near-interface oxide traps and to the concentration of the nitrogen atoms near to the interface for NMOS devices. Moreover, the field acceleration of the SILC generation has been found to follow a gate voltage Vg model, in accordance with the anode hole injection or hydrogen release process considered as the most probable mechanism for oxide trap creation. Besides the output transfer characteristic demonstrating the overall good behavior of the technology in terms of short channel effect.
References [1] K.J. Yang, C. Hu, IEEE Trans. Electron Dev. 46 (1999) 1500. [2] O. Simonetti et al., J. Appl. Phys. 92 (2002) 4449. [3] C.W. Yang et al., Solid-State-Electronics 47 (2003) 751–754. [4] P. Olivo, T.N. Nguyen, B. Ricco, IEEE Trans. Electron Dev. ED-35 (1988) 2259. [5] D.J. Dumin, J.R. Maddux, IEEE Trans. Electron Dev. ED-40 (1993) 986. [6] H. Satake, A. Toriumi, in: Proceedings of the International Conference on Solid State Devices and Materials, Yokohama, Japan, 1994, p. 562. [7] D.J. DiMaria, E. Cartier, J. Appl. Phys. 78 (1995) 3883. [8] C. Jahan, S. Bruyere, G. Ghibaudo, E. Vincent, K. Barla, Microelectron. Reliab. 39 (1999) 791. [9] G. Ghibaudo, P. Riess, S. Bruyere, B. DeSalvo, C. Jahan, A. Scarpa, G. Pananakakis, E. Vincent, Microelectron. Eng. 49 (1999) 41. [10] A. Meinerttzhagen et al., J. Appl. Phys. 91 (2002) 2123. [11] A. Ghetti, E. Sangiorgi, J. Bude, T.W. Sorsch, G. Weber, IEEE TED-47 2358 (2000). [12] R. Clerc, A. Spinelli, G. Ghibaudo, C. Leroux, G. Pananakakis, Proc. WODIM (2000) 50. [13] D. Ielmini, A.S. Spinelli, M.A. Rigamonti, A.L. Lacaita, IEEE Trans. Electron Dev. 47 (2000) 1258. [14] M. Bidaud et al., ECS Proceedings, 2003. [15] D.J. Bude, B. Weir, P. Silverman, Proc. IEEE/IEDM (1998) 179.