Comparison of drain-induced barrier-lowering in short-channel NMOS and PMOS devices at 77 K

Solid-State Electronics Vol. 34, No. 10, pp. 1065-1070, 1991 Printed in Great Britain. All rights reserved

0038-1101/91 $3.00 + 0.00 Copyright (~ 1991 Pergamon Press pie

C O M P A R I S O N OF D R A I N - I N D U C E D B A R R I E R - L O W E R I N G IN S H O R T - C H A N N E L N M O S A N D PMOS DEVICES AT 77 K Z. X. YAN a n d M. J. DEEN School of Engineering Science, Simon Fraser University, Burnaby, British Columbia, Canada V5A 1S6 (Received 11 December 1990; in revised form 7 March 1991)

Abstract--This paper presents detailed comparisons between the room temperature and liquid nitrogen temperature experimental and 2-D simulation DIBL results in varying channel lengths NMOS and PMOS devices. The results in PMOS devices showed that DIBL is always worse at 300 than at 77 K. However, for NMOS devices, a unique DIBL temperature-dependent feature was observed, that is, DIBL is improved for devices with L < 0.6 and L > 1.2 pm, but is worse for devices in which 0.6 < L < 1.2/~m. Investigation of the physical mechanisms for explaining the above phenomenon in both types of MOS devices was carried out with the new version of the 2-D device numerical simulation program MINIMOS 4.0, that includes device modeling at cryogenic temperatures. The simulation results show that: (a) the major difference between NMOS and PMOS devices structure is the additional B-ion channel doping which tends to prevent punch-through in the sub-surface region for shorter channel NMOS devices, but forms a buried p-type sub-surface channel for shorter channel PMOS devices; and (b) lowering the temperature from 300 to 77 K caused the channel current path to be pushed back towards the channel surface for both NMOS and PMOS devices due to the freeze-out effect in the substrate. Therefore, the observed DIBL characteristics could be explained physically by the combination of the different source drain junction potential profiles between NMOS and PMOS devices, and the different current flow paths at 300 and 77 K.

I. I N T R O D U C T I O N

This p a p e r presents a detailed c o m p a r i s o n of the experimental a n d simulated drain-induced barrier lowering ( D I B L ) results in short-channel M O S devices at 300 K with those at 77 K. In the past, D I B L has been studied by m a n y researchers for b o t h N M O S or P M O S devices, at r o o m t e m p e r a t u r e a n d at low temperatures[I-7]. A detailed discussion of the threshold voltage and related D I B L variation due to the freeze-out effect at 77 K was presented in[4], with the devices m a d e using a dual-poly gate C M O S process. In[2,6,7], b o t h experimental a n d simulated results were discussed o n D I B L variation at 300 and 77 K for either N M O S or P M O S devices. However, as far as the C M O S circuits are concerned, no detailed c o m p a r i s o n in D I B L in b o t h types of devices at 300 and 77 K has been made, n o r has there been any studies on the effects of the c o n d u c t i o n path difference between these devices at either 300 or at 77K. In addition, this study is also motivated by the continued shrinking o f the channel length of M O S devices in m o d e r n VLSI C M O S circuits a n d systems, and the fact that low-temperature operation presents an attractive alternative to 300 K o p e r a t i o n for highp e r f o r m a n c e electronic circuits a n d VLSI systems[8-10]. If the C M O S system, which was designed originally for r o o m t e m p e r a t u r e operation, but is now used at a liquid nitrogen t e m p e r a t u r e of 77 K, then those i m p o r t a n t short-channel effects like

threshold voltage reduction and D I B L for b o t h N M O S and P M O S devices should also be seriously and carefully considered for the improved device design. In this paper, a detailed comparison of the structure in the test devices a n d related experimental D I B L results at 300 and 77 K, together with the corresponding simulation results, are presented in Section 2. Using the 2-D M O S device numerical simulation p r o g r a m M I N I M O S 4.0111], the source/ drain j u n c t i o n profile difference between N M O S and P M O S devices are investigated in Section 3, the channel current paths at 300 and 77 K followed by a discussion of Section 4. Detailed explanation of the different D I B L t e m p e r a t u r e - d e p e n d e n t characteristics in N M O S and P M O S devices based on the above physical mechanism are then described in Section 5. The next section briefly discusses a channel doping design of b o t h N M O S a n d P M O S devices in a C M O S technology that is considered for low-temperature operation, and the conclusions are finally presented in Section 7. 2. DEVICE STRUCTURE AND DIBL MEASUREMENT

The N M O S a n d P M O S test devices used in this study were fabricated with typical m o d e r n C M O S technology processing. The N M O S devices were fabricated on a p - t y p e substrate o f doping ~ 9 x 10~Scm -3 and had source and drain j u n c t i o n

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Z, X. YAN and M. J. DEEN

depths of ~0.22/~m. The P M O S devices were fabricated in the n-well with surface doping concentration of ~ 2 x 10 ~6cm -3 and had source and drain junction depths of ~0.20/~m. The gate oxide thickness of 250 ~ and a self-aligned n + polysilicon gate process was used. B-ion implantation in the channel with a peak doping concentration of ~ 6 x 10~6cm 3 and a projected range of ~ 0 . 0 3 # m were used for both N M O S and P M O S devices for threshold voltage adjustment. The net simulated channel doping profile along the channel depth due to this B-ion implant is shown in Fig. 1. The test devices had same fixed channel width of 24 Ftm, but varying effective channel lengths from 0.5 to 2/~m for N M O S devices, and 0.6-21/~m for P M O S devices, respectively. D I B L was monitored by the parameter R[6,7], defined in this paper as the threshold voltage shift 6Vxn (DIBL) divided by the drain voltage variation dVDs, and is: R --

6 VTH ( D I B L )

VTH ( VDS2 ) -- VTH ( VDS] )

-

6 V~s

V~s., -

V~s,

. (1)

Here, the threshold voltage VTH is defined as the gate voltage required for the fixed drain current of 10 nA. VDs~ and VDs2 were chosen as 1 and 2 V for the N M O S devices, or - 1 and - 2 V for the PMOS devices, with the only exception being the shortest channel device with L = 0.5 ILm for which Vos ~ was 0.1 V and VDs2 was 0.2 V because of strong punchthrough at higher VDs biases. All the experimental data were measured using an automated HP4145 Semiconductor Parameter Analyzer, with the PC-AT type PC as the central controller. The measurement accuracy is 0.1% for voltage and 0.3 ~ 1% for current within the measurement range, as explained above. The measured D I B L parameter R vs channel length L at 300 and 77 K for both N M O S and P M O S devices is plotted in Fig. 2. F r o m these experimental

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NMOS

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L (,am) Fig. 2. Measured and simulated results o f the D I B L parameter R vs channel length for NMOS and PMOS devices

at 300 and 77 K, respectively.

results, we note that as the temperature decreases from 300 to 77 K, DIBL as monitored by R is always improved at 77 K compared with that at 300 K for P M O S devices over the entire channel length variation. However, R shows some different and unique DIBL temperature dependence for N M O S devices: it is improved for devices with L > 1.5 and L = 0.5 #m, but is worse for devices with L = 0 . 8 and 1.1 #m. To further confirm this interesting DIBL feature, M I N I M O S 4.0 was used to simulate los vs VGs curves for both N M O S and P M O S at 300 and 77 K, respectively. The channel length of the simulated devices was varied with much smaller steps of 0.05 #m, and the simulated DIBL parameter R vs channel length L is also plotted in Fig. 2 as solid lines. The simulation results are in good agreement with the experimental results, but they reveal more details about temperalure-dependent characteristics of D I B L in both N M O S and P M O S devices, especially for N M O S devices. From the simulated results for N M O S devices in Fig. 2, we observe that the variation of R with L is divided into three regions. In region 1 (referred to as the region with longer channel length devices) and region 3 (referred to as the region with very short channel length devices), DIBL is improved at 77 K compared with that at 300 K, especially for region 3. However in region 2 (referred to as the region with shorter channel length devices), DIBL becomes worse at 77 K. The intersection points of L~ (between regions I and 2) and L 2 (between regions 2 and 3) were measured to be ~1.2 and ~ 0 . 6 # m , respectively, for our test N M O S devices. Therefore the measured DIBL difference between N M O S and PMOS devices are quite interesting and must be investigated very carefully.

I 05

(tim)

Fig. 1. The simulated results of the channel doping profile as a function of channel depth for both test NMOS and PMOS devices.

3. S O U R C E / D R A I N J U N C T I O N POTENTIAL PROFILE

As mentioned above, the source/drain junction structures significantly affect the D I B L character-

Drain-induced barrier lowering at 77 K 06 05

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-----

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;:L 0.4

~ 03 c =

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02 ChonneL

04 Length

0.6

10

(tim)

Fig. 3. Simulated 0 V potential profile of the source and drain junction for NMOS and PMOS devices with channel length of L = 0.8 pro.

istics[5]. Figure 3 shows the simulated junction potential profiles at the electrostatic potential of 0 V for 0.8 pm N M O S a n d PMOS devices, respectively. The gate voltage for both NMOS and PMOS devices were set to zero. The simulated electrostatic potential of 0 V in the figure is referenced to the middle of the substrate band gap. Examining these potential profiles, we could clearly see some very important differences between NMOS and PMOS junction potential profiles near the channel surface. First, the junction potential profile near the surface channel is towards the channel direction and reach ~0.2 pm away from the source junction edge on the channel surface for NMOS devices. However, for the PMOS devices, this junction potential profile is directed away from the channel region and reach ~ 0 . 1 4 p m from the source junction edge on the channel surface. Second, this junction potential profile around the sub-surface channel goes towards the source (and drain) region for the NMOS devices (i.e. the separation between the source and drain junction increases ~ith depth). For the PMOS devices, the junction potential profile is convexly towards the channel region with the peak position of ~ 0 . 2 2 p m away from the source (and drain) region and ~0.08pro below the surface. The physical reason for above junction potential profile difference between NMOS and PMOS devices is mainly due to the different total or compensated channel doping profile in NMOS or PMOS channel regions, as shown previously in Fig. 1. The additional B-ion channel doping is the same p-type dopant as in the substrate for NMOS devices and has a peak concentration of ~0.3 pm beneath the channel surface. The effect of this channel doping on the junction potential profile results in an increase in the channel separation between the source and drain profile while moving away from the surface, as shown in Fig. 3. On the other hand, this additional B-ion channel doping profile in PMOS devices would form a so-called p-type buried channel. Although this PMOS device with a buried channel is still operated in enhancement

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mode due to the work-function difference between the n+-poly gate and the substrate, the junction potential profile near the channel surface in this ease is significantly changed. This was shown in Fig. 3 as a convex shape towards the channel, which corresponds to the compensated channel doping profile. Therefore the minimum potential barrier height between the source and channel would be located not at the surface, but at the sub-surface of a depth of ~ 0 . 0 8 # m for the PMOS devices. This significant difference of the junction potential profile between NMOS and PMOS devices is very important for the evaluation of the effective channel length and its related DIBL behavior at 300 and 77 K, as will be seen in the following section.

4. C H A N N E L

CURRENT

PATH

Figure 4 shows the simulated lateral current density along the channel depth at 300 and 77 K for both n- and p-channel of L = 0.8/~m as an example. The drain current in the devices was fixed by 10 -s A by adjusting the gate voltage, and the drain voltage is set to 1V for the NMOS and - 1 V for the PMOS devices. The simulation results clearly show that the channel current path for NMOS devices is much closer to the surface channel, compared mostly with the sub-surface channel for PMOS devices. This is consistent with the channel doping profile and junction potential profile. Figure 4 also shows that as the temperature decreases from 300 and 77 K, the drain current profiles are pushed back to the channel surface for both NMOS and PMOS devices. Careful examination of this figure reveal that the lateral current density profile for the NMOS devices is always spreading outwards, and is monotonously decreasing from the surface down towards the substrate, but has a convex-type shape with the peak 102

A

100

L=OS/~m 300 K 77K

"~"

10 - 2

10 - 4

a~ -J

10-e 10-10 0.0

0.1 ChonneL

02 depth

0.3

(/~rn)

Fig. 4. Simulated results of the lateral electron current density vs channel depth for NMOS and PMOS devices of L = 0.8 #m, W = 24 #m, with Vos = l V (NMOS) or - I V (PMOS) at T = 300 and 77 K, respectively. Vos was adjusted to fix the value of IDS at ~ l0 -s A.

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Z . X . YAN a n d

position below the channel surface for the PMOS devices. The reason for this shifting towards the channel surface of the lateral current density with lowering temperature from 300 to 77 K is essentially due to the freeze-out effect at 77 K in the substrate and has been discussed in the previous paper[7] for P M O S devices. Here, we just briefly comment on the comparison for both N M O S and P M O S devices based on detailed simulation results of electrostatic potential and transversal field as shown in Figs 5 and 6. 1. The potential barrier height: as temperature decreases from 300 and 77 K, the potential barrier height would increase from ~ 0 . 6 to 1.l V for N M O S devices, and also from ~0.55 to ~ I . 0 5 V for P M O S devices. This increase is clearly due to the freeze-out effect in the substrate as described in[7], and should be valid for both N M O S and P M O S devices. 2. The transversal field: for N M O S devices, the higher positive transveral field near the surface channel at 7 7 K (about 2 x 1 0 V c m ~ higher than its 300 K value) is due to the above higher potential variation, and would attract more mobile electrons towards the channel surface. Meanwhile, the corresponding but more negative transversal field near the channel surface for PMOS devices at 77 K (also ~ 2 x 1 0 V c m ~ lower than its 300K value) would attract more mobile holes towards the channel surface. Therefore the freeze-out effect which takes place primarily in the substrate at 77 K would result in a shifting of the channel current in both N M O S or P M O S devices to paths that are closer to the channel surface as shown in Fig. 4. In other words, the devices tend to be more like surface channel devices at the lower temperature. 150

]06 NMOS L=08# m

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oz

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f

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Fig. 5. Simulated results of the potential profile and transversal field vs channel depth for the NMOS devices of L = 0.8 l~m with VDS= 1 V at T = 300 and 77 K, respectively. VGS was adjusted to fix the value of lDs at ~ 10 -8 A.

M . J . DEEN

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Fig. 6. Simulated results of the potential profile and transversal field vs channel depth for the PMOS devices of L = 0 . 8 # m with VDS= --1V at T = 3 0 0 and 77K, respectively. VGs was adjusted to fix the value of IDS at ~IO-SA.

5. D E T A I L E D

EXPLANATION

Based on the above arguments, we can now explain in detail the temperature-dependent behavior of D I B L at 300 and 77 K in both N M O S and P M O S devices as follows: 1. For the P M O S devices, D I B L is improved at 77 K compared with 300 K for the whole channel length region of 0.5 to 2 #m. This was discussed in detail in[4] and the improved D I B L at 77 K compared to 300 K is due to the buried channel feature and freeze-out effect: the source/drain junction profile with a convex shape (looking from the channel direction) and the channel current path shifting towards the channel surface. 2. However, DIBL in the N M O S devices is only improved in longer channel length (L > 1.2#m) or very shorter channel length (L < 0.6 lira) devices, but is worse for shorter channel length (0.6 < L < 1.2/~m) devices at 77 than at 300 K. These quite interesting results could also be explained with the reasons described above: (a) the region with 0.6 < L < 1.2/~m is the most interesting one for the N M O S devices. By checking at the source/drain junction profile in Fig. 3 very carefully, the effective channel length increases from the surface channel towards the sub-surface channel. This is exactly the opposite trend near the channel surface that is observed in P M O S devices. Compared to 300 K operation, the channel current path at 77 K in N M O S devices is shifted back towards the surface, and thus D I B L at 77 K would be degraded because of the resulting decrease in the effective channel length. Thus, this unique temperature-related D I B L effect for N M O S devices is actually due to the additional B-ion channel doping, which results in different channel lengths;

Drain-induced barrier lowering at 77 K (b) the region with L > 1.2/zm is mainly referred to as the longer channel length region. Since the DIBL parameter R is very small, it is not very important and could be neglected. However, the experimental and simulated results still show that the DIBL parameter R in this region is slightly improved at 77 K. Because the DIBL in this longer channel region is referred to the surface DIBL at both 300 and 77 K, the effective electrical channel length along the surface at 77 K would be slightly longer than that at 300 K due to a freeze-out effect in the substrate, as already discussed in[13,14]. This effect on DIBL in the longer channel length region is dominant and results in a slight improvement in the DIBL parameter R at 77 K compared to 300 K; (c) in the region with L < 0 . 6 # m , it is easy to understand why DIBL at 300 K is worse than 77 K. Because of bulk punch-through, the channel current would move deeper away from the surface at 300 K. On the other hand, the corresponding channel current path at 77 K would be still quite close to the surface or sub-surface channel, compared with the bulk punch-through current path at 300 K. This is why DIBL for very short channel length NMOS devices is significantly improved at the lower temperature.

6. D I S C U S S I O N S

Since the channel B-ion implantation profile is one of the most important design factors for short-channel NMOS and PMOS devices, then for short-channel CMOS technology (for example ~ 1/am or less) designed for low-temperature operation, we make the following comments based on our experimental and simulated results. I. First, DIBL for PMOS devices is definitely better at 77 than at 300 K, but is worse for its NMOS device partner. Measurements of the DIBL parameter R for our test devices results in a 10 ~ 40% increase for NMOS devices of L = 0.8-1.0/zm and a 10 ~ 30% decrease for PMOS devices with the same channel length variation. Therefore, to improve DIBL in NMOS devices for low-temperature operation, one could suggest designing a channel doping profile with a higher peak concentration Npeak at the surface, in order to reduce the surface DIBL effect, and a smaller projected range a, in order to keep the same implantation dosage. On the other hand, this doping profile might result in just a small improvement in DIBL in the PMOS devices. The improved DIBL in PMOS devices occurs because the whole channel doping profile is now shifted closer to the surface, so it would transform the original sub-surface buried channel PMOS device to an almost surface channel PMOS device.

1069

2. Second, an even more serious problem regarding this channel doping profile design at 77 K is the threshold voltage variation for both NMOS and PMOS devices from 300 and 77 K. Experimental results of the threshold voltage VrH were increased by ~0.3 V in NMOS devices, and by ~0.42 V in PMOS devices (absolute value) as the temperature decreased from 300 and 77 K. Therefore, to make the CMOS circuits and systems operate better at 77 K, the absolute values of the threshold voltage at 300 K for both NMOS and PMOS devices should be reduced correspondingly. However, by changing the B-ion channel doping profile in NMOS and PMOS devices, the following effects on the threshold voltages are produced: (a) a decrease in the total dosage of the B-ion channel doping while keeping the same projected range would result in a decrease in VrH for the NMOS device, but would increase VTH (absolute value) for its PMOS device partner; (b) an increase in the projected range of the B-ion channel doping while keeping the same dosage would result in a decrease in VTH for the NMOS device, and an increase in absolute value of VT. for its PMOS device partner. Based on the above arguments, it is not easy to optimally design a unified B-ion channel doping profile to meet the above requirements of reducing both VTH values simultaneously in the NMOS and PMOS devices for low-temperature operation. For example, the simulation results show that in order to keep the same threshold voltage at 77 and 300 K, the total dosage of the B-ion channel implant should be decreased by ~60% for NMOS devices and increased by ~ 50% for PMOS devices. Therefore this requirement of the same Vvr~values in both devices at 77 K is a serious problem compared with DIBL described in this paper. This means that the optimal design for CMOS circuits operated at 77 K might use some different technology like dual-poly gate technology[4], twin-well technology[15] or different channel-dopants technology[16]. Actually all these technologies have been used for sub-micrometer CMOS technology at room temperature. So we do believe it it important and appropriate to use these new technologies for sub-micrometer CMOS circuits operating at 77 K. 7. C O N C L U S I O N S

The experimental and simulation results on DIBL vs channel length effect at 300 and 77 K for shortchannel NMOS and PMOS devices in CMOS technology show some very interesting characteristics: it is always improved for PMOS devices over the whole range of channel length variation; but it is only improved for the channel length range of L < 0.6 and L < 1.2/tm, and becomes worse for the devices with 0.6< L < 1.2/~m.

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Z.X. YAN and M. J. DEEN

M I N I M O S 4.0 device simulation results show that the physicl reason for the above interesting feature is due to a different source/drain j u n c t i o n potential profile, owing to the existence o f a n additional B-ion channel doping process for b o t h N M O S a n d P M O S devices. It is also due to the channel current path shifting towards the surface, owing to the freeze-out effects in the substrate as the t e m p e r a t u r e is lowered from 300 and 77 K. C o m p a r e d with the significant variation of the threshold voltage from 300 and 77 K, the corresponding D I B L variations are not serious, especially for the P M O S device. Therefore it is difficult to design optimally for b o t h short-channel N M O S and P M O S devices in C M O S technology operated at 77 K by using only one channel doping process, as it is for r o o m t e m p e r a t u r e design. Some new technologies, like dual-poly gate technology, twin-well technology or different channel d o p a n t s technology etc. must be chosen, based on b o t h VvH and D I B L considerations.

Acknowledgements--It is a pleasure to acknowledge the

assistance from J. llowski and R. Hadaway of Northern Telecom Electronics Limited, Ottawa, Ontario. This research was partially supported by grants from the Center for Systems Science, SFU, Northern Telecom Electronics Ltd and the Natural Sciences and Engineering Research Council (NSERC) of Canada. We are also thankful to the reviewers for their constructive comments.

REFERENCES

1. R. R. Troutman, 1EEE Trans. Electron Devices ED-26, 461 (1979). 2. J. C. S. Woo and J. D. Plummer, 1EEE Trans. Electron Devices ED-33, 1012 (1986). 3. S. G. Chamberlain and S. Ramanan, IEEE Trans. Electron Devices ED-33, 1745 (1986). 4. J. Y-C. Sun, Y. Taur, R. H. Dennard and S. P. Klepner, 1EEE Trans. Electron Devices ED-34, 19 (1987). 5. K. M. Cham, S. Y. Oh, D. Chin, J. L. Moll, K. Lee and P. V. Voorde, Computer-Aided Design and V L S I Development, Second Edn. Kluwer Academic Boston (1988). 6. M. J. Deen and Z. X. Yan, IEEE Trans. Eh, ctron Devices ED-37, 1707 (1990). 7. Z. X. Yah and M. J. Deen, Solid-St. Electron. 33, 1265 (1990). 8. M. J. Deen, Microprocess. Microsyst. 13, 245 (1989). 9. I. Kato, H. Oka, S. Hijiya, and T. Nakamura, I E D M Tech. Dig. 601 (1984). 10. M. J. Deen, Solid-St. Electron. 31, 291 (1988). 11. S. Selberherr, IEEE Trans. Electron Devices ED-36, 1464 (1989). 12. R. C. Jaeger, and F. H. Gaensslen, 1EEE Trans. Electron Devices ED-27, 914 (1980). 13. A. Kamgar, IEEE Trans. Electron Devices ED-29, 1226 (1982). 14. M. J. Deen, Low Temperature Engineering and Cryogenics (LTEC) Conf. 90, Southampton, U.K. (1990). 15. R. A. Chapman, C. C. Wei, D. A. Bell, S. Aur, G. A. Brown and R. A. Haken. 1EDM Tech. Digest, p. 52 (1988). 16. B. Davari, W. H. Chang, M. R. Wordeman, C. S. Oh, Y. Taur, K. E. Petrillo, D. Moy, J. J. Bucchignano, H. Y. Ng, M. G. Rosenfield, F. J. Hohn and M. D. Rodriguez, I E D M Teeh. Digest, p. 56 (1988).