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The dependence of drain-induced barrier lowering on substrate biasing in short channel PMOS devices at 77 K
Solid-State Electronics Vol. 33, No. 10, pp. 1265-1273,1990 Printed in Great Britain. All rights reserved
0038-I101/90 $3.00+ 0.00 Copyright 0 1990Pergamon Press plc
THE DEPENDENCE OF DRAIN-INDUCED BARRIER LOWERING ON SUBSTRATE BIASING IN SHORT CHANNEL PMOS DEVICES AT 77K Z. X. YAN and M. J. DEEN School of Engineering Science, Simon Fraser University, Bumaby, British Columbia, Canada V5A lS6 (Received 7 November 1989; in revised form 9 April 1990) Abstract-This paper presents detailed experimental results on the substrate biasing characteristics of drain-induced barrier lowering DIBL at 77 K in short channel PMOS devices with boron ion channel doping. It was found that as the channel length decreased, the threshold voltage shift caused by DIBL first increased with increasing substrate bias, and thereafter began decreasing. The new version of the two-dimensional device numerical simulation program MINIMOS 4.0, that includes device modeling at cryogenic temperatures, was used to investigate this unique feature of DIBL vs substrate biasing. From the simulation results, the dependence of DIBL on substrate biasing could be explained as the transition of the surface DIBL effect to the subsurface DIBL effect and the onset of the punchthrough effect. Based on the experimental results, a new empirical model for describing this substrate bias-dependent characteristics of DIBL: R = 6 VTH(DIBL)/S V,, = aL -8, a = a,, + a, VW, j = & + j?, VBs has been developed, and using this model, quantitative comparisons between 77 and 300 K results were made. These comparisons clearly show the improvement of DIBL at 77 K, especially for shorter channel devices. The experimental results could be explained physically by the transition of the subsurface current flow towards the surface current flow due to higher surface potential bending at 77 K. Further analysis were carried out with the emphasis on the variation of the threshold voltage definition and the boron ion channel doping profile. It was found that the extracted parameters a and B were very sensitive to the channel implant dose and energy, but were only slightly related to the threshold voltage definition.
1. INTRODUCHON The low-temperature operation of CMOS circuits and systems is being seriously considered as an attractive alternative to room temperature operation for high performance electronic circuits and VLSI systems[l+. This is mainly due to their very low
power dissipation, higher switching speeds, steeper subthreshold slopes, improved reliability, lower leakage currents and a drastic reduction in thermally activated degradation mechanisms at low temperatures, compared with the room temperature operation of the CMOS devices and systems[l-91. Since the channel length of CMOS devices now extends to submicrometer values, the associated important short channel effects such as threshold voltage shift and drain-induced barrier lowering (DIBL) have to be carefully considered for proper device operation with long lifetimes. DIBL has previously been studied by many researchers, but most of them dealt with this effect in NMOS devices, either at room temperature or at low temperatures[8-141. On the other hand, PMOS devices with N+ polysilicon gate, (as in typical modern CMOS devices), have an additional boron ion implant in the channel that results in a buried channel PMOS device structure. It is expected that, due to this partially compensated channel doping profile and possibly freeze-out effect in this region at cryogenic temperatures[ 15-l 71,
that DIBL for this buried-channel PMOS device at 77 K, will exhibit a more complicated behavior as the channel length and substrate bias are varied. To date, there has been no publication discussing this important short-channel effect in boron channel doped PMOS devices at low temperatures. Reference [8] first reported the measured and simulated DIBL in PMOS devices at 77 K; however it was limited to devices with a constant channel length, and no effects due to substrate biasing were given. References [lo] and [14] presented detailed studies on DIBL by 2-D simulation, including the substrate bias characteristics, but only for NMOS devices at room temperature. Reference [18] also used 2-D simulations to investigate the DIBL dependence of buried channel PMOS devices on the gate oxide thickness, channel doping junction depth and source/drain junction depths, but only for devices of a fixed channel length operating at room temperature. In this paper, we shall first present experimental results of DIBL at 77 K for short channel PMOS devices, and shall then investigate the observed substrate-bias dependent characteristics using a twodimensional device numerical simulation program MINIMOS 4.0 which is suitable for low temperature simulations[l6]. Section 4 presents a detailed comparison of these substrate bias DIBL effects between 300 K and 77 K using our new empirical model[l9],
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Z. X. YAN and M. J. DEEN
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a liquid nitrogen Dewar. These measurements were ‘made with an automated HP4145 semiconductor parameter analyzer, with an IBM PC-AT type personal computer as the central controller. The measurement accuracy was 0.1% for voltages and 0.3-1.0% for currents within the measurement range. Figures 1 and 2 show some of these measured curves for the test PMOS devices with L = 0.9 and 0.6 pm respectively. In this paper, the parameter R was used to quantify DIBL, and it was calculated as the change in the threshold voltage sI’r,(DIBL) divided by the change in the drain voltage SV,, . Here, the threshold voltage Vr, is defined as the gate voltage Vos at which the drain current I,,, is 1 nA, as shown in Figs 1 and 2. Thus R can be expressed as
and the temperature dependence of those extracted DIBL-related parameters are explained from the device physics point of view. Additional evaluations of the substrate bias related DIBL effect with an emphasis on the variation of the threshold voltage definition and the boron ion channel doping profile at 77 K, are discussed in Section 5. The conclusions are then presented in Section 6. 2. EXPERIMENTAL DETAILS
The PMOS test devices used in this study were designed and fabricated by modern VLSI CMOS technology. The doping concentration of the N-well substrate was -2 x 1Or6cm-3. The gate oxide thickness was 250 8, and a self-aligned N+ polysilicon gate process was used. The source and drain regions were formed by boron ion implantation with their junction depths being -0.2 pm. The geometry of these test devices had effective channel lengths ranging from 0.6 to 2.4 pm, and a fixed channel width of 24 pm. These PMOS devices had an additional boron ion implantation in the channel, which was implemented simultaneously for both NMOS and PMOS devices in order to match the devices threshold voltages, as typically required for CMOS technology. This was also one of the critical steps in fabricating the devices due to the requirements for precisely controlling the threshold voltage, and for preventing the PMOS devices from turning into depletion mode transistors. The drain current vs gate voltage measurements with different drain voltage biases of - 1 to - 5 V and different substrate voltage biases of O-4 V at 77 K were made by inserting these test PMOS devices into
R = _W,(DIBL) 6 vus =--
VTH ( vDS2 ) vvDS2 -
IIDS=,“* VTH ( vDSl ) DSI
.
In eqn (l), VDsl and VDsz are chosen as -1 and -5 V respectively for all the test PMOS devices. In this paper, we defined the threshold voltage as the gate voltage at which the drain current is 1 nA. This definition of V,, was used, because for submicron devices, it results in a larger change in the gate voltage with increasing drain bias, when compared with different VT, definitions at higher drain currents such as 10 or lOOnA[20]. Also, at the lower drain current, it is quite easy to observe whether the device is operating in its punchthrough mode or not. To complete the comparison, we present later the effects
10-5 IO+ IO"
3 - 8
IOIO-' IO” 10-O 1 o-‘0 1 o-”
0.00
0.40
(1)
0.80
V GS
1.20
1.60
2.00
lv)
Fig. 1. Experimental curves of the drain current vs gate voltage at 77 K for the test PMOS device of L = 0.9 pm, W = 24 pm, with V,,, varying from - 1 to - 5 V and at the fixed value of V,, = 0 and 4 V.
Drain-induced barrier lower in PMOS devices
V GS
1267
(v)
Fig. 2. Experimental curves of the drain current vs gate voltage at 77 K for the test PMOS device of L = 0.6 pm, W = 24 pm, with V,, varying from - 1 to - 5 V and at the fixed value of Vss = 0 and 4 V.
of choosing larger drain currents of 10 and 100 nA on the DIBL parameter R. 3.
MEASUREMENT
RESULTS
In order to quantitatively illustrate the measured substrate biasing characteristics of DIBL, the new empirical DIBL model developed in Ref. [19] is used here. It is R = ~Vr,(DIBL)/GVo,
= --c( I+.
(2)
Based on experimentally extracted values of doand fi, a linear dependence on V,, is suggested, that is, GI=a,+cc,.
V,,
(3)
B =B0+81.
VW.
(4)
The parameter L,,, discussed below, is defined as
From these figures, we can make the following interesting observations: (1) the extracted curve-fitting parameters of CI and /l in eqn (2) are really not constant with respect to V,, as implied in the previous models of Refs [12,14], but rather could be described more accurately by our new model using eqns (3) and (4); (2) the DIBL variation with the substrate bias in Fig. 3 is divided into two sections by the channel length L,,,, roughly corresponding to the intersection region of R vs L curves for different Vss values. In the region L > LINT, the threshold voltage shift 6Vr,(DIBL) increases as the sub250
+
200
+
150
WI. (VW - vrd-
’
1
(5)
The experimental curves of the DIBL parameter R vs channel length L with different substrate voltage biases V,, at 77 K are shown in Fig. 3. The R values measured were based on eqn (1). The solid lines in this figure are the curve fitting results using the power relationship between R and L in eqn (2). The extracted values of c( and /I vs Ves are plotted in Fig. 4 and similar results were also obtained from our test PMOS devices at room temperature[l9].
0”
dr
1”
0
2v
+
Jv
.
4”
100
50
0 0.50
1.00
1.50
2.00
2.50
L (micron) Fig. 3. The measured results of the DIBL parameter R vs effective channel length for the test PMOS devices at 77 K. The different curves are for V,, varying from 0 to 4V.
Z. X.
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YAN
and M. J.
DEEN
40.0
30.0
tl
Q_ 20.0
10.0 0.0 -2.00 0.0 1.0
2.0
3.0
4.0
v, (VI
Channel
Depth
(micron)
Fig. 4. The measured results of the u and the fi vs Vss for the test PMOS devices at 77 K. a and p are obtained from the empirical model described in eqns (2H4) in text.
strate voltage VBs is increased, but the opposite variation occurs in the region L < L,,, . The value of J&r in the case of our test devices is between 0.684.74pm from the measurements shown in Fig. 3, and 0.72pm from the calculation using eqn (5) with Vssl = 0 V and Vss2= 4 V. The cause for DIBL in short channel MOS devices is the significant field penetration from drain to source, due to the closeness of their junction depletion regions[8,12,14]. In the case of the enhancement mode NMOS devices, this DIBL and the related increased electron injection occurs at the channel surface and is usually referred to as surface DIBL[8,12]. For our test PMOS devices, although they are still designed and operated in enhancement mode as required for CMOS technology, a lightly doped P-type buried channel between the source and drain regions under the gate was formed, and the carrier freeze-out effect at cryogenic temperature might also take place with this partially compensated channel doping device structure[ 15,161. In order to explain the above measured DIBL characteristic, the two-dimensional device numerical simulation program MINIMOS 4.0 was used throughout this paper to get those basic and important physical quantities, such as the electrostatic potential distribution, the lateral hole current density distribution, and the subthreshold current under various biasing conditions at 77 K. Figures 5(a) and (b) show the simulated electrostatic potential distribution and the lateral hole current density perpendicular to the channel length direction at the point of the minimum surface potential for the devices with L = 0.6, 0.7 and 0.9 pm, and at Vss = 0 and 4 V respectively. The gate voltage was adjusted to obtain a drain current of = 1 nA at a drain voltage Vn, = - 1 V. From Fig. 5, it is easy to observe that as the channel length is reduced from 0.9 to 0.6 pm (passing through the LINTregion shown previously in Fig. 3), that the current flow path
u /..’
1.10
0.10 -0.90
;
1; (j
/4’
Ii /..’ :
IO-
v,=4v
4
k
v,=-
----
lo-’ L=oswn ,o* 1v
L-o.7m L4.W
IO_
c
0.00
0.20
Channel
0.40
Depth
IO_‘0
0.60
0.80
(micron)
@I
Fig. 5. The simulated results of the electrostatic potential distribution and lateral hole current density vs channel depth at 77 K for the PMOS device of L = 0.9 pm with VDs = - 1 V at (a) V,, = 0 V; and (b) V,, = 4 V, respect-
ively. VGs was adjusted to fix the value of I,, = 1nA. changes gradually from the surface channel towards the subsurface channel in the case of Ves = 0 V, but it still remains along the surface channel for Ves = 4V. From the substrate bias-related DIBL dependence shown in Fig. 3, we conclude that this DIBL is the surface DIBL phenomenon for the whole range of Vss variation for the devices with L > LINT, whereas it gradually changes from a subsurface DIBL to a surface DIBL with increasing substrate biases for the devices with L < LLNT. Given the surface DIBL feature for devices with L > &NT, the surface potential distribution along the channel surface direction with Va, = 0 and 4 V was computed by MINIMOS 4.0 for the device of L = 0.9 pm. The gate voltage for V,,, = - 5 V was chosen to be the same as that for ‘Vns= - 1 V and the simulated results of the surface potential distribution are plotted in Fig. 6. As shown in this figure, we see that as the substrate voltage bias increases from 0 to 4V, the transition width of the potential barrier
Drain-induced barrier lower in PMOS devices -6.00
2 3 .-
e
,
I
L=O.9m - 5.00
f-
I ----v,=ov v_+v
- 4.00
0.00
fl I
t. 0.00
0.30
Distance
0.60
Based on the above discussions, the channel length L INT, corresponding to the average intersection points of the R vs L curves in Fig. 4 actually
v,=-5v
I
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represents the transition from the surface DIBL for Ves = OV. By examining the experimental drain current curves for the L = 0.6 pm device in Fig. 2, the subthreshold slope [defined as log(Zn,/V,,)] decreased slightly with increasing Vn, at I’,, = 0 V, compared with almost parallel curves for the L = 0.9 pm device shown in Fig. 1. This indicates that the punchthrough effect is indeed observed experimentally and confirmed by simulations for the devices of channel lengths L < L,,,.
0.90
(micron)
Fig. 6. The simulated results of the surface potential vs channel length at 77 K for the PMOS device of L = 0.9 Nrn with Vi,,=--1 or -5V and Va,=OV or Pas= -4V, reswctivelv. V,. was chosen to lx -0.995 V for V,,, = 0 and - 1.472 V ?or ya, = 4 V at V,, = - 1 V (in order”;0 fix the I,, 1 1 nA). At V,,, = -5 V, the same values of V,, were used for V,, = 0 and 4 V. variation between the source (or drain) and the channel becomes wider due to the increase of the barrier height, in agreement with that reported in Ref. [14]. This increased barrier height at the higher substrate bias would increase the field penetration from the drain to the source, causing a reduction in the effective channel length that results in an increase in DIBL, when compared to the case at zero substrate voltage bias. This increase in the barrier height at the
higher substrate biases is the reason for the increased DIBL for devices with L > L,,,. For example, from Fig. 6, the minimum surface potential difference at I’,,= -1 and -5V is 42mV for V,,=OV, but is 68 mV for Pa, =4V, which further confirms our measurement results. On the other hand, for the device with L = 0.6 pm which is less than L,,,, the current flow paths at varying VBsbiases are quite different, as shown in Fig. 5. The minimum potential is now located at -0.06 pm below the surface with V,, = 0 V, so most of the hole current is now flowing through this subsurface channel. The device is actually operating in the punchthrough mode, which is more severe due to the existence of the P-type buried channel as previously discussed in Refs [ 1l-l 31. However, as the substrate bias voltage increases to 4 V, the depletion layer width between the surface and the substrate widens to about 0.7 pm as shown in Fig. 5(b), which is wider than the depletion layer width (0.4pm) for Pas = 0 V, as shown in Fig. 5(a). Also the transverse electric field near the surface increases at the higher substrate bias of 4 V, and this causes a shift in the minimum potential point back to the surface. Therefore, the gate voltage now has more control on the drain current at Ves = 4 V, compared with that of the subsurface current flow at Pas = 0 V, resulting in less DIBL at the higher V,, bias.
4. TEMPERATURE
COMPARISONS
The comparison of the measured drain-current vs gate-voltage curves and the corresponding substratebias DIBL dependences for the test PMOS devices at 77 and 300 K are shown in Figs 7 and 8. From these two figures, we see that DIBL is improved at 77 K, within the measured ranges of V,, = O-4 V, and of L = 0.62.4 pm, especially for shorter channel devices of L < 1.2 Zirn. In order to compare these characteristics quantitatively, the new empirical DIBL model described by eqns (2)-(5) was used, and all the DIBL parameters that we‘re extracted from the measured substrate bias DIBL dependent curves based on the VTH definition of 1 nA are listed in Table 1. The detailed comparison are as follows:
The extracted values of the DIBL parameters CI,,and a, based on eqn (3) are 2.82 x lo-* and 2.39 x 10e3 V-i for 77 K, and 3.65 x lo-* and 1.24 x lo-’ V-’ for 300 K respectively. The physical meaning of a could be expressed as the threshold voltage shift due to a change in the drain bias SV,, of 1 V for a device of unit channel length (1 .Opm). Therefore as the temperature decreases from 300 to 77 K, DIBL is improved by -35% for the case of Vss = 0 V, and by -9% for V,, = 4 V. (2) B The extracted values of the DIBL parameters /I0 and /I, based on eqn (4) are 3.35 and -0.219 V-’ at 77 K, and 3.55 and -0.243 V-’ at 300 K, respectively. The physical meaning of /l is the curvature of the R vs L curves, which is much more dependent on the characteristics of the submicron devices as seen from eqn (2). Therefore the -6% and -4% decrease of B at Vss = 0 V and Ves = 4 V respectively on decreasing the temperature from 300 to 77 K also means that there is less DIBL for submicron devices operated at 77 K. (3) L,N, From Fig. 7, the DIBL parameter L,,, was measured as 0.71 pm at 77 K and 0.88 pm at 300 K
Z. X. YAN and
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M. J. DEEN
lo-’ 10+ IO” IO_ IO-’ 10d IO4 1 o-‘0
IO-” -0.20
0.20
0.00
0.40
V GS
0.80
1.20
1.20
1.60
(V)
(4
0.00
0.40
0.80,
0.80
V GS (b)
lv)
Fig. 7. Experimental curves of the drain current vs gate voltage at 300 and 77 K for the test PMOS device
of L = 0.9 pm, W = 24 pm, with V,, = - 1 a;d :i,“, BS with Vss, = 0 V and VBs2= 4 V. The smaller value of G,, at 77 K compared to 300 K indicates that the punchthrough effect would take place at shorter lengths in buried channel PMOS devices. The calculated values of I,,,, based on eqn (8) are 0.72 /*rn for
at the fixed value of (a) V,, = OV; and (b)
77 K and 0.88 pm for 300 K respectively[l9], in good agreement with the measured values. The reason for this improvement of the substrate bias DIBL dependence at 77 K could be explained physically by partial impurity ionization in the sub-
Drain-induced barrier lower in PMOS devices
300
+ OV
300K
b
4v
3oOK
l
OV
77K
.
4V
77K
1271
200
1.oo
0.50
I .50
2.00
2.50
0.00
L (micron) Fig. 8. The measured results of the DIBL parameter R vs effective channel length for the test PMOS devices with a fixed substrate biases of V,, = 0 and 4 V, at temperatures of 77 and 300K. strate of the PMOS device. Usually, the impurity doping concentration in the substrate is assumed to be fully ionized at room temperature, but not at low temperatures. It is well known that the variation in the impurity ionization concentrations with temperature[l6] are described by the following equations
ND
N,+=
NA
Ni =
(6)
(7)
where ED and EA are the ionization energies of the respective donor and acceptor dopants, and Ef, and Elp are the quasi-Fermi levels of the electrons and holes respectively. Therefore, the effective doping concentration (Ng - NA) in PMOS devices might be significantly decreased at 77 K. This freeze-out effect was also experimentally observed for our test buried-channel PMOS devices, as shown previously in Fig. 2. However, for the subthreshold conduction and the related DIBL effect at 77 K, freeze-out effects in the channel are not important, as previously described in Refs [l&16] and also confirmed by our simulation results. On the other hand, this freeze-out effect in the bulk of the PMOS devices at 77 K would cause some effect on DIBL, as explained shortly. Figure 9 shows the simulation results of the electrostatic potential profile and the lateral hole current density normal to the channel length direction for L = 0.9 pm PMOS device at 300 and 77 K. These
0.10
0.20
Channel
0.30
Depth
0.40
0.50
(micron)
Fig. 9. The simulated results of the surface potential bending profile and the lateral hole current density normal to the channel direction, for the PMOS device of L = 0.9 pm with the fixed biases of Vss = 0 V and V,, = - 1 V and at 77 and 300 K.
simulated results were obtained by adjusting the gate voltage until a drain current of _ 1 nA was obtained. From Fig. 9, as the temperature decreased from 300 to 77 K, the surface potential bending normal to the channel length direction needed for the subthreshold conduction at 1,, = 1 nA is increased from 0.48 to 1.04 V. This increase in the surface potential bending is due to the freeze-out effect in the substrate, as expected from eqns (6) and (7), and also pointed out in Ref. [7]. As before, the minimum potential point is located about 0.04 pm below the surface at 300 K, but is almost at the surface at 77 K. This is quite similar to the case of increasing substrate bias at a fixed temperature as discussed above, and could be explained by the higher surface potential bending at the lower temperature of 77 K. Therefore the hole current flow path would shift back from the subsurface channel at 300 K to the surface channel at 77 K, and this results in the improvement of the DIBL effect and a decrease of the corresponding parameters a, fi and L,,,. 5.
DISCUSSION
5.1. Variation of a and /3 with the threshold voltage dejnition As mentioned before, the measured threshold voltage change sV,,(DIBL) in eqn (1) is based on a constant current definition of V,,. For the test PMOS devices with channel length of L > LINT, because of the surface DIBL characteristics, all measured Z,, vs Vcs curves with varying VDs are
Table 1. The measured results of the values of q,, cq, PO, 8, at 300 and 77 K. Here, V,, was defined as the gate voltage at which the drain current was 1 nA Temperature (K) 300 77
Z. X. YAN and M. J. DEN
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Table 2. The extracted values of a,,, a,, PO, /3,based on measurement results with three different drain current definitions of V,, at 77 K Drain current @A)
1 10 100
(x z-2) 2.82 2.15 2.65
2.39 2.34 2.30
actually parallel within the measurement range as shown in Fig. 1, so the difference of sVr,.i(DIBL) at different Ins chosen for measuring Vrn can be neglected. However, for the devices with channel lengths L < Li,,, this difference could be significant and it depends largely on the range of drain voltages used and the channel length of the device. Table 2 lists the related DIBL parameters extracted with Vrn defined at a fixed drain current chosen from 1 to 100 nA. The measured ranges of Vu, and I’,, were chosen from - 1 to - 5 V and 0 to 4 V respectively. The corresponding variations of those DIBL parameters at 77 K were -6% for a,,, -4% for a,, - 3% for /I0 and - 1% for fi, within the range of the drain current variations from 1 to 100nA. The measured results show that the different Vrn definitions[20] within the above ranges have a small effect on the extracted DIBL parameters. This is due to the significant improvement of DIBL at 77 K, as compared with -30% variation of u, and - 10% of p, for the same test devices measured at room temperature[ 191. 5.2. Variation of CLand fl with the channel doping proJile Since the boron ion implant in channel is one of the critical factors for the substrate bias related DIBL dependence in the short channel PMOS devices, further simulations by MINIMOS 4.0 were performed in order to investigate the influence of channel doping profile variation on those DIBL parameters CIand /I introduced in our new model. The simulations were carried out by varying separately either the channel implant dose from 4.3 x 10” cm-’ to 8.7 x 10” cm-2 with a fixed implant energy of 25 keV, or the channel implant energy from 25 to 35 keV with a fixed implant dose of 6.5 x 10” cmm2. From the simulated Zns-Vc, curves, the DIBL par-
PO
(x 108: “-1)
3.35 3.30 3.24
-2.19 -2.18 -2.17
0.72 0.715 0.71
ameter R was evaluated from the gate voltage shift at the drain current of - 1 nA, due to SV,, = 1 V. The DIBL parameters of CIand /J were then extracted by the power fitting technique from the R-L figures as previously described in Section 3. These simulated results are listed in Tables 3 and 4 and they show that the extracted values of a,, u, and /Ii are very strongly related to the channel doping profile and will be briefly discussed below. increasing dose from On the implant 4.3 x 10” cmL2 to 8.7 x 10” cm-‘, a0 increased by -53%. This increase in a,, is due to the fact that the higher boron implant dose results in a higher doping concentration in the substrate, causing a more severe field penetration from the drain to the source and an increase in DIBL. The increased implant energy from 25 to 35 keV results in a deeper projected peak position of the implant profile in the substrate, resulting in an increase in DIBL and also in a0 of -27%. This increase in DIBL with implant energy is also due to the more severe field penetration from the drain to the source, but now at a deeper distance into the substrate from the Si-Si02 interface because of the higher implant energies. The value of a, is decreased to -60% for the same variations of the implant dose or energy described above. The reason for this decrease is probably due to the existence of the higher electric field near the surface channel at the higher implant dose, or the deeper minimum potential position away from the surface because of the higher implant energy. These higher electric fields near the surface, or the deeper potential positions from the surface would cause a smaller shift of the hole current flow path towards the channel surface as the substrate voltage increases from 0 to 4V. Therefore the extracted value of aI becomes less sensitive to increasing Va,.
Table 3. The simulated results of the values of q,, r*,, &,, /3,with three different implantation doses or corresponding maximum dosages at 77 K. The implant energy was kept fixed at 25 keV Implant dose (cm-‘)
Maximum dosage (cm -‘)
4.3 x 10” 6.5 x IO” 8.7 x 10”
-2 x 10’6 -4 x 10’6 -6 x lOI
1.78 2.26 3.24
4.78 3.49 I .66
3.54 3.67 4.05
-3.19 -3.52 -3.99
Table 4. The simulated results of the value of &,, a,, /3,,,8, with three different implantation energies or corresponding projected ranges at 77 K. The implant dose was kept constant at 6.5 x IO” cmm2 Implant energy (kev) 25 30 35
Projected range (rm) -0.02 -0.04 -0.06
(A-2) 2.04 2.26 2.51
(x lo%-‘) 3.75 3.49 2.86
Bo 3.75 3.67 4.01
(XlO%l) -3.61 -3.52 -4.40
Drain-induced barrier lower in PMOS devices In the case of the parameter /?, the simulations resulted in a small change of 2-6% in /IO, but a significantly larger increase in B, by -30% for the same dose variation range, or by N 56% for the same energy variation range, as stated above. Based on eqns (2) and (4), /I0 is related to the channel length variation, especially for those shorter channel devices with L < 1.0 pm. The higher implant dose or energy basically has little effect on the subsurface DIBL characteristics at Ves = 0 V, but would make the shifting of the current flow path from subsurface channel to surface channel more difficult with increasing I’,, , resulting in the increase of the absolute value of B,. 6. CONCLUSIONS
The substrate characteristics of DIBL for short channel PMOS devices with boron ion channel doping at 77 K are measured experimentally and simulated in detail using MINIMOS 4.0. As the channel length decreased, the threshold voltage shift caused by DIBL first increased with increasing substrate bias and thereafter began decreasing. This feature could be explained physically as the transition of surface DIBL to subsurface DIBL and the onset of the punch-through effect. Based on the new empirical model for describing the substrate bias-dependent characteristics of DIBL, detailed quantitative comparisons between 300 and 77 K were made. At 77 K, the extracted values of CQ and u, were N 35% decreased and N 93% increased respectively from their 300 K values. The corresponding values of p,, and /I, were -6% and N 10% decreased respectively for the same temperature reduction. All the above results clearly show the improvement of DIBL at 77 K, especially for smaller V and these improvements could be explained p&ically as the transition of the subsurface current flow towards surface current flow due to higher surface potential bending at 77 K. Further measurement and simulations of the substrate bias-related DIBL dependence were carried out with the emphasis on the threshold voltage definition and the boron ion channel doping profile. The results show that choosing different drain currents from 1 nA to 100 nA for the V,, definition had a small effect on those empirical DIBL parameters. However, at the different channel doping profiles, it was found that Q, CI, and fl, , but not /I,, were very sensitive (between 30% and 50% variation) to
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changes in either the implant or the implant energy variation. Acknowledgements-It is a pleasure to acknowledge the assistance from J. Ilowski and R. Hadaway of Northern Telecom Electronics Limited, Ottawa, Ontario and Z. P. Zuo of Simon Fraser Universitv. Bumabv, British Columbia. We are thankful to the revi&vers of this work for their useful comments and suggestions. This research was partially supported by grants from the Center for Systems Science, SFU, Northern Telecom Electronics Ltd, and the Natural Sciences and Engineering Research Council (NSERC) of Canada. REFERENCES
1. M. J. Deen, Microprocessors Microsystems 13, 245 (1989). 2. I. Kato, H. Oka, S. Hijiya and T. Nakamura, ZEDM Tech. Dig., p. 601 (1984). 3. M. J. Deen, Solid-St. Electron. 31, 291 (1988). 4. M. J. Deen and J. Wang, Proc. Symp. Low Temperature Electronics
5. 6. 7.
8. 9. 10. 11. 12. 13. 14.
and
High
Temperature
Superconductors
(Edited by S. I. Raider, R. Kirschman, H. Hayakawa and H. Ohta), p. 108. Electrochemical Society, Pennington, NJ (1988). F. H. Gaensslen, V. L. Rideout, E. J. Walker and J. J. Walker, IEEE Trans. Electron Devices ED-24, 218 (1977). M. J. Deen, IEEE J. Solid-St. Circuits 24, 158 (1989). A. Kamgar, IEEE Trans. Electron Devices ED29, 1226 (1982). J. C. S. Woo and J. D. Plummer, IEEE Trans. Electron Devices ED-33, 1012 (1986). J. Y-C. Sun, Y. Taur, R. H. Dennard and S. P. Klepner, IEEE Trans. Electron Devices ED-34, 19 (1987). _ R. R. Troutman. IEEE J. Solid-St. Circuits SC-9. 55 (1974). G. W. Taylor, IEEE Trans. Electron Devices ED-25,337 (1978). R. R. Troutman, IEEE Trans. Electron Devices ED-26, 461 (1979). R. H. Dennard, F. H. Gaensslen, E. J. Walker and P. W. Cook, IEEE Trans. Electron Devices ED-26, 325 (1979). S. G. Chamberlain and S. Ramanan, IEEE Trans.
Electron Devices ED-33, 1745 (1986). 15. K. M. Cham, S. Y. Oh, D. Chin, J. L. Moll, K. Lee and P. V. Voorde, Cornpurer-Aided Design and VLSI Device Development, 2nd edn. Kluwer, Boston (1988). 16. R. C. Jaeger and F. H. Gaensslen, IEEE Trans. Electron Devices ED-27, 914 (1980). 17. S. Selberherr, IEEE Trans. Electron Devices 36, 1464 (1989). 18. J. Zhu, R. A. Martin and J. Y. Chen, IEEE Trans. Electron Devices ED-35, 145 (1988). 19. M. J. Deen and Z. X. Yan, IEEE Trans. Electron Devices ED-37, 1707 (1990). 20. M. J. Deen and Z. X. Yan, Solid-St. Electron 33, 503 (1990).
0038-I101/90 $3.00+ 0.00 Copyright 0 1990Pergamon Press plc
THE DEPENDENCE OF DRAIN-INDUCED BARRIER LOWERING ON SUBSTRATE BIASING IN SHORT CHANNEL PMOS DEVICES AT 77K Z. X. YAN and M. J. DEEN School of Engineering Science, Simon Fraser University, Bumaby, British Columbia, Canada V5A lS6 (Received 7 November 1989; in revised form 9 April 1990) Abstract-This paper presents detailed experimental results on the substrate biasing characteristics of drain-induced barrier lowering DIBL at 77 K in short channel PMOS devices with boron ion channel doping. It was found that as the channel length decreased, the threshold voltage shift caused by DIBL first increased with increasing substrate bias, and thereafter began decreasing. The new version of the two-dimensional device numerical simulation program MINIMOS 4.0, that includes device modeling at cryogenic temperatures, was used to investigate this unique feature of DIBL vs substrate biasing. From the simulation results, the dependence of DIBL on substrate biasing could be explained as the transition of the surface DIBL effect to the subsurface DIBL effect and the onset of the punchthrough effect. Based on the experimental results, a new empirical model for describing this substrate bias-dependent characteristics of DIBL: R = 6 VTH(DIBL)/S V,, = aL -8, a = a,, + a, VW, j = & + j?, VBs has been developed, and using this model, quantitative comparisons between 77 and 300 K results were made. These comparisons clearly show the improvement of DIBL at 77 K, especially for shorter channel devices. The experimental results could be explained physically by the transition of the subsurface current flow towards the surface current flow due to higher surface potential bending at 77 K. Further analysis were carried out with the emphasis on the variation of the threshold voltage definition and the boron ion channel doping profile. It was found that the extracted parameters a and B were very sensitive to the channel implant dose and energy, but were only slightly related to the threshold voltage definition.
1. INTRODUCHON The low-temperature operation of CMOS circuits and systems is being seriously considered as an attractive alternative to room temperature operation for high performance electronic circuits and VLSI systems[l+. This is mainly due to their very low
power dissipation, higher switching speeds, steeper subthreshold slopes, improved reliability, lower leakage currents and a drastic reduction in thermally activated degradation mechanisms at low temperatures, compared with the room temperature operation of the CMOS devices and systems[l-91. Since the channel length of CMOS devices now extends to submicrometer values, the associated important short channel effects such as threshold voltage shift and drain-induced barrier lowering (DIBL) have to be carefully considered for proper device operation with long lifetimes. DIBL has previously been studied by many researchers, but most of them dealt with this effect in NMOS devices, either at room temperature or at low temperatures[8-141. On the other hand, PMOS devices with N+ polysilicon gate, (as in typical modern CMOS devices), have an additional boron ion implant in the channel that results in a buried channel PMOS device structure. It is expected that, due to this partially compensated channel doping profile and possibly freeze-out effect in this region at cryogenic temperatures[ 15-l 71,
that DIBL for this buried-channel PMOS device at 77 K, will exhibit a more complicated behavior as the channel length and substrate bias are varied. To date, there has been no publication discussing this important short-channel effect in boron channel doped PMOS devices at low temperatures. Reference [8] first reported the measured and simulated DIBL in PMOS devices at 77 K; however it was limited to devices with a constant channel length, and no effects due to substrate biasing were given. References [lo] and [14] presented detailed studies on DIBL by 2-D simulation, including the substrate bias characteristics, but only for NMOS devices at room temperature. Reference [18] also used 2-D simulations to investigate the DIBL dependence of buried channel PMOS devices on the gate oxide thickness, channel doping junction depth and source/drain junction depths, but only for devices of a fixed channel length operating at room temperature. In this paper, we shall first present experimental results of DIBL at 77 K for short channel PMOS devices, and shall then investigate the observed substrate-bias dependent characteristics using a twodimensional device numerical simulation program MINIMOS 4.0 which is suitable for low temperature simulations[l6]. Section 4 presents a detailed comparison of these substrate bias DIBL effects between 300 K and 77 K using our new empirical model[l9],
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Z. X. YAN and M. J. DEEN
1266
a liquid nitrogen Dewar. These measurements were ‘made with an automated HP4145 semiconductor parameter analyzer, with an IBM PC-AT type personal computer as the central controller. The measurement accuracy was 0.1% for voltages and 0.3-1.0% for currents within the measurement range. Figures 1 and 2 show some of these measured curves for the test PMOS devices with L = 0.9 and 0.6 pm respectively. In this paper, the parameter R was used to quantify DIBL, and it was calculated as the change in the threshold voltage sI’r,(DIBL) divided by the change in the drain voltage SV,, . Here, the threshold voltage Vr, is defined as the gate voltage Vos at which the drain current I,,, is 1 nA, as shown in Figs 1 and 2. Thus R can be expressed as
and the temperature dependence of those extracted DIBL-related parameters are explained from the device physics point of view. Additional evaluations of the substrate bias related DIBL effect with an emphasis on the variation of the threshold voltage definition and the boron ion channel doping profile at 77 K, are discussed in Section 5. The conclusions are then presented in Section 6. 2. EXPERIMENTAL DETAILS
The PMOS test devices used in this study were designed and fabricated by modern VLSI CMOS technology. The doping concentration of the N-well substrate was -2 x 1Or6cm-3. The gate oxide thickness was 250 8, and a self-aligned N+ polysilicon gate process was used. The source and drain regions were formed by boron ion implantation with their junction depths being -0.2 pm. The geometry of these test devices had effective channel lengths ranging from 0.6 to 2.4 pm, and a fixed channel width of 24 pm. These PMOS devices had an additional boron ion implantation in the channel, which was implemented simultaneously for both NMOS and PMOS devices in order to match the devices threshold voltages, as typically required for CMOS technology. This was also one of the critical steps in fabricating the devices due to the requirements for precisely controlling the threshold voltage, and for preventing the PMOS devices from turning into depletion mode transistors. The drain current vs gate voltage measurements with different drain voltage biases of - 1 to - 5 V and different substrate voltage biases of O-4 V at 77 K were made by inserting these test PMOS devices into
R = _W,(DIBL) 6 vus =--
VTH ( vDS2 ) vvDS2 -
IIDS=,“* VTH ( vDSl ) DSI
.
In eqn (l), VDsl and VDsz are chosen as -1 and -5 V respectively for all the test PMOS devices. In this paper, we defined the threshold voltage as the gate voltage at which the drain current is 1 nA. This definition of V,, was used, because for submicron devices, it results in a larger change in the gate voltage with increasing drain bias, when compared with different VT, definitions at higher drain currents such as 10 or lOOnA[20]. Also, at the lower drain current, it is quite easy to observe whether the device is operating in its punchthrough mode or not. To complete the comparison, we present later the effects
10-5 IO+ IO"
3 - 8
IOIO-' IO” 10-O 1 o-‘0 1 o-”
0.00
0.40
(1)
0.80
V GS
1.20
1.60
2.00
lv)
Fig. 1. Experimental curves of the drain current vs gate voltage at 77 K for the test PMOS device of L = 0.9 pm, W = 24 pm, with V,,, varying from - 1 to - 5 V and at the fixed value of V,, = 0 and 4 V.
Drain-induced barrier lower in PMOS devices
V GS
1267
(v)
Fig. 2. Experimental curves of the drain current vs gate voltage at 77 K for the test PMOS device of L = 0.6 pm, W = 24 pm, with V,, varying from - 1 to - 5 V and at the fixed value of Vss = 0 and 4 V.
of choosing larger drain currents of 10 and 100 nA on the DIBL parameter R. 3.
MEASUREMENT
RESULTS
In order to quantitatively illustrate the measured substrate biasing characteristics of DIBL, the new empirical DIBL model developed in Ref. [19] is used here. It is R = ~Vr,(DIBL)/GVo,
= --c( I+.
(2)
Based on experimentally extracted values of doand fi, a linear dependence on V,, is suggested, that is, GI=a,+cc,.
V,,
(3)
B =B0+81.
VW.
(4)
The parameter L,,, discussed below, is defined as
From these figures, we can make the following interesting observations: (1) the extracted curve-fitting parameters of CI and /l in eqn (2) are really not constant with respect to V,, as implied in the previous models of Refs [12,14], but rather could be described more accurately by our new model using eqns (3) and (4); (2) the DIBL variation with the substrate bias in Fig. 3 is divided into two sections by the channel length L,,,, roughly corresponding to the intersection region of R vs L curves for different Vss values. In the region L > LINT, the threshold voltage shift 6Vr,(DIBL) increases as the sub250
+
200
+
150
WI. (VW - vrd-
’
1
(5)
The experimental curves of the DIBL parameter R vs channel length L with different substrate voltage biases V,, at 77 K are shown in Fig. 3. The R values measured were based on eqn (1). The solid lines in this figure are the curve fitting results using the power relationship between R and L in eqn (2). The extracted values of c( and /I vs Ves are plotted in Fig. 4 and similar results were also obtained from our test PMOS devices at room temperature[l9].
0”
dr
1”
0
2v
+
Jv
.
4”
100
50
0 0.50
1.00
1.50
2.00
2.50
L (micron) Fig. 3. The measured results of the DIBL parameter R vs effective channel length for the test PMOS devices at 77 K. The different curves are for V,, varying from 0 to 4V.
Z. X.
1268
YAN
and M. J.
DEEN
40.0
30.0
tl
Q_ 20.0
10.0 0.0 -2.00 0.0 1.0
2.0
3.0
4.0
v, (VI
Channel
Depth
(micron)
Fig. 4. The measured results of the u and the fi vs Vss for the test PMOS devices at 77 K. a and p are obtained from the empirical model described in eqns (2H4) in text.
strate voltage VBs is increased, but the opposite variation occurs in the region L < L,,, . The value of J&r in the case of our test devices is between 0.684.74pm from the measurements shown in Fig. 3, and 0.72pm from the calculation using eqn (5) with Vssl = 0 V and Vss2= 4 V. The cause for DIBL in short channel MOS devices is the significant field penetration from drain to source, due to the closeness of their junction depletion regions[8,12,14]. In the case of the enhancement mode NMOS devices, this DIBL and the related increased electron injection occurs at the channel surface and is usually referred to as surface DIBL[8,12]. For our test PMOS devices, although they are still designed and operated in enhancement mode as required for CMOS technology, a lightly doped P-type buried channel between the source and drain regions under the gate was formed, and the carrier freeze-out effect at cryogenic temperature might also take place with this partially compensated channel doping device structure[ 15,161. In order to explain the above measured DIBL characteristic, the two-dimensional device numerical simulation program MINIMOS 4.0 was used throughout this paper to get those basic and important physical quantities, such as the electrostatic potential distribution, the lateral hole current density distribution, and the subthreshold current under various biasing conditions at 77 K. Figures 5(a) and (b) show the simulated electrostatic potential distribution and the lateral hole current density perpendicular to the channel length direction at the point of the minimum surface potential for the devices with L = 0.6, 0.7 and 0.9 pm, and at Vss = 0 and 4 V respectively. The gate voltage was adjusted to obtain a drain current of = 1 nA at a drain voltage Vn, = - 1 V. From Fig. 5, it is easy to observe that as the channel length is reduced from 0.9 to 0.6 pm (passing through the LINTregion shown previously in Fig. 3), that the current flow path
u /..’
1.10
0.10 -0.90
;
1; (j
/4’
Ii /..’ :
IO-
v,=4v
4
k
v,=-
----
lo-’ L=oswn ,o* 1v
L-o.7m L4.W
IO_
c
0.00
0.20
Channel
0.40
Depth
IO_‘0
0.60
0.80
(micron)
@I
Fig. 5. The simulated results of the electrostatic potential distribution and lateral hole current density vs channel depth at 77 K for the PMOS device of L = 0.9 pm with VDs = - 1 V at (a) V,, = 0 V; and (b) V,, = 4 V, respect-
ively. VGs was adjusted to fix the value of I,, = 1nA. changes gradually from the surface channel towards the subsurface channel in the case of Ves = 0 V, but it still remains along the surface channel for Ves = 4V. From the substrate bias-related DIBL dependence shown in Fig. 3, we conclude that this DIBL is the surface DIBL phenomenon for the whole range of Vss variation for the devices with L > LINT, whereas it gradually changes from a subsurface DIBL to a surface DIBL with increasing substrate biases for the devices with L < LLNT. Given the surface DIBL feature for devices with L > &NT, the surface potential distribution along the channel surface direction with Va, = 0 and 4 V was computed by MINIMOS 4.0 for the device of L = 0.9 pm. The gate voltage for V,,, = - 5 V was chosen to be the same as that for ‘Vns= - 1 V and the simulated results of the surface potential distribution are plotted in Fig. 6. As shown in this figure, we see that as the substrate voltage bias increases from 0 to 4V, the transition width of the potential barrier
Drain-induced barrier lower in PMOS devices -6.00
2 3 .-
e
,
I
L=O.9m - 5.00
f-
I ----v,=ov v_+v
- 4.00
0.00
fl I
t. 0.00
0.30
Distance
0.60
Based on the above discussions, the channel length L INT, corresponding to the average intersection points of the R vs L curves in Fig. 4 actually
v,=-5v
I
1269
represents the transition from the surface DIBL for Ves = OV. By examining the experimental drain current curves for the L = 0.6 pm device in Fig. 2, the subthreshold slope [defined as log(Zn,/V,,)] decreased slightly with increasing Vn, at I’,, = 0 V, compared with almost parallel curves for the L = 0.9 pm device shown in Fig. 1. This indicates that the punchthrough effect is indeed observed experimentally and confirmed by simulations for the devices of channel lengths L < L,,,.
0.90
(micron)
Fig. 6. The simulated results of the surface potential vs channel length at 77 K for the PMOS device of L = 0.9 Nrn with Vi,,=--1 or -5V and Va,=OV or Pas= -4V, reswctivelv. V,. was chosen to lx -0.995 V for V,,, = 0 and - 1.472 V ?or ya, = 4 V at V,, = - 1 V (in order”;0 fix the I,, 1 1 nA). At V,,, = -5 V, the same values of V,, were used for V,, = 0 and 4 V. variation between the source (or drain) and the channel becomes wider due to the increase of the barrier height, in agreement with that reported in Ref. [14]. This increased barrier height at the higher substrate bias would increase the field penetration from the drain to the source, causing a reduction in the effective channel length that results in an increase in DIBL, when compared to the case at zero substrate voltage bias. This increase in the barrier height at the
higher substrate biases is the reason for the increased DIBL for devices with L > L,,,. For example, from Fig. 6, the minimum surface potential difference at I’,,= -1 and -5V is 42mV for V,,=OV, but is 68 mV for Pa, =4V, which further confirms our measurement results. On the other hand, for the device with L = 0.6 pm which is less than L,,,, the current flow paths at varying VBsbiases are quite different, as shown in Fig. 5. The minimum potential is now located at -0.06 pm below the surface with V,, = 0 V, so most of the hole current is now flowing through this subsurface channel. The device is actually operating in the punchthrough mode, which is more severe due to the existence of the P-type buried channel as previously discussed in Refs [ 1l-l 31. However, as the substrate bias voltage increases to 4 V, the depletion layer width between the surface and the substrate widens to about 0.7 pm as shown in Fig. 5(b), which is wider than the depletion layer width (0.4pm) for Pas = 0 V, as shown in Fig. 5(a). Also the transverse electric field near the surface increases at the higher substrate bias of 4 V, and this causes a shift in the minimum potential point back to the surface. Therefore, the gate voltage now has more control on the drain current at Ves = 4 V, compared with that of the subsurface current flow at Pas = 0 V, resulting in less DIBL at the higher V,, bias.
4. TEMPERATURE
COMPARISONS
The comparison of the measured drain-current vs gate-voltage curves and the corresponding substratebias DIBL dependences for the test PMOS devices at 77 and 300 K are shown in Figs 7 and 8. From these two figures, we see that DIBL is improved at 77 K, within the measured ranges of V,, = O-4 V, and of L = 0.62.4 pm, especially for shorter channel devices of L < 1.2 Zirn. In order to compare these characteristics quantitatively, the new empirical DIBL model described by eqns (2)-(5) was used, and all the DIBL parameters that we‘re extracted from the measured substrate bias DIBL dependent curves based on the VTH definition of 1 nA are listed in Table 1. The detailed comparison are as follows:
The extracted values of the DIBL parameters CI,,and a, based on eqn (3) are 2.82 x lo-* and 2.39 x 10e3 V-i for 77 K, and 3.65 x lo-* and 1.24 x lo-’ V-’ for 300 K respectively. The physical meaning of a could be expressed as the threshold voltage shift due to a change in the drain bias SV,, of 1 V for a device of unit channel length (1 .Opm). Therefore as the temperature decreases from 300 to 77 K, DIBL is improved by -35% for the case of Vss = 0 V, and by -9% for V,, = 4 V. (2) B The extracted values of the DIBL parameters /I0 and /I, based on eqn (4) are 3.35 and -0.219 V-’ at 77 K, and 3.55 and -0.243 V-’ at 300 K, respectively. The physical meaning of /l is the curvature of the R vs L curves, which is much more dependent on the characteristics of the submicron devices as seen from eqn (2). Therefore the -6% and -4% decrease of B at Vss = 0 V and Ves = 4 V respectively on decreasing the temperature from 300 to 77 K also means that there is less DIBL for submicron devices operated at 77 K. (3) L,N, From Fig. 7, the DIBL parameter L,,, was measured as 0.71 pm at 77 K and 0.88 pm at 300 K
Z. X. YAN and
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M. J. DEEN
lo-’ 10+ IO” IO_ IO-’ 10d IO4 1 o-‘0
IO-” -0.20
0.20
0.00
0.40
V GS
0.80
1.20
1.20
1.60
(V)
(4
0.00
0.40
0.80,
0.80
V GS (b)
lv)
Fig. 7. Experimental curves of the drain current vs gate voltage at 300 and 77 K for the test PMOS device
of L = 0.9 pm, W = 24 pm, with V,, = - 1 a;d :i,“, BS with Vss, = 0 V and VBs2= 4 V. The smaller value of G,, at 77 K compared to 300 K indicates that the punchthrough effect would take place at shorter lengths in buried channel PMOS devices. The calculated values of I,,,, based on eqn (8) are 0.72 /*rn for
at the fixed value of (a) V,, = OV; and (b)
77 K and 0.88 pm for 300 K respectively[l9], in good agreement with the measured values. The reason for this improvement of the substrate bias DIBL dependence at 77 K could be explained physically by partial impurity ionization in the sub-
Drain-induced barrier lower in PMOS devices
300
+ OV
300K
b
4v
3oOK
l
OV
77K
.
4V
77K
1271
200
1.oo
0.50
I .50
2.00
2.50
0.00
L (micron) Fig. 8. The measured results of the DIBL parameter R vs effective channel length for the test PMOS devices with a fixed substrate biases of V,, = 0 and 4 V, at temperatures of 77 and 300K. strate of the PMOS device. Usually, the impurity doping concentration in the substrate is assumed to be fully ionized at room temperature, but not at low temperatures. It is well known that the variation in the impurity ionization concentrations with temperature[l6] are described by the following equations
ND
N,+=
NA
Ni =
(6)
(7)
where ED and EA are the ionization energies of the respective donor and acceptor dopants, and Ef, and Elp are the quasi-Fermi levels of the electrons and holes respectively. Therefore, the effective doping concentration (Ng - NA) in PMOS devices might be significantly decreased at 77 K. This freeze-out effect was also experimentally observed for our test buried-channel PMOS devices, as shown previously in Fig. 2. However, for the subthreshold conduction and the related DIBL effect at 77 K, freeze-out effects in the channel are not important, as previously described in Refs [l&16] and also confirmed by our simulation results. On the other hand, this freeze-out effect in the bulk of the PMOS devices at 77 K would cause some effect on DIBL, as explained shortly. Figure 9 shows the simulation results of the electrostatic potential profile and the lateral hole current density normal to the channel length direction for L = 0.9 pm PMOS device at 300 and 77 K. These
0.10
0.20
Channel
0.30
Depth
0.40
0.50
(micron)
Fig. 9. The simulated results of the surface potential bending profile and the lateral hole current density normal to the channel direction, for the PMOS device of L = 0.9 pm with the fixed biases of Vss = 0 V and V,, = - 1 V and at 77 and 300 K.
simulated results were obtained by adjusting the gate voltage until a drain current of _ 1 nA was obtained. From Fig. 9, as the temperature decreased from 300 to 77 K, the surface potential bending normal to the channel length direction needed for the subthreshold conduction at 1,, = 1 nA is increased from 0.48 to 1.04 V. This increase in the surface potential bending is due to the freeze-out effect in the substrate, as expected from eqns (6) and (7), and also pointed out in Ref. [7]. As before, the minimum potential point is located about 0.04 pm below the surface at 300 K, but is almost at the surface at 77 K. This is quite similar to the case of increasing substrate bias at a fixed temperature as discussed above, and could be explained by the higher surface potential bending at the lower temperature of 77 K. Therefore the hole current flow path would shift back from the subsurface channel at 300 K to the surface channel at 77 K, and this results in the improvement of the DIBL effect and a decrease of the corresponding parameters a, fi and L,,,. 5.
DISCUSSION
5.1. Variation of a and /3 with the threshold voltage dejnition As mentioned before, the measured threshold voltage change sV,,(DIBL) in eqn (1) is based on a constant current definition of V,,. For the test PMOS devices with channel length of L > LINT, because of the surface DIBL characteristics, all measured Z,, vs Vcs curves with varying VDs are
Table 1. The measured results of the values of q,, cq, PO, 8, at 300 and 77 K. Here, V,, was defined as the gate voltage at which the drain current was 1 nA Temperature (K) 300 77
Z. X. YAN and M. J. DEN
1272
Table 2. The extracted values of a,,, a,, PO, /3,based on measurement results with three different drain current definitions of V,, at 77 K Drain current @A)
1 10 100
(x z-2) 2.82 2.15 2.65
2.39 2.34 2.30
actually parallel within the measurement range as shown in Fig. 1, so the difference of sVr,.i(DIBL) at different Ins chosen for measuring Vrn can be neglected. However, for the devices with channel lengths L < Li,,, this difference could be significant and it depends largely on the range of drain voltages used and the channel length of the device. Table 2 lists the related DIBL parameters extracted with Vrn defined at a fixed drain current chosen from 1 to 100 nA. The measured ranges of Vu, and I’,, were chosen from - 1 to - 5 V and 0 to 4 V respectively. The corresponding variations of those DIBL parameters at 77 K were -6% for a,,, -4% for a,, - 3% for /I0 and - 1% for fi, within the range of the drain current variations from 1 to 100nA. The measured results show that the different Vrn definitions[20] within the above ranges have a small effect on the extracted DIBL parameters. This is due to the significant improvement of DIBL at 77 K, as compared with -30% variation of u, and - 10% of p, for the same test devices measured at room temperature[ 191. 5.2. Variation of CLand fl with the channel doping proJile Since the boron ion implant in channel is one of the critical factors for the substrate bias related DIBL dependence in the short channel PMOS devices, further simulations by MINIMOS 4.0 were performed in order to investigate the influence of channel doping profile variation on those DIBL parameters CIand /I introduced in our new model. The simulations were carried out by varying separately either the channel implant dose from 4.3 x 10” cm-’ to 8.7 x 10” cm-2 with a fixed implant energy of 25 keV, or the channel implant energy from 25 to 35 keV with a fixed implant dose of 6.5 x 10” cmm2. From the simulated Zns-Vc, curves, the DIBL par-
PO
(x 108: “-1)
3.35 3.30 3.24
-2.19 -2.18 -2.17
0.72 0.715 0.71
ameter R was evaluated from the gate voltage shift at the drain current of - 1 nA, due to SV,, = 1 V. The DIBL parameters of CIand /J were then extracted by the power fitting technique from the R-L figures as previously described in Section 3. These simulated results are listed in Tables 3 and 4 and they show that the extracted values of a,, u, and /Ii are very strongly related to the channel doping profile and will be briefly discussed below. increasing dose from On the implant 4.3 x 10” cmL2 to 8.7 x 10” cm-‘, a0 increased by -53%. This increase in a,, is due to the fact that the higher boron implant dose results in a higher doping concentration in the substrate, causing a more severe field penetration from the drain to the source and an increase in DIBL. The increased implant energy from 25 to 35 keV results in a deeper projected peak position of the implant profile in the substrate, resulting in an increase in DIBL and also in a0 of -27%. This increase in DIBL with implant energy is also due to the more severe field penetration from the drain to the source, but now at a deeper distance into the substrate from the Si-Si02 interface because of the higher implant energies. The value of a, is decreased to -60% for the same variations of the implant dose or energy described above. The reason for this decrease is probably due to the existence of the higher electric field near the surface channel at the higher implant dose, or the deeper minimum potential position away from the surface because of the higher implant energy. These higher electric fields near the surface, or the deeper potential positions from the surface would cause a smaller shift of the hole current flow path towards the channel surface as the substrate voltage increases from 0 to 4V. Therefore the extracted value of aI becomes less sensitive to increasing Va,.
Table 3. The simulated results of the values of q,, r*,, &,, /3,with three different implantation doses or corresponding maximum dosages at 77 K. The implant energy was kept fixed at 25 keV Implant dose (cm-‘)
Maximum dosage (cm -‘)
4.3 x 10” 6.5 x IO” 8.7 x 10”
-2 x 10’6 -4 x 10’6 -6 x lOI
1.78 2.26 3.24
4.78 3.49 I .66
3.54 3.67 4.05
-3.19 -3.52 -3.99
Table 4. The simulated results of the value of &,, a,, /3,,,8, with three different implantation energies or corresponding projected ranges at 77 K. The implant dose was kept constant at 6.5 x IO” cmm2 Implant energy (kev) 25 30 35
Projected range (rm) -0.02 -0.04 -0.06
(A-2) 2.04 2.26 2.51
(x lo%-‘) 3.75 3.49 2.86
Bo 3.75 3.67 4.01
(XlO%l) -3.61 -3.52 -4.40
Drain-induced barrier lower in PMOS devices In the case of the parameter /?, the simulations resulted in a small change of 2-6% in /IO, but a significantly larger increase in B, by -30% for the same dose variation range, or by N 56% for the same energy variation range, as stated above. Based on eqns (2) and (4), /I0 is related to the channel length variation, especially for those shorter channel devices with L < 1.0 pm. The higher implant dose or energy basically has little effect on the subsurface DIBL characteristics at Ves = 0 V, but would make the shifting of the current flow path from subsurface channel to surface channel more difficult with increasing I’,, , resulting in the increase of the absolute value of B,. 6. CONCLUSIONS
The substrate characteristics of DIBL for short channel PMOS devices with boron ion channel doping at 77 K are measured experimentally and simulated in detail using MINIMOS 4.0. As the channel length decreased, the threshold voltage shift caused by DIBL first increased with increasing substrate bias and thereafter began decreasing. This feature could be explained physically as the transition of surface DIBL to subsurface DIBL and the onset of the punch-through effect. Based on the new empirical model for describing the substrate bias-dependent characteristics of DIBL, detailed quantitative comparisons between 300 and 77 K were made. At 77 K, the extracted values of CQ and u, were N 35% decreased and N 93% increased respectively from their 300 K values. The corresponding values of p,, and /I, were -6% and N 10% decreased respectively for the same temperature reduction. All the above results clearly show the improvement of DIBL at 77 K, especially for smaller V and these improvements could be explained p&ically as the transition of the subsurface current flow towards surface current flow due to higher surface potential bending at 77 K. Further measurement and simulations of the substrate bias-related DIBL dependence were carried out with the emphasis on the threshold voltage definition and the boron ion channel doping profile. The results show that choosing different drain currents from 1 nA to 100 nA for the V,, definition had a small effect on those empirical DIBL parameters. However, at the different channel doping profiles, it was found that Q, CI, and fl, , but not /I,, were very sensitive (between 30% and 50% variation) to
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changes in either the implant or the implant energy variation. Acknowledgements-It is a pleasure to acknowledge the assistance from J. Ilowski and R. Hadaway of Northern Telecom Electronics Limited, Ottawa, Ontario and Z. P. Zuo of Simon Fraser Universitv. Bumabv, British Columbia. We are thankful to the revi&vers of this work for their useful comments and suggestions. This research was partially supported by grants from the Center for Systems Science, SFU, Northern Telecom Electronics Ltd, and the Natural Sciences and Engineering Research Council (NSERC) of Canada. REFERENCES
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