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structure interaction phenomenon in IC packaging
Microelectronics Reliability 52 (2012) 241–252
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Investigation of the fluid/structure interaction phenomenon in IC packaging C.Y. Khor ⇑, M.Z. Abdullah, H.J. Tony Tan, W.C. Leong, D. Ramdan School of Mechanical Engineering, Universiti Sains Malaysia, Engineering Campus, 14300 Nibong Tebal, Penang, Malaysia
a r t i c l e
i n f o
Article history: Received 16 July 2011 Received in revised form 14 September 2011 Accepted 14 September 2011 Available online 2 October 2011
a b s t r a c t In the present study, experiment and simulation studies were conducted on the fluid/structure interaction (FSI) analysis of integrated circuit (IC) packaging. The visualisation of FSI phenomenon in the actual package is difficult due to limitations of package size, available equipment, and the high cost of the experimental setup. However, the experimental data are necessary to validate the simulation results in the FSI analysis of IC packaging. Scaled-up package size was fabricated to emulate the encapsulation of IC packaging and to study the effects of FSI phenomenon in the moulded package. The interaction between the fluid and the structure was observed. The deformation of the imitated chip was studied experimentally. The air-trap mechanism that occurred during the experiment is also presented in this paper. Simulation technique was utilised to validate the experimental result and to describe the physics of FSI. The predicted flow front was validated well by the experiment. Hence, the virtual modelling technique was proven to be excellent in handling this problem. The study also extends FSI modelling in actual-size packaging. Ó 2011 Elsevier Ltd. All rights reserved.
1. Introduction The trend of integrated circuit (IC) packaging is toward miniaturisation. Modern ICs are designed to be very thin, with high memory capacity, and with improved performance for various applications in electronic devices. To accomplish these characteristics, engineers, package designers, and researchers place continuous efforts in research. The use of the thinned silicon chip and the solder bump has enabled the IC package to be miniaturised with high interconnectivity. The thinned chip has also facilitated three-dimensional (3D) packaging [1] and 3D integration [2] technology in microelectronic technology. With the rapid development of IC packaging technology, reliability is a main issue in the manufacturing process. To maintain reliability and quality, IC encapsulation technology is widely used to protect the silicon chip, solder bumps, wire bonds, lead frame, and paddle from the hazardous environment. In this technology, an epoxy moulding compound (EMC) is applied to the structures (chip and solder bumps), causing deformation. The structures become subjected to stress that may induce unintended defects. Hence, packaging reliability is reduced. Numerical and experimental investigations on microchip encapsulation were carried out by Reddy et al. [3] to solve the paddle shift problem. They developed an analytical model for paddle shift predictions. In addition, their study also reported on the effect of cavity thickness. Islam et al. [4] discussed the concept of flip-chip (FCMBGA) using moulding
⇑ Corresponding author. Tel.: +60 195637283. E-mail address: [email protected] (C.Y. Khor). 0026-2714/$ - see front matter Ó 2011 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2011.09.013
compound to enhance packaging reliability. The application of moulding compound improved the warpage and reduced the package size. Reliability of passive components and solder joints was also increased. No cracks were found on the package. Moreover, Liu et al. [5] carried out an investigation on the effect of moulded underfill material to package reliability. The moulding material was found to be excellent for the transfer process of moulded underfill. This process minimised packaging time and improved package reliability. The application of transfer moulding on the matrix array flip-chip underfill process was reported by Kooi et al. [6]. They found that over-moulded packages yield better reliability without any crack at the mould corner. Chen [7] compared conventional underfill and moulded underfill package through impact testing. Solder bumps, low-K chip, bump stress, and package co-planarity and reliability were considered. Stress improvements of 58.3%, 8.4%, and 41.8% were found for the solder bumps, chip, and coplanar of the moulded package, respectively. Chen also reported that moulded underfill packaging was applicable to large die and large packaging sizes with low-K chip, as well as all kinds of bump compositions. The vacuumed transfer moulding of FCMBGA with low CTE core substrate encapsulation was studied by Jung et al. [8]. The method effectively eliminated void in the package. The stress threshold of the package was also improved by using a low coefficient of thermal expansion substrate with the low-K device package. Moreover, optimisations of the overmoulded flip-chip package-on-package (PoP) design and material selection were studied by Lin and Shi [9] using finite element method (FEM). Virtual modelling is a significant method for the simulation and improvement of IC packaging. Modelling tools such as PLICE-CAD
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Nomenclature A1, A2 B C1, C2 CP E1, E2 E F ~ g k K1, K2 m1, m2 n p T t Tb u v
pre-exponential factors, 1/s exponential-fitted constant, Pa s fitting constant specific heat, J/kg K activation energies, K elastic modulus, GPa front advancement parameter gravitational acceleration, m/s2 thermal conductivity, W/m K rate parameters described by an Arrhenius temperature dependency, 1/s constants for the reaction order power law index pressure, Pa temperature, K time, s temperature-fitted constant, K fluid velocity component in x-direction, mm/s fluid velocity component in y-direction, mm/s
[10], FORTRAN [11], FLUENT [12], C-MOLD [13,14], and Moldex3D [15] have been utilised for continuous improvement in various types of IC packages. Computer aided engineering (CAE) and FEM-based software have also assisted the research for wire bonding [16] and paddle shift [17] enhancements during the encapsulation process. Therefore, implementation of virtual modelling in the microelectronic industry contributes to the better understanding of encapsulation and enhancement to IC packages. In the present study, experiment and fluid/structure interaction (FSI) simulation are carried out on the imitation of the IC package. The simulation technique is also applied for the actual size of the moulded packaging. FLUENT 6.3.26, ABAQUS 6.9, and MpCCI are used for the modelling of the FSI phenomenon [18] in the encapsulation process. In the actual packaging, EMC fluid behaviour is modelled by the Castro–Macosko model with curing effect. Appropriate user-defined functions (UDFs) are written and incorporated into the FLUENT analysis. The volume of fluid (VOF) is applied for flow front tracking during the process. During real-time FSI simulation, MpCCI is used to transfer the forces induced during the encapsulation process (FLUENT) to ABAQUS for simultaneous structural analysis. The present experiment and virtual modelling technique in moulded packaging should provide reliable predictions and better understanding of the IC encapsulation process.
2. Problem description The small IC package and non-transparent packaging mould used in the actual encapsulation process causes difficulties in visualisation of the FSI phenomenon. FSI also occurs in the encapsulation of wire-bonding package, as extensively reported in available literature. The deformation of the wire bond is normally observed from the top view of the package. However, the visualisation of FSI in the moulded flip-chip package is more complicated than the wire-bonding package. The horizontal position of the chip complicates FSI visualisation. The chip is also thin and tiny in package size. The best method for visualisation of FSI is through cross-sectional and side views of the mould. Investigation can also be conducted using simulation tools. Therefore, a transparent and scaled-up mould was fabricated to emulate the moulded package with silicon chip, solder bumps, and substrate for the encapsulation process, as illustrated in Fig. 1. Two different gap heights (h = 0.4 and 0.65 cm) were considered to enable the better visualisation of
w x, y, z
fluid velocity component in z-direction, mm/s Cartesian coordinates
Greek symbols a conversion of reaction agel degree of cure at gel DH exothermic heat of polymerisation, J//kg g viscosity, Pa s g0 zero shear rate viscosity, Pa s q density, kg/m3 q solid density, kg/m3 $s r recoverable stresses, Pa s shear stress, Pa c_ shear rate, 1/s s parameter that describes the transition region between zero shear rates and the power law region of the viscosity curve, Pa m Poisson ratio
Fig. 1. Scale model of IC package.
FSI, fluid flow and air trap phenomenon in the experimental work. The virtual modelling technique using finite volume (FV) and finite element (FE) codes was utilised for the FSI analysis. 3. Governing equations In virtual modelling, the finite volume method (FVM)-based software (FLUENT) was used for the fluid analysis, whereas FEMbased software (ABAQUS) was used for the structural calculation. Three-dimensional incompressible flow transport equations (FLUENT) i.e., continuity (conservation of mass), Navier–Stokes, and Newtonian fluids equations are given below: Continuity equation:
@u @ v @w þ ¼0 þ @x @y @z
ð1Þ
Navier–Stokes equation: x-direction
@u @u @u @u 1 @p þu þv þw ¼ @t @x @y @z q @x @ @u @ @u @ @u þ þ þ g g g @x @x @y @y @z @z ð2Þ y-direction
@v @v @v @v 1 @p þu þv þw ¼ @t @x @y @z q @y @ @v @ @v @ @v þ g g g þ þ @x @y @z @x @y @z ð3Þ
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z-direction
@w @w @w @w 1 @p þu þv þw ¼ @t @x @y @z q @w @ @w @ @w @ @w þ þ þ g g g @x @x @y @y @z @z
$ @~ u þ~ u:r~ u ¼ r r þqs~ g qs @t
243
ð7Þ
where qs is the density of solid, ~ u is the velocity of solid in x, y and z $ axis, r is the recoverable stresses, and ~ g is the gravitational acceleration.
ð4Þ 4. Experimental setup
Newtonian fluid equation:
s g¼ _ c
ð5Þ
where s is the shear stress and c_ is the strain rate. The VOF model was utilised for flow front tracking during encapsulation. In the model, F specifies the fraction of the cell’s volume occupied by liquid. Here, F takes the value 1 (F = 1) in cells containing only resin, the value 0 (F = 0) in cells void of resin, and the value between 0 and 1 (0 < F < 1) in ‘interface’ cells (referred as the resin melt front). The equation for melt front over time is governed by the following transport equation:
dF @F @F @F @F ¼ þu þv þw dt @t @t @t @t
( ) @2F @2F @2F ¼0 þ þ @x2 @y2 @z2
ð6Þ
Moreover, the following momentum equation was used in FEM (ABAQUS) for solving the structural deformation:
(a) Actual
Fig. 2 depicts the actual diagram and schematics of the experimental setup. Test fluid with constant viscosity of 4 Pa s and density of 1067 kg/m3 was utilised as a fluid medium. The servomotor illustrated in Fig. 2 controlled system delivery of the test fluid into the mould. The system was tested to obtain constant pressures (70.76 kPa, 113.13 kPa, and 161.14 kPa) for the experiment. The FSI process during encapsulation was recorded using a camera and was processed by computer. The detailed and exploded views of the mould are presented in Fig. 3. The mould was fabricated from transparent Perspex for better visualisation. The material used for the imitated chip was a thin sheet of plastic. Scale model of the IC package with different gap heights were built and labelled as shown in Fig. 4. The dimensions of the cavity were 9 cm 4.5 cm 1.5 cm. The thickness of the imitated substrate was 0.5 cm. The dimensions of the imitated chip were 7 cm 3.5 cm 0.02 cm. The gap heights (h) were 0.65 and
(b) Schemaatic diiagrram
Fig. 2. (a) Actual diagram and (b) schematics of the experimental setup.
Fig. 3. (a) Detailed and (b) exploded views of the mould.
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Imitated chip
Imitated bump
Imitated substrate
Elastic modulus, E (GPa) Poisson ratio, m Solid density, qs (kg/m3)
1.571
213
2.7
0.37 1180
0.29 7710
0.375 1170
(a) h = 0.65cm tions of structures were calculated simultaneously. The structures (chip, bumps, and substrate) were defined as the coupled regions in FSI simulation. FLUENT was used to solve the fluid flow modelling by simulating the physic of flow front that filled the cavity. ABAQUS was used to calculate the displacement and von Mises stress during the encapsulation process.
(b) h = 0.40cm
5.1. FLUENT modelling
Fig. 4. Detailed view of imitated bumps, chip, and substrate with different gap heights (h).
0.4 cm. The present experimental work only focused on the interaction between the fluid and the structures. Thus, temperature effect was not considered in the experiment. 5. FSI simulation modelling The basic idea of FSI modelling in the present study is the coupling of FVM- and FEM-based software in conducting the fluid and structural analyses. During FSI analysis, the transformation of analysis generated from the FLUENT 6.3.26 to ABAQUS 6.9 was performed using MpCCI. Real-time data were transferred from one program to the other. The forces induced from the fluid acting on the structures were directly solved by ABAQUS. Thus, the deforma-
In the FLUENT analysis, the 3D model was built according to the dimensions of the package fabricated in the experimental work. The model was meshed with a total of 92,986 tetrahedral elements. Fig. 5 illustrates the (a) boundary conditions and (b) meshed model of the imitated IC package. The surface of the mould, substrate, chip, and bump were defined as wall boundaries under no-slip condition. Temperature effect was not considered in the experiment. Therefore, this process was assumed to be isothermal during the simulation and was set at room temperature. FSI phenomenon focused on the fluid feeding into the cavity until the ‘final’ stage, which is before the plunger is retracted from the fluid cylinder. The boundary and initial conditions are as follows: @p (a) On wall: u ¼ v ¼ w ¼ 0; T ¼ T w ; @n ¼ 0, @u @v @w @T (b) On centre line: @z ¼ @z ¼ @z ¼ @z ¼ 0,
Fig. 5. Boundary conditions and meshed model of the imitated IC package.
Fig. 6. Structural meshed model.
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Fig. 7. Experimental (70.76 kPa) and simulation (FLUENT) results.
(c) On melt front: p = 0, (d) At inlet: p = pin(x, y, z); T = Tin.
Flow front advancement, x (cm)
10 Experiment FLUENT
8
Upper stream
6
Lower stream
4
2
0 0.0
0.5
1.0
1.5
2.0
2.5
Time (s) Fig. 8. Flow front advancement (at upper stream and lower stream) versus filling time.
In the analysis, the VOF model was used to solve the modelling of fluid and air during the filling process. Fluid and air were defined as the phases in the analysis. The viscosity of the fluid varied with shear rate, as calculated by Eq. (5). The VOF model was used to solve a set of single momentum equations. This set was shared by the fluid and the volume fractions of each of the fluids in the computational cell, which were tracked throughout the domain [19]. A second-order upwind scheme was used for the momentum and volume fraction equations. A SIMPLE algorithm was applied for pressure–velocity calculation. Implicit solution and time-dependent formulation were considered for the volume fraction in each time step. The optimum time step size of 0.001 was utilised in the analysis. The simulation took around 8 h to complete one case. An Intel Core i3 processor with i3-540, 3.07 GHz, and 3.24 GB of RAM was used for the simulation. 5.2. ABAQUS modelling Fig. 6 shows the model of coupled regions (imitated chip, bumps, and substrate) for structural analysis. The 3D meshed mod-
Fig. 9. Initial and deformed view at the edge of imitated chip for 0.65 cm (113.13 kPa).
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Fig. 10. Initial and slightly deformed view at the centre of imitated chip for 0.4 cm (70.76 kPa).
el was generated using hexahedral with sweep method by ABAQUS 6.9. The mechanical aspects were considered. Thus, the structures
of the coupled regions were defined as deformable in the analysis. In the experiment, the structures of chip and bumps were properly
Fig. 11. FSI simulation for gap height of 0.4 cm.
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positioned on the imitated substrate in the cavity. Therefore, the fixed boundary condition was set at the bottom surface of the imitated substrate, as depicted in Fig. 6a and b. In addition, some basic assumptions were considered in the FEM analyses [20] for simplification purpose. Elastic behaviour was taken as homogeneous and isotropic in the structures of chip and bump [21,22]. The solder pad effect was neglected, where the solder pad was not considered in the scaled-up model. The bump and chip were perfectly bonded in the experiment work, where the bonding between chip and bumps assumed to be fully adhesive. The temperature effect on the structures was not considered in the experimental work. Therefore, thermal effect on the creep and fracture behaviour was not considered in the present modelling. The mechanical properties of emulated chip, bump, and substrate are summarised in Table 1. 6. Results and discussion 6.1. Model validation The experiments were conducted for a scaled-up moulded package prototype. The filling process of the viscous fluid into the cavity was recorded in front of the transparent mould. FSI simulation was also performed on the imitated package with gap height of 0.4 cm, as presented in Fig. 7. The flow front advancement of the simulation results was compared with the experimental results. The results show that flow front predictions from the simulation code had nearly the same profile with the experimental results at different filling times. The flow front advancement measurements are plotted in Fig. 8 for upper (top of chip) and lower (beneath of chip) streams. Both streams showed an approximately identical trend with only 5.16% and 6.33% average discrepancy. Therefore, the present modelling techniques yield reliable predictions in handling moulded packaging problem. 6.2. Fluid/structure interaction (FSI) The FSI phenomenon was investigated through experimental work for gap heights of 0.4 and 0.65 cm at different pressures. Only
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selected results are presented in this paper. Fig. 9 shows the initial and deformed views at the edge of the chip for gap height of 0.65 cm. Interaction between the fluid and the structures was observed during the process. The edge of the imitated chip deformed due to continuous fluid flow from the inlet gate. The upward deformation at the edge is shown in Fig. 9d. In addition, the fluid flow was found to be nearly stable at the upper and lower streams. This caused a small pressure difference between both streams. Thus, no obvious deformation was observed at the middle region of chip. Fig. 10 shows the initial and deformed views of the package for gap height of 0.4 cm. The decrease of gap height caused greater flow resistance at the lower stream. Faster flow was observed at the top of the chip, as illustrated in Fig. 10b. As a result, the unstable flow caused downward deformation at the middle region. Deformation was also caused by the unbalanced force acting on the chip, as clearly shown in Fig. 10d. Meanwhile, only slight deformation was found at the edge of chip for gap height of 0.4 cm. FSI modelling was performed in the present study. Fig. 11 presents the FSI simulation results from FLUENT and ABAQUS codes. The flow front advancement is presented in the left column, whereas the deformation of the structure is shown in the right column. The deformation of the structure was viewed from the top and at the front. In the ABAQUS column, U represents displacement during the filling process. The imitated chip began to deform around the edge at 0.2 s filling time from the first interaction. Continuous flow from the inlet covered nearly 25% of the chip at 0.6 s. The fluid totally 50–80% of the chip at 1.0–1.6 s filling time. Thus, the downward deformation of the chip around the middle region became evident at the front view observation of the chip at 1.2 and 1.6 s (Fig. 11). 6.3. Stress analysis The FSI modelling technique is capable of handling the prediction and simulation of complicated geometry in the structural analysis. In the actual experiment and in the industry, the stress of the structures during FSI is difficult to determine, especially for miniaturised IC packaging. Therefore, this technique is important for continuous improvement and for investigation of microelectronic reliability problems. Fig. 12 shows the von Mises stress
Fig. 12. Von Mises stress of the imitated chip.
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the joint between the imitated chip and the bumps. In actual moulded packaging, improper process control could lead to unintended occurrences such as overstress, serious deformation, and the chip can be ‘swept away’ [23] in the packaging. Therefore, the FSI phenomenon during encapsulation for miniaturised, thinned chip, and 3D packaging and integration should be considered in the process. 6.4. Void formation
Fig. 13. Air traps phenomenon at gap height 0.4 cm (113.13 kPa).
Fig. 14. The flow mechanism at gap height 0.65 cm (113.13 kPa).
of the structures during the filling process. The fluid flow into the cavity subjected force upon the structure and induced stress. According to the simulation, stress distribution varied according to the fluid force. At 2.0 s, maximum stress was concentrated at
Air traps, EMC moisture content, and improper process control and design of IC package are factors that normally cause void formation during the encapsulation process. The mechanism of air traps during the experiment was visualised in the present study. This phenomenon is presented in Fig. 13 for the height of 0.4 cm. As shown in Fig. 13a, faster flow front was identified at upper stream. Although the flow front completely covered the imitated chip, the space beneath the chip was still not completely filled (Fig. 13b). Flow resistance through the small gap height was greater compared to that in the space on top of the chip. Fig. 13c shows the chip being completely covered by fluid. However, the space underneath the chip was still not completely filled. This was due to an air trap when the fluid reached the free region, as shown in Fig. 13d. Encapsulation process was also carried out for the gap height of 0.65 cm. Fig. 14 shows the flow mechanism during the completion of the filling process. The results show that the increase in gap height eliminated void formation and unbalanced flow front. This is unlike the phenomenon observed at the gap height of 0.4 cm (Fig. 13). The flow on top of the chip was slightly faster than the flow underneath, as illustrated in Fig. 14a and b. When the fluid began to fill the free region, the space beneath the chip was nearly full of fluid. This filling mechanism reduced the chances of air traps below the chip and diminished the undesired defect in the package. In addition, the effect of different pressures on air traps during the encapsulation process was also considered. Fig. 15 shows the effect of pressure on void formation for the gap heights of 0.4 and 0.65 cm. In the present experiment, increase in pressure effectively minimised air traps. As depicted in Fig. 15b, the air traps were reduced by nearly 50%. However, increase in pressure showed no air traps for the gap height of 0.65 cm (Fig. 15c and d), where the EMC flow through the gap freely and filled the top and bottom spaces of chip compared with Fig. 15a and b. Therefore, proper process control and packaging design are crucial to improve the reliability of IC packages. 6.5. Application of FSI in IC packaging In this section, an IC package (9 mm 9 mm 0.7 mm) with silicon chip (5 mm 5 mm 0.25 mm) and perimeter arrange-
Fig. 15. Air traps beneath the imitated chip with gap height of 0.4 cm at (a) 70.76 kPa and (b) 161.14 kPa; absence of air traps in the imitated chip with gap height of 0.65 cm at (c) 70.76 kPa and (d) 161.14 kPa.
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Fig. 16. FLUENT boundary conditions and meshed model.
for predicting the relationship between viscosity and the degree of polymerisation, which is expressed as follows:
Table 2 EMC material properties [10]. Castro–Macosko model parameters B (kPa s) Tb (K)
ag C1 C2
3.81E7 5230 0.17 1.03 1.50
Kamal model parameters m1 m2 A1 (1/s) A2 (1/s) E1 E2
1.21 1.57 33.53E3 30.54E6 7161 8589
ment of SnPb solder bumps was considered for the FSI investigation. Fig. 16 shows the boundary conditions and meshed model for the FLUENT solver. The diameter of the solder bump was 250 lm and the standoff height was 150 lm. The mould, silicon chip, and solder bumps were defined as wall boundaries. The inlet of the mould was located opposite to the outlet vents. The sizes of the inlet and the outlet were 2.2 mm 0.2 mm and 2.2 mm 0.1 mm, respectively. The model was meshed with 328,561 tetrahedral elements. During the encapsulation, the mould temperature was set as 170 °C. The inlet pressure was set at 1 MPa and pre-heated temperature of 90 °C for EMC. In FSI modelling, the FLUENT software was utilised to handle fluid flow analysis during the encapsulation. EMC was assumed to be a generalised Newtonian fluid (GNF). The viscosity behaviour of EMC was described by the Castro–Macosko model [10,17,24,25]
gðT; c_ Þ ¼
g0 ðTÞ 1þ
1n
g0 c_ s
ag
C1 þC2 a
ag a
ð8Þ
with
g0 ðTÞ ¼ B exp
Tb T
ð9Þ
where B is an exponential-fitted constant, Tb is a temperature fittedconstant, n is the power law index, g0 is the zero-shear viscosity, and s is the parameter that describes the transition region between zero-shear rate and the power law region of the viscosity curve. The Kamal’s equation [10,17,24,25] is integrated with the Castro–Macosko model in this study. The rate of chemical conversion of the compound is predicted as follows:
da ¼ ðk1 þ k2 am1 Þð1 aÞm2 dt E1 K 1 ¼ A1 exp T E2 K 2 ¼ A2 exp T
Fig. 17. ABAQUS meshed model and fixed boundary.
ð10Þ
ð11Þ
ð12Þ
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Table 3 Mechanical properties of silicon chip and solder bump.
7. Deformation and stress on the structures
Parameter
Silicon chip
Solder bump
Elastic modulus, E (GPa) Poisson ratio, m Solid density, qs (kg/m3)
100 0.3 2329
25 0.4 7500
where a is the conversion, A1 and A2 are Arrhenius pre-exponential factors, E1 and E2 are the activation energies, m and n are the reaction orders, and T is the absolute temperature. The Castro–Macosko model with curing kinetics was written into suitable UDFs and incorporated with FLUENT during the simulation. The properties of EMC materials used for the moulded packaging are summarised in Table 2. Fig. 17 shows the meshed coupled region for structural analysis. In the encapsulation, the rigid substrate was fixed and clamped properly [23] in the mould cavity. Thus, the substrate effect was neglected during the simulation. The fixed boundary was set at the bottom of the solder bumps. Similarly, several basic assumptions were made in the analyses as previously mentioned in Section 5.2. Table 3 summarises the mechanical properties for the structural analysis.
Fig. 18 illustrates the FSI simulation results for moulded packaging at different filling times. FLUENT predicted the flow front advancement of EMC. ABAQUS calculated the deformation of the silicon chip and solder bumps. The filled and unfilled regions of EMC were clearly labelled in the FLUENT result. In the FSI simulation, forces induced from EMC caused the deformation of the structures (chip and solder bumps). As shown in Fig. 18, the first interaction between EMC and the structures occurred at 0.5 s. Deformation was observed at the edge of the silicon chip. Continuous EMC feeding to the cavity resulted in unstable flow front on top and underneath the chip. This phenomenon was observed at filling times of 1.0 and 1.5 s. EMC flow experienced resistance while passing through space beneath the chip. Unbalanced flow at upper (on top of the chip) and lower (underneath of chip) streams resulted in unstable forces acting on the structures. Thus, the chip deformed at the middle region with no support of solder bumps at filling time of 1.0–2.0 s. The solder bumps were subjected to compression force during the encapsulation process and induced stress upon their structure. The von Mises stress of the solder bumps at various filling stages is presented in Fig. 19.
Fig. 18. FSI of moulded packaging for FLUENT (flow front advancement) and ABAQUS (displacement, unit: mm).
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Fig. 19. Von Mises stress of the silicon chip and bumps at different filling time.
Fig. 20. Void position and cross-sectional view beneath the chip.
8. Void in the package Unintended void in the package might lead to reduction of package reliability. Thus, unintended void was also investigated in the moulded package during the encapsulation process. Fig. 20 shows the position of the void and the cross-sectional view at selected locations (solder bump number 5 and centre of the package). As shown in Fig. 20, the void was formed at the end region and beneath the chip, closer to the outlet gate. This occurrence has been discussed in Section 6.4. The elimination of the void in the package could be achieved by the optimised inlet gate design [26]. 9. Conclusion The encapsulation process on the scaled-up prototype that emulates the IC package was investigated through experiment and FSI simulation. The foci of the experiment were encapsulation phenomena, such as fluid/structure interaction, and the mechanism of the void formation. Deformation of the imitated chip was investigated for gap heights of 0.4 and 0.65 cm. Results show that edge and the middle regions of chip deformed due to continuous force induced by the fluid, as well as pressure differences between upper and lower streams. The experiment and simulation results
were well validated. The air trap mechanism was studied at gap heights of 0.4 and 0.65 cm. Results show that increase of pressure significantly reduced air traps for packages with gap height h = 0.4 cm. Therefore, the present experiment provided better understanding and visualisation of the FSI phenomenon and airtrap mechanisms during encapsulation. Furthermore, the simulation technique yield realistic predictions on the flow front, structural deformation, and stress to help resolve the FSI issue in the actual packaging process. Acknowledgements The authors would like to thank the Ministry of Higher Education Malaysia for the financial support for this research work and PhD scholarship program. The technical support of D. Ramdan is also greatly acknowledged. References [1] Tu KN. Reliability challenges in 3D IC packaging technology. Microelectron Reliab 2010;51(3):517–23. [2] Lau JH. TSV manufacturing yield and hidden costs for 3D IC integration. In: Electronic components and technology conference; 2010. p. 1031–42.
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[3] Reddy AMK, Han R, Gupta M. Numerical and experimental investigation of microchip encapsulation. J Reinf Plast Compos 1998;17(1):70–93. [4] Islam N, Darveaux R, Jimarez M, Sy H, Jung BY, Gim JY, Jung YS, Hwang TK, Choi SC, Mendoza L. Molded flip chip – FCMBGA. In: International conference and exhibition on device packaging, IMAPS, Scottsdale, Arizona; March 2008. [5] Liu F, Wang YP, Chai K, Her TD. Characterization of molded underfill material for flip chip ball grid array packages. In: Electronic components and technology conference; 2001. [6] Kooi CC, Yan CY, Rudge VS, Lim SS, Then E. Underfilling flip chip packages with transfer molding technologies. Electron Pack Technol Conf 2004:625–9. [7] Chen KM. Comparing the impacts of the capillary and the molded underfill process on the reliability of the flip chip BGA. IEEE Trans Compon Pack Technol 2008;31(3):586–91. [8] Jung BY, Gim JY, Yoo M, Kim JD, Lee CH. Study of FCMBGA with low CTE core substrate. Electron Compon Technol Conf 2009:301–4. [9] Lin Y, Shi FG. Package design and material selection optimization for overmolded flip chip packaging. IEEE Trans Adv Pack 2006;29(3):525–32. [10] Nguyen L, Quentin C, Lee W, Bayyuk S, Bidstrup-Allen SA, Wang S-T. Computational modeling and validation of the encapsulation of plastic packages by transfer molding. J Electron Pack 2000;122:138–46. [11] Abdullah MK, Abdullah MZ, Kamarudin S, Ariff ZM. Study of flow visualization in stacked-chip scale packages (S-CSP). Int Commun Heat Mass Transfer 2007;34(7):820–8. [12] Khor CY, Abdullah MK, Abdullah MZ, Abdul Mujeebu M, Ramdan D, Majid MFMA, et al. Effect of vertical stacking dies on flow behavior of epoxy molding compound during encapsulation of stacked-chip scale packages. Heat Mass Transfer 2010;46(11–12):1315–25. [13] Chang RY, Yang WH, Hwang SJ, Su F. Three-dimensional modelling of mold filling in microelectronics encapsulation process. IEEE Trans Compon Pack Technol 2004;27(1):200–9. [14] Bae DH, Lee MC, Lee ES, Yun HC, Lim JC, Kim IB. Simulation of encapsulation process for BGA type semi-conducting microchip. J Ind Eng Chem 2003;9(2):188–92.
[15] Wang H, Zhou H, Zhang Y, Li D. Stabilized filling simulation of microchip encapsulation process. Microelectron Eng 2010;87(12):2602–9. [16] Jong WR, Chen YR, Kuo TH. Wire density in CAE analysis of high pin-count IC packages: simulation and verification. Int Commun Heat Mass Transfer 2005;32:1350–9. [17] Teng S-Y, Hwang S-J. Simulations and experiments of three-dimensional paddle shift for IC packaging. Microelectron Eng 2008;85(1):115–25. [18] Khor CY, Abdullah MZ, Che Ani F. Study on the fluid/structure interaction at different inlet pressures in molded packaging. Microelectron Eng. 2011;88:3182–94. [19] Modelling multiphase flow. FLUENT documentation. Chapter 23. [20] Chen RS, Tseng SC, Wan CS. Effects of solder joint structure and shape on thermal reliability of plastic ball grid array package. Int J Adv Manuf Technol 2006;27:677–87. [21] Piet JG. Schreurs, fatigue damage in solder joints. WCCM V Fifth world congress on computational mechanics, Vienna, Austria; July 7–12, 2002. [22] Kim J-W, Kim D-G, Jung S-B. Investigations of the test parameters and bump structures in the shear test of flip chip solder bump. Thin Solid Films 2006;504:405–9. [23] Zhang Z, Wong CP. Recent advances in flip chip underfill: materials, process, and reliability. IEEE Trans Adv Pack 2004;27:515–23. [24] Khor CY, Abdullah MZ, Abdullah MK, Mujeebu MA, Ramdan D, Majid MFMA, et al. Numerical analysis on the effects of different inlet gates and gap heights in TQFP encapsulation process. Int J Heat Mass Transfer 2011;54:1861–70. [25] Pei CC, Hwang SJ. Three-dimensional paddle shift modeling for IC packaging. J Electron Pack 2005;127(3):324–34. [26] Lee MW, Jung WK, Sohn ES, Lee JY, Hwang CH, Lee CH. A study on the rheological characterization and flow modelling of molded underfill (MUF) for optimized void elimination design. Electron Compon Technol Conf 2008:382–8.
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Investigation of the fluid/structure interaction phenomenon in IC packaging C.Y. Khor ⇑, M.Z. Abdullah, H.J. Tony Tan, W.C. Leong, D. Ramdan School of Mechanical Engineering, Universiti Sains Malaysia, Engineering Campus, 14300 Nibong Tebal, Penang, Malaysia
a r t i c l e
i n f o
Article history: Received 16 July 2011 Received in revised form 14 September 2011 Accepted 14 September 2011 Available online 2 October 2011
a b s t r a c t In the present study, experiment and simulation studies were conducted on the fluid/structure interaction (FSI) analysis of integrated circuit (IC) packaging. The visualisation of FSI phenomenon in the actual package is difficult due to limitations of package size, available equipment, and the high cost of the experimental setup. However, the experimental data are necessary to validate the simulation results in the FSI analysis of IC packaging. Scaled-up package size was fabricated to emulate the encapsulation of IC packaging and to study the effects of FSI phenomenon in the moulded package. The interaction between the fluid and the structure was observed. The deformation of the imitated chip was studied experimentally. The air-trap mechanism that occurred during the experiment is also presented in this paper. Simulation technique was utilised to validate the experimental result and to describe the physics of FSI. The predicted flow front was validated well by the experiment. Hence, the virtual modelling technique was proven to be excellent in handling this problem. The study also extends FSI modelling in actual-size packaging. Ó 2011 Elsevier Ltd. All rights reserved.
1. Introduction The trend of integrated circuit (IC) packaging is toward miniaturisation. Modern ICs are designed to be very thin, with high memory capacity, and with improved performance for various applications in electronic devices. To accomplish these characteristics, engineers, package designers, and researchers place continuous efforts in research. The use of the thinned silicon chip and the solder bump has enabled the IC package to be miniaturised with high interconnectivity. The thinned chip has also facilitated three-dimensional (3D) packaging [1] and 3D integration [2] technology in microelectronic technology. With the rapid development of IC packaging technology, reliability is a main issue in the manufacturing process. To maintain reliability and quality, IC encapsulation technology is widely used to protect the silicon chip, solder bumps, wire bonds, lead frame, and paddle from the hazardous environment. In this technology, an epoxy moulding compound (EMC) is applied to the structures (chip and solder bumps), causing deformation. The structures become subjected to stress that may induce unintended defects. Hence, packaging reliability is reduced. Numerical and experimental investigations on microchip encapsulation were carried out by Reddy et al. [3] to solve the paddle shift problem. They developed an analytical model for paddle shift predictions. In addition, their study also reported on the effect of cavity thickness. Islam et al. [4] discussed the concept of flip-chip (FCMBGA) using moulding
⇑ Corresponding author. Tel.: +60 195637283. E-mail address: [email protected] (C.Y. Khor). 0026-2714/$ - see front matter Ó 2011 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2011.09.013
compound to enhance packaging reliability. The application of moulding compound improved the warpage and reduced the package size. Reliability of passive components and solder joints was also increased. No cracks were found on the package. Moreover, Liu et al. [5] carried out an investigation on the effect of moulded underfill material to package reliability. The moulding material was found to be excellent for the transfer process of moulded underfill. This process minimised packaging time and improved package reliability. The application of transfer moulding on the matrix array flip-chip underfill process was reported by Kooi et al. [6]. They found that over-moulded packages yield better reliability without any crack at the mould corner. Chen [7] compared conventional underfill and moulded underfill package through impact testing. Solder bumps, low-K chip, bump stress, and package co-planarity and reliability were considered. Stress improvements of 58.3%, 8.4%, and 41.8% were found for the solder bumps, chip, and coplanar of the moulded package, respectively. Chen also reported that moulded underfill packaging was applicable to large die and large packaging sizes with low-K chip, as well as all kinds of bump compositions. The vacuumed transfer moulding of FCMBGA with low CTE core substrate encapsulation was studied by Jung et al. [8]. The method effectively eliminated void in the package. The stress threshold of the package was also improved by using a low coefficient of thermal expansion substrate with the low-K device package. Moreover, optimisations of the overmoulded flip-chip package-on-package (PoP) design and material selection were studied by Lin and Shi [9] using finite element method (FEM). Virtual modelling is a significant method for the simulation and improvement of IC packaging. Modelling tools such as PLICE-CAD
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Nomenclature A1, A2 B C1, C2 CP E1, E2 E F ~ g k K1, K2 m1, m2 n p T t Tb u v
pre-exponential factors, 1/s exponential-fitted constant, Pa s fitting constant specific heat, J/kg K activation energies, K elastic modulus, GPa front advancement parameter gravitational acceleration, m/s2 thermal conductivity, W/m K rate parameters described by an Arrhenius temperature dependency, 1/s constants for the reaction order power law index pressure, Pa temperature, K time, s temperature-fitted constant, K fluid velocity component in x-direction, mm/s fluid velocity component in y-direction, mm/s
[10], FORTRAN [11], FLUENT [12], C-MOLD [13,14], and Moldex3D [15] have been utilised for continuous improvement in various types of IC packages. Computer aided engineering (CAE) and FEM-based software have also assisted the research for wire bonding [16] and paddle shift [17] enhancements during the encapsulation process. Therefore, implementation of virtual modelling in the microelectronic industry contributes to the better understanding of encapsulation and enhancement to IC packages. In the present study, experiment and fluid/structure interaction (FSI) simulation are carried out on the imitation of the IC package. The simulation technique is also applied for the actual size of the moulded packaging. FLUENT 6.3.26, ABAQUS 6.9, and MpCCI are used for the modelling of the FSI phenomenon [18] in the encapsulation process. In the actual packaging, EMC fluid behaviour is modelled by the Castro–Macosko model with curing effect. Appropriate user-defined functions (UDFs) are written and incorporated into the FLUENT analysis. The volume of fluid (VOF) is applied for flow front tracking during the process. During real-time FSI simulation, MpCCI is used to transfer the forces induced during the encapsulation process (FLUENT) to ABAQUS for simultaneous structural analysis. The present experiment and virtual modelling technique in moulded packaging should provide reliable predictions and better understanding of the IC encapsulation process.
2. Problem description The small IC package and non-transparent packaging mould used in the actual encapsulation process causes difficulties in visualisation of the FSI phenomenon. FSI also occurs in the encapsulation of wire-bonding package, as extensively reported in available literature. The deformation of the wire bond is normally observed from the top view of the package. However, the visualisation of FSI in the moulded flip-chip package is more complicated than the wire-bonding package. The horizontal position of the chip complicates FSI visualisation. The chip is also thin and tiny in package size. The best method for visualisation of FSI is through cross-sectional and side views of the mould. Investigation can also be conducted using simulation tools. Therefore, a transparent and scaled-up mould was fabricated to emulate the moulded package with silicon chip, solder bumps, and substrate for the encapsulation process, as illustrated in Fig. 1. Two different gap heights (h = 0.4 and 0.65 cm) were considered to enable the better visualisation of
w x, y, z
fluid velocity component in z-direction, mm/s Cartesian coordinates
Greek symbols a conversion of reaction agel degree of cure at gel DH exothermic heat of polymerisation, J//kg g viscosity, Pa s g0 zero shear rate viscosity, Pa s q density, kg/m3 q solid density, kg/m3 $s r recoverable stresses, Pa s shear stress, Pa c_ shear rate, 1/s s parameter that describes the transition region between zero shear rates and the power law region of the viscosity curve, Pa m Poisson ratio
Fig. 1. Scale model of IC package.
FSI, fluid flow and air trap phenomenon in the experimental work. The virtual modelling technique using finite volume (FV) and finite element (FE) codes was utilised for the FSI analysis. 3. Governing equations In virtual modelling, the finite volume method (FVM)-based software (FLUENT) was used for the fluid analysis, whereas FEMbased software (ABAQUS) was used for the structural calculation. Three-dimensional incompressible flow transport equations (FLUENT) i.e., continuity (conservation of mass), Navier–Stokes, and Newtonian fluids equations are given below: Continuity equation:
@u @ v @w þ ¼0 þ @x @y @z
ð1Þ
Navier–Stokes equation: x-direction
@u @u @u @u 1 @p þu þv þw ¼ @t @x @y @z q @x @ @u @ @u @ @u þ þ þ g g g @x @x @y @y @z @z ð2Þ y-direction
@v @v @v @v 1 @p þu þv þw ¼ @t @x @y @z q @y @ @v @ @v @ @v þ g g g þ þ @x @y @z @x @y @z ð3Þ
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z-direction
@w @w @w @w 1 @p þu þv þw ¼ @t @x @y @z q @w @ @w @ @w @ @w þ þ þ g g g @x @x @y @y @z @z
$ @~ u þ~ u:r~ u ¼ r r þqs~ g qs @t
243
ð7Þ
where qs is the density of solid, ~ u is the velocity of solid in x, y and z $ axis, r is the recoverable stresses, and ~ g is the gravitational acceleration.
ð4Þ 4. Experimental setup
Newtonian fluid equation:
s g¼ _ c
ð5Þ
where s is the shear stress and c_ is the strain rate. The VOF model was utilised for flow front tracking during encapsulation. In the model, F specifies the fraction of the cell’s volume occupied by liquid. Here, F takes the value 1 (F = 1) in cells containing only resin, the value 0 (F = 0) in cells void of resin, and the value between 0 and 1 (0 < F < 1) in ‘interface’ cells (referred as the resin melt front). The equation for melt front over time is governed by the following transport equation:
dF @F @F @F @F ¼ þu þv þw dt @t @t @t @t
( ) @2F @2F @2F ¼0 þ þ @x2 @y2 @z2
ð6Þ
Moreover, the following momentum equation was used in FEM (ABAQUS) for solving the structural deformation:
(a) Actual
Fig. 2 depicts the actual diagram and schematics of the experimental setup. Test fluid with constant viscosity of 4 Pa s and density of 1067 kg/m3 was utilised as a fluid medium. The servomotor illustrated in Fig. 2 controlled system delivery of the test fluid into the mould. The system was tested to obtain constant pressures (70.76 kPa, 113.13 kPa, and 161.14 kPa) for the experiment. The FSI process during encapsulation was recorded using a camera and was processed by computer. The detailed and exploded views of the mould are presented in Fig. 3. The mould was fabricated from transparent Perspex for better visualisation. The material used for the imitated chip was a thin sheet of plastic. Scale model of the IC package with different gap heights were built and labelled as shown in Fig. 4. The dimensions of the cavity were 9 cm 4.5 cm 1.5 cm. The thickness of the imitated substrate was 0.5 cm. The dimensions of the imitated chip were 7 cm 3.5 cm 0.02 cm. The gap heights (h) were 0.65 and
(b) Schemaatic diiagrram
Fig. 2. (a) Actual diagram and (b) schematics of the experimental setup.
Fig. 3. (a) Detailed and (b) exploded views of the mould.
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Imitated chip
Imitated bump
Imitated substrate
Elastic modulus, E (GPa) Poisson ratio, m Solid density, qs (kg/m3)
1.571
213
2.7
0.37 1180
0.29 7710
0.375 1170
(a) h = 0.65cm tions of structures were calculated simultaneously. The structures (chip, bumps, and substrate) were defined as the coupled regions in FSI simulation. FLUENT was used to solve the fluid flow modelling by simulating the physic of flow front that filled the cavity. ABAQUS was used to calculate the displacement and von Mises stress during the encapsulation process.
(b) h = 0.40cm
5.1. FLUENT modelling
Fig. 4. Detailed view of imitated bumps, chip, and substrate with different gap heights (h).
0.4 cm. The present experimental work only focused on the interaction between the fluid and the structures. Thus, temperature effect was not considered in the experiment. 5. FSI simulation modelling The basic idea of FSI modelling in the present study is the coupling of FVM- and FEM-based software in conducting the fluid and structural analyses. During FSI analysis, the transformation of analysis generated from the FLUENT 6.3.26 to ABAQUS 6.9 was performed using MpCCI. Real-time data were transferred from one program to the other. The forces induced from the fluid acting on the structures were directly solved by ABAQUS. Thus, the deforma-
In the FLUENT analysis, the 3D model was built according to the dimensions of the package fabricated in the experimental work. The model was meshed with a total of 92,986 tetrahedral elements. Fig. 5 illustrates the (a) boundary conditions and (b) meshed model of the imitated IC package. The surface of the mould, substrate, chip, and bump were defined as wall boundaries under no-slip condition. Temperature effect was not considered in the experiment. Therefore, this process was assumed to be isothermal during the simulation and was set at room temperature. FSI phenomenon focused on the fluid feeding into the cavity until the ‘final’ stage, which is before the plunger is retracted from the fluid cylinder. The boundary and initial conditions are as follows: @p (a) On wall: u ¼ v ¼ w ¼ 0; T ¼ T w ; @n ¼ 0, @u @v @w @T (b) On centre line: @z ¼ @z ¼ @z ¼ @z ¼ 0,
Fig. 5. Boundary conditions and meshed model of the imitated IC package.
Fig. 6. Structural meshed model.
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245
Fig. 7. Experimental (70.76 kPa) and simulation (FLUENT) results.
(c) On melt front: p = 0, (d) At inlet: p = pin(x, y, z); T = Tin.
Flow front advancement, x (cm)
10 Experiment FLUENT
8
Upper stream
6
Lower stream
4
2
0 0.0
0.5
1.0
1.5
2.0
2.5
Time (s) Fig. 8. Flow front advancement (at upper stream and lower stream) versus filling time.
In the analysis, the VOF model was used to solve the modelling of fluid and air during the filling process. Fluid and air were defined as the phases in the analysis. The viscosity of the fluid varied with shear rate, as calculated by Eq. (5). The VOF model was used to solve a set of single momentum equations. This set was shared by the fluid and the volume fractions of each of the fluids in the computational cell, which were tracked throughout the domain [19]. A second-order upwind scheme was used for the momentum and volume fraction equations. A SIMPLE algorithm was applied for pressure–velocity calculation. Implicit solution and time-dependent formulation were considered for the volume fraction in each time step. The optimum time step size of 0.001 was utilised in the analysis. The simulation took around 8 h to complete one case. An Intel Core i3 processor with i3-540, 3.07 GHz, and 3.24 GB of RAM was used for the simulation. 5.2. ABAQUS modelling Fig. 6 shows the model of coupled regions (imitated chip, bumps, and substrate) for structural analysis. The 3D meshed mod-
Fig. 9. Initial and deformed view at the edge of imitated chip for 0.65 cm (113.13 kPa).
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Fig. 10. Initial and slightly deformed view at the centre of imitated chip for 0.4 cm (70.76 kPa).
el was generated using hexahedral with sweep method by ABAQUS 6.9. The mechanical aspects were considered. Thus, the structures
of the coupled regions were defined as deformable in the analysis. In the experiment, the structures of chip and bumps were properly
Fig. 11. FSI simulation for gap height of 0.4 cm.
C.Y. Khor et al. / Microelectronics Reliability 52 (2012) 241–252
positioned on the imitated substrate in the cavity. Therefore, the fixed boundary condition was set at the bottom surface of the imitated substrate, as depicted in Fig. 6a and b. In addition, some basic assumptions were considered in the FEM analyses [20] for simplification purpose. Elastic behaviour was taken as homogeneous and isotropic in the structures of chip and bump [21,22]. The solder pad effect was neglected, where the solder pad was not considered in the scaled-up model. The bump and chip were perfectly bonded in the experiment work, where the bonding between chip and bumps assumed to be fully adhesive. The temperature effect on the structures was not considered in the experimental work. Therefore, thermal effect on the creep and fracture behaviour was not considered in the present modelling. The mechanical properties of emulated chip, bump, and substrate are summarised in Table 1. 6. Results and discussion 6.1. Model validation The experiments were conducted for a scaled-up moulded package prototype. The filling process of the viscous fluid into the cavity was recorded in front of the transparent mould. FSI simulation was also performed on the imitated package with gap height of 0.4 cm, as presented in Fig. 7. The flow front advancement of the simulation results was compared with the experimental results. The results show that flow front predictions from the simulation code had nearly the same profile with the experimental results at different filling times. The flow front advancement measurements are plotted in Fig. 8 for upper (top of chip) and lower (beneath of chip) streams. Both streams showed an approximately identical trend with only 5.16% and 6.33% average discrepancy. Therefore, the present modelling techniques yield reliable predictions in handling moulded packaging problem. 6.2. Fluid/structure interaction (FSI) The FSI phenomenon was investigated through experimental work for gap heights of 0.4 and 0.65 cm at different pressures. Only
247
selected results are presented in this paper. Fig. 9 shows the initial and deformed views at the edge of the chip for gap height of 0.65 cm. Interaction between the fluid and the structures was observed during the process. The edge of the imitated chip deformed due to continuous fluid flow from the inlet gate. The upward deformation at the edge is shown in Fig. 9d. In addition, the fluid flow was found to be nearly stable at the upper and lower streams. This caused a small pressure difference between both streams. Thus, no obvious deformation was observed at the middle region of chip. Fig. 10 shows the initial and deformed views of the package for gap height of 0.4 cm. The decrease of gap height caused greater flow resistance at the lower stream. Faster flow was observed at the top of the chip, as illustrated in Fig. 10b. As a result, the unstable flow caused downward deformation at the middle region. Deformation was also caused by the unbalanced force acting on the chip, as clearly shown in Fig. 10d. Meanwhile, only slight deformation was found at the edge of chip for gap height of 0.4 cm. FSI modelling was performed in the present study. Fig. 11 presents the FSI simulation results from FLUENT and ABAQUS codes. The flow front advancement is presented in the left column, whereas the deformation of the structure is shown in the right column. The deformation of the structure was viewed from the top and at the front. In the ABAQUS column, U represents displacement during the filling process. The imitated chip began to deform around the edge at 0.2 s filling time from the first interaction. Continuous flow from the inlet covered nearly 25% of the chip at 0.6 s. The fluid totally 50–80% of the chip at 1.0–1.6 s filling time. Thus, the downward deformation of the chip around the middle region became evident at the front view observation of the chip at 1.2 and 1.6 s (Fig. 11). 6.3. Stress analysis The FSI modelling technique is capable of handling the prediction and simulation of complicated geometry in the structural analysis. In the actual experiment and in the industry, the stress of the structures during FSI is difficult to determine, especially for miniaturised IC packaging. Therefore, this technique is important for continuous improvement and for investigation of microelectronic reliability problems. Fig. 12 shows the von Mises stress
Fig. 12. Von Mises stress of the imitated chip.
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the joint between the imitated chip and the bumps. In actual moulded packaging, improper process control could lead to unintended occurrences such as overstress, serious deformation, and the chip can be ‘swept away’ [23] in the packaging. Therefore, the FSI phenomenon during encapsulation for miniaturised, thinned chip, and 3D packaging and integration should be considered in the process. 6.4. Void formation
Fig. 13. Air traps phenomenon at gap height 0.4 cm (113.13 kPa).
Fig. 14. The flow mechanism at gap height 0.65 cm (113.13 kPa).
of the structures during the filling process. The fluid flow into the cavity subjected force upon the structure and induced stress. According to the simulation, stress distribution varied according to the fluid force. At 2.0 s, maximum stress was concentrated at
Air traps, EMC moisture content, and improper process control and design of IC package are factors that normally cause void formation during the encapsulation process. The mechanism of air traps during the experiment was visualised in the present study. This phenomenon is presented in Fig. 13 for the height of 0.4 cm. As shown in Fig. 13a, faster flow front was identified at upper stream. Although the flow front completely covered the imitated chip, the space beneath the chip was still not completely filled (Fig. 13b). Flow resistance through the small gap height was greater compared to that in the space on top of the chip. Fig. 13c shows the chip being completely covered by fluid. However, the space underneath the chip was still not completely filled. This was due to an air trap when the fluid reached the free region, as shown in Fig. 13d. Encapsulation process was also carried out for the gap height of 0.65 cm. Fig. 14 shows the flow mechanism during the completion of the filling process. The results show that the increase in gap height eliminated void formation and unbalanced flow front. This is unlike the phenomenon observed at the gap height of 0.4 cm (Fig. 13). The flow on top of the chip was slightly faster than the flow underneath, as illustrated in Fig. 14a and b. When the fluid began to fill the free region, the space beneath the chip was nearly full of fluid. This filling mechanism reduced the chances of air traps below the chip and diminished the undesired defect in the package. In addition, the effect of different pressures on air traps during the encapsulation process was also considered. Fig. 15 shows the effect of pressure on void formation for the gap heights of 0.4 and 0.65 cm. In the present experiment, increase in pressure effectively minimised air traps. As depicted in Fig. 15b, the air traps were reduced by nearly 50%. However, increase in pressure showed no air traps for the gap height of 0.65 cm (Fig. 15c and d), where the EMC flow through the gap freely and filled the top and bottom spaces of chip compared with Fig. 15a and b. Therefore, proper process control and packaging design are crucial to improve the reliability of IC packages. 6.5. Application of FSI in IC packaging In this section, an IC package (9 mm 9 mm 0.7 mm) with silicon chip (5 mm 5 mm 0.25 mm) and perimeter arrange-
Fig. 15. Air traps beneath the imitated chip with gap height of 0.4 cm at (a) 70.76 kPa and (b) 161.14 kPa; absence of air traps in the imitated chip with gap height of 0.65 cm at (c) 70.76 kPa and (d) 161.14 kPa.
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Fig. 16. FLUENT boundary conditions and meshed model.
for predicting the relationship between viscosity and the degree of polymerisation, which is expressed as follows:
Table 2 EMC material properties [10]. Castro–Macosko model parameters B (kPa s) Tb (K)
ag C1 C2
3.81E7 5230 0.17 1.03 1.50
Kamal model parameters m1 m2 A1 (1/s) A2 (1/s) E1 E2
1.21 1.57 33.53E3 30.54E6 7161 8589
ment of SnPb solder bumps was considered for the FSI investigation. Fig. 16 shows the boundary conditions and meshed model for the FLUENT solver. The diameter of the solder bump was 250 lm and the standoff height was 150 lm. The mould, silicon chip, and solder bumps were defined as wall boundaries. The inlet of the mould was located opposite to the outlet vents. The sizes of the inlet and the outlet were 2.2 mm 0.2 mm and 2.2 mm 0.1 mm, respectively. The model was meshed with 328,561 tetrahedral elements. During the encapsulation, the mould temperature was set as 170 °C. The inlet pressure was set at 1 MPa and pre-heated temperature of 90 °C for EMC. In FSI modelling, the FLUENT software was utilised to handle fluid flow analysis during the encapsulation. EMC was assumed to be a generalised Newtonian fluid (GNF). The viscosity behaviour of EMC was described by the Castro–Macosko model [10,17,24,25]
gðT; c_ Þ ¼
g0 ðTÞ 1þ
1n
g0 c_ s
ag
C1 þC2 a
ag a
ð8Þ
with
g0 ðTÞ ¼ B exp
Tb T
ð9Þ
where B is an exponential-fitted constant, Tb is a temperature fittedconstant, n is the power law index, g0 is the zero-shear viscosity, and s is the parameter that describes the transition region between zero-shear rate and the power law region of the viscosity curve. The Kamal’s equation [10,17,24,25] is integrated with the Castro–Macosko model in this study. The rate of chemical conversion of the compound is predicted as follows:
da ¼ ðk1 þ k2 am1 Þð1 aÞm2 dt E1 K 1 ¼ A1 exp T E2 K 2 ¼ A2 exp T
Fig. 17. ABAQUS meshed model and fixed boundary.
ð10Þ
ð11Þ
ð12Þ
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Table 3 Mechanical properties of silicon chip and solder bump.
7. Deformation and stress on the structures
Parameter
Silicon chip
Solder bump
Elastic modulus, E (GPa) Poisson ratio, m Solid density, qs (kg/m3)
100 0.3 2329
25 0.4 7500
where a is the conversion, A1 and A2 are Arrhenius pre-exponential factors, E1 and E2 are the activation energies, m and n are the reaction orders, and T is the absolute temperature. The Castro–Macosko model with curing kinetics was written into suitable UDFs and incorporated with FLUENT during the simulation. The properties of EMC materials used for the moulded packaging are summarised in Table 2. Fig. 17 shows the meshed coupled region for structural analysis. In the encapsulation, the rigid substrate was fixed and clamped properly [23] in the mould cavity. Thus, the substrate effect was neglected during the simulation. The fixed boundary was set at the bottom of the solder bumps. Similarly, several basic assumptions were made in the analyses as previously mentioned in Section 5.2. Table 3 summarises the mechanical properties for the structural analysis.
Fig. 18 illustrates the FSI simulation results for moulded packaging at different filling times. FLUENT predicted the flow front advancement of EMC. ABAQUS calculated the deformation of the silicon chip and solder bumps. The filled and unfilled regions of EMC were clearly labelled in the FLUENT result. In the FSI simulation, forces induced from EMC caused the deformation of the structures (chip and solder bumps). As shown in Fig. 18, the first interaction between EMC and the structures occurred at 0.5 s. Deformation was observed at the edge of the silicon chip. Continuous EMC feeding to the cavity resulted in unstable flow front on top and underneath the chip. This phenomenon was observed at filling times of 1.0 and 1.5 s. EMC flow experienced resistance while passing through space beneath the chip. Unbalanced flow at upper (on top of the chip) and lower (underneath of chip) streams resulted in unstable forces acting on the structures. Thus, the chip deformed at the middle region with no support of solder bumps at filling time of 1.0–2.0 s. The solder bumps were subjected to compression force during the encapsulation process and induced stress upon their structure. The von Mises stress of the solder bumps at various filling stages is presented in Fig. 19.
Fig. 18. FSI of moulded packaging for FLUENT (flow front advancement) and ABAQUS (displacement, unit: mm).
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Fig. 19. Von Mises stress of the silicon chip and bumps at different filling time.
Fig. 20. Void position and cross-sectional view beneath the chip.
8. Void in the package Unintended void in the package might lead to reduction of package reliability. Thus, unintended void was also investigated in the moulded package during the encapsulation process. Fig. 20 shows the position of the void and the cross-sectional view at selected locations (solder bump number 5 and centre of the package). As shown in Fig. 20, the void was formed at the end region and beneath the chip, closer to the outlet gate. This occurrence has been discussed in Section 6.4. The elimination of the void in the package could be achieved by the optimised inlet gate design [26]. 9. Conclusion The encapsulation process on the scaled-up prototype that emulates the IC package was investigated through experiment and FSI simulation. The foci of the experiment were encapsulation phenomena, such as fluid/structure interaction, and the mechanism of the void formation. Deformation of the imitated chip was investigated for gap heights of 0.4 and 0.65 cm. Results show that edge and the middle regions of chip deformed due to continuous force induced by the fluid, as well as pressure differences between upper and lower streams. The experiment and simulation results
were well validated. The air trap mechanism was studied at gap heights of 0.4 and 0.65 cm. Results show that increase of pressure significantly reduced air traps for packages with gap height h = 0.4 cm. Therefore, the present experiment provided better understanding and visualisation of the FSI phenomenon and airtrap mechanisms during encapsulation. Furthermore, the simulation technique yield realistic predictions on the flow front, structural deformation, and stress to help resolve the FSI issue in the actual packaging process. Acknowledgements The authors would like to thank the Ministry of Higher Education Malaysia for the financial support for this research work and PhD scholarship program. The technical support of D. Ramdan is also greatly acknowledged. References [1] Tu KN. Reliability challenges in 3D IC packaging technology. Microelectron Reliab 2010;51(3):517–23. [2] Lau JH. TSV manufacturing yield and hidden costs for 3D IC integration. In: Electronic components and technology conference; 2010. p. 1031–42.
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