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Sub-30 nm via interconnects fabricated using directed self-assembly
Microelectronic Engineering 110 (2013) 152–155
Contents lists available at SciVerse ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Sub-30 nm via interconnects fabricated using directed self-assembly Hirokazu Kato ⇑, Yuriko Seino, Hiroki Yonemitsu, Hironobu Sato, Masahiro Kanno, Katsutoshi Kobayashi, Ayako Kawanishi, Tsubasa Imamura, Mitsuhiro Omura, Naofumi Nakamura, Tsukasa Azuma Center for Semiconductor Research & Development, Toshiba Corporation, 8 Shinsugita-cho, Isogo-ku, Yokohama, Kanagawa 235-8522, Japan
a r t i c l e
i n f o
Article history: Available online 16 March 2013 Keywords: Directed self-assembly Graphoepitaxy Block copolymer PS-b-PMMA Hole shrink
a b s t r a c t In this study, sub-30 nm via interconnects were fabricated and fully integrated on a 300 mm wafer using directed self-assembly lithography (DSAL). They were tested electrically and initial test results are reported. DSAL was applied on the via layer, which is connecting between the lower metal layer and the upper metal layer. A trilayer resist process was utilized for preparing a guiding pattern of graphoepitaxy. Exposure dose of 193 nm immersion lithography was centered so that via size in spin-on-carbon (SOC) was just 70 nm in diameter. Poly (styrene-block-methyl methacrylate) (PS-b-PMMA) block copolymer (BCP) solution was applied on the SOC pre-pattern, and then annealed in N2 atmosphere to induce micro-phase separation. PMMA domain was finally transferred into a dTEOS oxide film as a via hole. Via interconnects were fabricated using tungsten deposition followed by CMP. Intra-wafer variation of via resistance was measured and the correlation between the via resistance and the via dimension was discussed. Ó 2013 Elsevier B.V. All rights reserved.
1. Introduction
2. Experiments
Since 193 nm immersion lithography has reached its optical resolution limit, various double patterning techniques have been used in semiconductor device manufacturing. However, they have disadvantages with respect to process complexity and higher cost of ownership (COO). Single patterning techniques have also been anticipated and investigated. One of the most rigorously developed techniques is extreme ultraviolet lithography (EUVL). However, source power still needs to be improved in order to meet the throughput requirement for semiconductor device manufacturing [1]. Recently DSAL has been paid more attention to as an alternative patterning technique to realize sublithographic patterning. DSAL may be used in conjunction with existing lithography techniques [2]. In order to utilize DSAL for semiconductor device manufacturing, DSAL needs to be integrated with existing semiconductor manufacturing process. Large area defectivity is critical as well [3]. In this work, sub-30 nm via interconnects were fabricated on a 300 mm wafer using DSAL and electrically tested. Although an electrical test requires fully integrated wafers, it is more device-oriented and it enables evaluation of total process performance including dimension control, overlay, defectivity, metallization and etc. In this paper, the fabrication process and the electrical test results are reported.
The whole process in sample preparation is illustrated in Fig. 1. A dTEOS oxide film was deposited using a CVD method on a freshly prepared 300 mm Si wafer. On top of the dTEOS oxide film, trilayer resist stack which is consisting of spin-on carbon (SOC), spin-on glass (SOG) and chemically amplified positive tone resist was deposited. The resist film was exposed using 193 nm immersion lithography tool to form trench patterns. The trench patterns in the resist film were transferred to the SOG film by reactive ion etching (RIE) using fluorocarbon gas chemistry and then transferred to SOC film by RIE using O2 gas chemistry. The trench patterns in the SOC film is finally transferred to the dTEOS oxide film by RIE using fluorocarbon gas chemistry. The lower metal layer was fabricated by tungsten deposition into the trench pattern in the dTEOS oxide film followed by chemical mechanical polishing (CMP) as shown in Fig. 1(a). The fabrication process of via patterns using DSAL is as follows. A 150-nm-thick dTEOS oxide film was deposited using a CVD method on the lower metal layer. On top of the dTEOS film, trilayer resist stack which is consisting of 160-nm-thick spin-on carbon (SOC), 45-nm-thick spin-on glass (SOG) and 120-nm-thick chemically amplified positive tone resist was deposited. The important point is that the post-applied-bake condition of SOC was 350 °C for 60 s, which made the SOC highly cross-linked and gave very high thermal stability. The top resist film was exposed using 193 nm immersion lithography tool to form via patterns as shown in Fig. 1(b). The via exposure was aligned to the
⇑ Corresponding author. E-mail address: [email protected] (H. Kato). 0167-9317/$ - see front matter Ó 2013 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.mee.2013.03.025
H. Kato et al. / Microelectronic Engineering 110 (2013) 152–155
153
Fig. 1. Schematic illustrations of sample preparation (a) lower metal layer, (b) via exposure, (c) trilayer RIE, (d) BCP coating and annealing, (e) dry development, (f) dTEOS oxide RIE, (g) tungsten deposition and CMP and (h) upper metal layer.
Fig. 2. CD and intra-wafer CD uniformity on each process step.
lower metal layer. The via patterns in the resist film were transferred to the SOG film by reactive ion etching (RIE) using fluorocarbon gas chemistry and then transferred to SOC film by RIE using O2 gas chemistry as shown in Fig. 1(c). The via dimension target in SOC film was 70 nm in diameter, which was determined based on our previous study to give maximum hole open yield [4]. In this study, SOC was used as a guiding pattern of graphoepitaxy. SOC guiding patterns have three major advantages over resist guiding patterns. The first advantage is thermal stability. As the post-applied-bake temperature of SOC is much higher than the annealing temperature of block copolymer (BCP), SOC shows
very good thermal stability on BCP annealing. On the other hand, the glass transition temperature (Tg) of the resist film for 193 nm immersion lithography is around 200 °C. The resist pattern profile may degrade during BCP annealing. Special process is required for the resist guiding patterns to obtain enough thermal stability [5]. The second advantage is the depth of guiding patterns. As the SOC guiding patterns are fabricated using O2 RIE and the etching selectivity of SOG over SOC is very high, it is easy to prepare deep SOC guiding patterns. Moreover, the depth is easily adjustable by changing the spin speed of SOC coating. On the other hand, the maximum depth of the resist guiding patterns is limited by
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H. Kato et al. / Microelectronic Engineering 110 (2013) 152–155
depth-of-focus (DOF) of the via exposure. In addition, adjusting the depth of resist guiding patterns is often difficult, because the resist thickness is chosen from maxima and minima of CD swing curve. The third advantage is the profile of the guiding pattern. The sidewall of the SOC guiding pattern is very straight and steep, which gives uniform diameter along the depth of the guiding pattern. However, the sidewall of the resist guiding pattern is often tapered and has standing waves. A propylene glycol methyl ether acetate (PGMEA) solution of poly (styrene-block-methyl methacrylate) (PS-b-PMMA) block copolymer (BCP) (80.5 kg/mol 34.5 kg/mol) was applied on the SOC guiding pattern followed by thermal annealing at 240 °C for 60 s in N2 atmosphere. Micro-phase separation resulted in PMMA domain in the center of the guiding pattern surrounded by PS domain as shown in Fig. 1(d). It must be noted that PS domain exists at the bottom of the guiding pattern. According to our previous study [4], the thickness of the bottom PS is about 10 nm. Although wet development is reported to be a promising option to remove only the central PMMA domain [2,4], dry development was employed in this study. O2 gas chemistry was employed to remove the central PMMA domain and the bottom part of PS domain in one step as shown in Fig. 1(e). The via patterns were finally transferred into the dTEOS oxide film by RIE using fluorocarbon gas chemistry as shown in Fig. 1(f). Processing time on Fig. 1(e) was optimized to give the best electrical yield without losing via shrink achieved by DSAL. Achieving high RIE selectivity between PS and PMMA is a key technique in order to leave enough PS film thickness for the following dTEOS oxide RIE. Yamashita has conducted basic research on this process step [6]. The via layer was fabricated by tungsten deposition into the via pattern in the dTEOS oxide film followed by CMP as shown in Fig. 1(g). Another dTEOS oxide film and trilayer resist stack were deposited. The top resist film was exposed using 193 nm immersion lithography tool to form trench patterns. The trench exposure was aligned to the via layer. As DSAL could have impact on alignment marks, alignment degradation is a concern for full integration of DSAL. Overlay errors were compared between with and without DSAL and we verified that overlay deterioration was negligible. The trench patterns were transferred into the dTEOS oxide film by RIE. The upper metal layer was fabricated by tungsten deposition into the trench pattern in the dTEOS oxide film followed by CMP as shown in Fig. 1(h). Finally via resistance was measured on the whole wafer.
Fig. 3. TEM images of via chain (a) with DSAL and (b) without DSAL.
3. Results and discussion We measured critical dimension (CD) along the wafer diameter on each process step by CD-SEM (Hitachi CG4000). Those results are shown in Fig. 2 along with top-down images. Via dimension after trilayer RIE was 68.6 ± 3.4 nm in diameter, which was very close to target dimension (70 nm). Via dimension after dTEOS oxide RIE was 25.8 ± 2.1 nm with DSAL and 55.3 ± 3.3 nm without DSAL. Via shrinkage achieved by DSAL was nearly 30 nm. CD is very useful for collecting statistical data, there is often some offset between CD and physical dimension. The physical dimension needs to be determined separately. TEM images of via chain are shown in Fig. 3. Via dimension is less than 30 nm from top to bottom with DSAL. Intra-wafer variation of single via resistance is shown in Fig. 4. In the ideal case, via resistance is proportional to inverse square of via diameter. Mean via resistance increased by a factor of 6.22 with DSAL, which corresponds to via size shrinkage by a factor of 2.49. Based on Fig. 3, the via diameter shrank by a factor of 2.42 at top and 2.55 at bottom. There is a good correlation between via resistance and via diameter. In order to find the root cause of via resistance variation, via diameter and via resistance are compared along the wafer
Fig. 4. Intra-wafer variation of single via resistance.
diameter in Fig. 5. Via resistance is relatively low on the extreme wafer edge position ( 5 and 5) and relatively high on the neighbor position ( 4 and 4) irrespective of whether DSAL was applied or not. As regards intra-wafer variation of single via resistance, correlation between via diameter and via resistance is small. As CD is based on secondary electron signal image, it is more reflecting via dimension at top. This implies the cross-sectional via profile may vary depending on the position on the wafer. Intra-wafer uniformity of tungsten deposition and CMP is another possible cause. Further investigation is necessary. Process integration is a key enabler of DSAL.
H. Kato et al. / Microelectronic Engineering 110 (2013) 152–155
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Fig. 5. Via diameter and via resistance variation along wafer diameter.
4. Conclusions
References
DSAL was fully integrated with semiconductor manufacturing process. Sub-30 nm via interconnects were successfully fabricated using DSAL. Electrical evaluation of sub-30 nm via interconnects was demonstrated across the 300 mm wafer. The mean via resistance across the 300 mm wafer increased proportionally to inverse square of via diameter by using DSAL. But there was small correlation between via diameter and via resistance. Process integration is a key enabler of DSAL.
[1] R. Moors, V. Banine, G. Swinkels, F. Wortel, J. Micro/Nanolithogr. MEMS MOEMS 11 (2) (2012) 021102. [2] B. Rathsack, M. Somervell, J. Hooge, M. Muramatsu, K. Tanouchi, T. Kitano, E. Nishimura, K. Yatsuda, S. Nagahara, I. Hiroyuki, K. Akai, T. Hayakawa, Proc. SPIE 8323 (2012). [3] C. Bencher, H. Yi, J. Zhou, M. Cai, J. Smith, L. Miao, O. Montal, S. Blitshtein, A. Lavia, K. Dotan, H. Dai, J.Y. Cheng, D.P. Sanders, M. Tjio, S. Holmes, Proc. SPIE 8323 (2012). [4] Y. Seino, H. Yonemitsu, H. Sato, M. Kanno, H. Kato, K. Kobayashi, A. Kawanishi, T. Azuma, M. Muramatsu, S. Nagahra, T. Kitano, T. Toshima, Proc. SPIE 8323 (2012). [5] J.Y. Cheng, D.P. Sanders, H.D. Truong, S. Harrer, A. Friz, S. Holmes, M. Colburn, W.D. Hinsberg, ACS Nano 4 (8) (2010) 4815–4823. [6] F. Yamashita, E. Nishimura, K. Yatsuda, H. Mochiki, J. Bannister, Proc. SPIE 8328 (2012).
Acknowledgment The authors would like to thank Tokyo Electron Ltd. and Tokyo Ohka Kogyo Co., Ltd. for their support in this work.
Contents lists available at SciVerse ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Sub-30 nm via interconnects fabricated using directed self-assembly Hirokazu Kato ⇑, Yuriko Seino, Hiroki Yonemitsu, Hironobu Sato, Masahiro Kanno, Katsutoshi Kobayashi, Ayako Kawanishi, Tsubasa Imamura, Mitsuhiro Omura, Naofumi Nakamura, Tsukasa Azuma Center for Semiconductor Research & Development, Toshiba Corporation, 8 Shinsugita-cho, Isogo-ku, Yokohama, Kanagawa 235-8522, Japan
a r t i c l e
i n f o
Article history: Available online 16 March 2013 Keywords: Directed self-assembly Graphoepitaxy Block copolymer PS-b-PMMA Hole shrink
a b s t r a c t In this study, sub-30 nm via interconnects were fabricated and fully integrated on a 300 mm wafer using directed self-assembly lithography (DSAL). They were tested electrically and initial test results are reported. DSAL was applied on the via layer, which is connecting between the lower metal layer and the upper metal layer. A trilayer resist process was utilized for preparing a guiding pattern of graphoepitaxy. Exposure dose of 193 nm immersion lithography was centered so that via size in spin-on-carbon (SOC) was just 70 nm in diameter. Poly (styrene-block-methyl methacrylate) (PS-b-PMMA) block copolymer (BCP) solution was applied on the SOC pre-pattern, and then annealed in N2 atmosphere to induce micro-phase separation. PMMA domain was finally transferred into a dTEOS oxide film as a via hole. Via interconnects were fabricated using tungsten deposition followed by CMP. Intra-wafer variation of via resistance was measured and the correlation between the via resistance and the via dimension was discussed. Ó 2013 Elsevier B.V. All rights reserved.
1. Introduction
2. Experiments
Since 193 nm immersion lithography has reached its optical resolution limit, various double patterning techniques have been used in semiconductor device manufacturing. However, they have disadvantages with respect to process complexity and higher cost of ownership (COO). Single patterning techniques have also been anticipated and investigated. One of the most rigorously developed techniques is extreme ultraviolet lithography (EUVL). However, source power still needs to be improved in order to meet the throughput requirement for semiconductor device manufacturing [1]. Recently DSAL has been paid more attention to as an alternative patterning technique to realize sublithographic patterning. DSAL may be used in conjunction with existing lithography techniques [2]. In order to utilize DSAL for semiconductor device manufacturing, DSAL needs to be integrated with existing semiconductor manufacturing process. Large area defectivity is critical as well [3]. In this work, sub-30 nm via interconnects were fabricated on a 300 mm wafer using DSAL and electrically tested. Although an electrical test requires fully integrated wafers, it is more device-oriented and it enables evaluation of total process performance including dimension control, overlay, defectivity, metallization and etc. In this paper, the fabrication process and the electrical test results are reported.
The whole process in sample preparation is illustrated in Fig. 1. A dTEOS oxide film was deposited using a CVD method on a freshly prepared 300 mm Si wafer. On top of the dTEOS oxide film, trilayer resist stack which is consisting of spin-on carbon (SOC), spin-on glass (SOG) and chemically amplified positive tone resist was deposited. The resist film was exposed using 193 nm immersion lithography tool to form trench patterns. The trench patterns in the resist film were transferred to the SOG film by reactive ion etching (RIE) using fluorocarbon gas chemistry and then transferred to SOC film by RIE using O2 gas chemistry. The trench patterns in the SOC film is finally transferred to the dTEOS oxide film by RIE using fluorocarbon gas chemistry. The lower metal layer was fabricated by tungsten deposition into the trench pattern in the dTEOS oxide film followed by chemical mechanical polishing (CMP) as shown in Fig. 1(a). The fabrication process of via patterns using DSAL is as follows. A 150-nm-thick dTEOS oxide film was deposited using a CVD method on the lower metal layer. On top of the dTEOS film, trilayer resist stack which is consisting of 160-nm-thick spin-on carbon (SOC), 45-nm-thick spin-on glass (SOG) and 120-nm-thick chemically amplified positive tone resist was deposited. The important point is that the post-applied-bake condition of SOC was 350 °C for 60 s, which made the SOC highly cross-linked and gave very high thermal stability. The top resist film was exposed using 193 nm immersion lithography tool to form via patterns as shown in Fig. 1(b). The via exposure was aligned to the
⇑ Corresponding author. E-mail address: [email protected] (H. Kato). 0167-9317/$ - see front matter Ó 2013 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.mee.2013.03.025
H. Kato et al. / Microelectronic Engineering 110 (2013) 152–155
153
Fig. 1. Schematic illustrations of sample preparation (a) lower metal layer, (b) via exposure, (c) trilayer RIE, (d) BCP coating and annealing, (e) dry development, (f) dTEOS oxide RIE, (g) tungsten deposition and CMP and (h) upper metal layer.
Fig. 2. CD and intra-wafer CD uniformity on each process step.
lower metal layer. The via patterns in the resist film were transferred to the SOG film by reactive ion etching (RIE) using fluorocarbon gas chemistry and then transferred to SOC film by RIE using O2 gas chemistry as shown in Fig. 1(c). The via dimension target in SOC film was 70 nm in diameter, which was determined based on our previous study to give maximum hole open yield [4]. In this study, SOC was used as a guiding pattern of graphoepitaxy. SOC guiding patterns have three major advantages over resist guiding patterns. The first advantage is thermal stability. As the post-applied-bake temperature of SOC is much higher than the annealing temperature of block copolymer (BCP), SOC shows
very good thermal stability on BCP annealing. On the other hand, the glass transition temperature (Tg) of the resist film for 193 nm immersion lithography is around 200 °C. The resist pattern profile may degrade during BCP annealing. Special process is required for the resist guiding patterns to obtain enough thermal stability [5]. The second advantage is the depth of guiding patterns. As the SOC guiding patterns are fabricated using O2 RIE and the etching selectivity of SOG over SOC is very high, it is easy to prepare deep SOC guiding patterns. Moreover, the depth is easily adjustable by changing the spin speed of SOC coating. On the other hand, the maximum depth of the resist guiding patterns is limited by
154
H. Kato et al. / Microelectronic Engineering 110 (2013) 152–155
depth-of-focus (DOF) of the via exposure. In addition, adjusting the depth of resist guiding patterns is often difficult, because the resist thickness is chosen from maxima and minima of CD swing curve. The third advantage is the profile of the guiding pattern. The sidewall of the SOC guiding pattern is very straight and steep, which gives uniform diameter along the depth of the guiding pattern. However, the sidewall of the resist guiding pattern is often tapered and has standing waves. A propylene glycol methyl ether acetate (PGMEA) solution of poly (styrene-block-methyl methacrylate) (PS-b-PMMA) block copolymer (BCP) (80.5 kg/mol 34.5 kg/mol) was applied on the SOC guiding pattern followed by thermal annealing at 240 °C for 60 s in N2 atmosphere. Micro-phase separation resulted in PMMA domain in the center of the guiding pattern surrounded by PS domain as shown in Fig. 1(d). It must be noted that PS domain exists at the bottom of the guiding pattern. According to our previous study [4], the thickness of the bottom PS is about 10 nm. Although wet development is reported to be a promising option to remove only the central PMMA domain [2,4], dry development was employed in this study. O2 gas chemistry was employed to remove the central PMMA domain and the bottom part of PS domain in one step as shown in Fig. 1(e). The via patterns were finally transferred into the dTEOS oxide film by RIE using fluorocarbon gas chemistry as shown in Fig. 1(f). Processing time on Fig. 1(e) was optimized to give the best electrical yield without losing via shrink achieved by DSAL. Achieving high RIE selectivity between PS and PMMA is a key technique in order to leave enough PS film thickness for the following dTEOS oxide RIE. Yamashita has conducted basic research on this process step [6]. The via layer was fabricated by tungsten deposition into the via pattern in the dTEOS oxide film followed by CMP as shown in Fig. 1(g). Another dTEOS oxide film and trilayer resist stack were deposited. The top resist film was exposed using 193 nm immersion lithography tool to form trench patterns. The trench exposure was aligned to the via layer. As DSAL could have impact on alignment marks, alignment degradation is a concern for full integration of DSAL. Overlay errors were compared between with and without DSAL and we verified that overlay deterioration was negligible. The trench patterns were transferred into the dTEOS oxide film by RIE. The upper metal layer was fabricated by tungsten deposition into the trench pattern in the dTEOS oxide film followed by CMP as shown in Fig. 1(h). Finally via resistance was measured on the whole wafer.
Fig. 3. TEM images of via chain (a) with DSAL and (b) without DSAL.
3. Results and discussion We measured critical dimension (CD) along the wafer diameter on each process step by CD-SEM (Hitachi CG4000). Those results are shown in Fig. 2 along with top-down images. Via dimension after trilayer RIE was 68.6 ± 3.4 nm in diameter, which was very close to target dimension (70 nm). Via dimension after dTEOS oxide RIE was 25.8 ± 2.1 nm with DSAL and 55.3 ± 3.3 nm without DSAL. Via shrinkage achieved by DSAL was nearly 30 nm. CD is very useful for collecting statistical data, there is often some offset between CD and physical dimension. The physical dimension needs to be determined separately. TEM images of via chain are shown in Fig. 3. Via dimension is less than 30 nm from top to bottom with DSAL. Intra-wafer variation of single via resistance is shown in Fig. 4. In the ideal case, via resistance is proportional to inverse square of via diameter. Mean via resistance increased by a factor of 6.22 with DSAL, which corresponds to via size shrinkage by a factor of 2.49. Based on Fig. 3, the via diameter shrank by a factor of 2.42 at top and 2.55 at bottom. There is a good correlation between via resistance and via diameter. In order to find the root cause of via resistance variation, via diameter and via resistance are compared along the wafer
Fig. 4. Intra-wafer variation of single via resistance.
diameter in Fig. 5. Via resistance is relatively low on the extreme wafer edge position ( 5 and 5) and relatively high on the neighbor position ( 4 and 4) irrespective of whether DSAL was applied or not. As regards intra-wafer variation of single via resistance, correlation between via diameter and via resistance is small. As CD is based on secondary electron signal image, it is more reflecting via dimension at top. This implies the cross-sectional via profile may vary depending on the position on the wafer. Intra-wafer uniformity of tungsten deposition and CMP is another possible cause. Further investigation is necessary. Process integration is a key enabler of DSAL.
H. Kato et al. / Microelectronic Engineering 110 (2013) 152–155
155
Fig. 5. Via diameter and via resistance variation along wafer diameter.
4. Conclusions
References
DSAL was fully integrated with semiconductor manufacturing process. Sub-30 nm via interconnects were successfully fabricated using DSAL. Electrical evaluation of sub-30 nm via interconnects was demonstrated across the 300 mm wafer. The mean via resistance across the 300 mm wafer increased proportionally to inverse square of via diameter by using DSAL. But there was small correlation between via diameter and via resistance. Process integration is a key enabler of DSAL.
[1] R. Moors, V. Banine, G. Swinkels, F. Wortel, J. Micro/Nanolithogr. MEMS MOEMS 11 (2) (2012) 021102. [2] B. Rathsack, M. Somervell, J. Hooge, M. Muramatsu, K. Tanouchi, T. Kitano, E. Nishimura, K. Yatsuda, S. Nagahara, I. Hiroyuki, K. Akai, T. Hayakawa, Proc. SPIE 8323 (2012). [3] C. Bencher, H. Yi, J. Zhou, M. Cai, J. Smith, L. Miao, O. Montal, S. Blitshtein, A. Lavia, K. Dotan, H. Dai, J.Y. Cheng, D.P. Sanders, M. Tjio, S. Holmes, Proc. SPIE 8323 (2012). [4] Y. Seino, H. Yonemitsu, H. Sato, M. Kanno, H. Kato, K. Kobayashi, A. Kawanishi, T. Azuma, M. Muramatsu, S. Nagahra, T. Kitano, T. Toshima, Proc. SPIE 8323 (2012). [5] J.Y. Cheng, D.P. Sanders, H.D. Truong, S. Harrer, A. Friz, S. Holmes, M. Colburn, W.D. Hinsberg, ACS Nano 4 (8) (2010) 4815–4823. [6] F. Yamashita, E. Nishimura, K. Yatsuda, H. Mochiki, J. Bannister, Proc. SPIE 8328 (2012).
Acknowledgment The authors would like to thank Tokyo Electron Ltd. and Tokyo Ohka Kogyo Co., Ltd. for their support in this work.