System on a chip (SoC) and design methodology challenges

ELSEVIER

Microelectronic

Engineering

54 (2000) IS-22 www.elsevier.nl/locate/mee

System on a Chip (SoC) and Design Methodology

Challenges

Joseph Bore1 STMicroelectronics,

850 rue Jean Monnet, BP 16, 38921 Crolles, France

1. INTRODUCTION System on a chip, while recently introduced [l], is becoming more and more a driver for development either for process or in Design Automation. This is due to the fact that the concept itself (though far from being applied in present products) is raising a lot of interesting problems yet to solve. System on a Chip (So0 is defined as “on a single chip co-location of sense, compute, control, store, communicate and actuate capabilities”. In the existing products, few of these capabilities are implemented and a lot of developments remains to be done to get the concept generalized and the corresponding products available on the shelf. We are going to review the main enabling factors of System on a Chip, the silicon core process evolution, the options necessary mostly for the interfaces to real word, the Design Automation and then to go to a conclusion.

devices, non volatile memories,...), or from the Micro Electra Mechanical (MEM) area [3] like inductors, high quality switches, loudspeakers (Figure 1). Additional technologies will appear in the coming years to give even more capabilities (magnetic memories, piezoresistive devices, thin film batteries,. .I 14, 51.

2. ENABLING FACTORS FOR SoC MANUFACTURING AND PRODUCTION

Figure 1: System on a Chip Implementation

From the above definition, SoC is built around a core (the central processing functions) in CMOS process for low cost and maximum complexity (multiprocessor system); the remaining functions depend on the application and define the extra cost associated with the basic CMOS process (in average up to 4 mask layers are necessary per added option) 121;they may be compatible with the CMOS process (sensors, switches,.. .), or need extra processing steps from the microelectronics field (power

SoC is leading to a new type of economical competition by the fact that it is potentially “the single chip” solution for the customer. This means that where several suppliers are sharing a market, only one will supply the SoC products. Consequently, the well known “time to market” constraint will be much more drastic for those missing their entry. Figure 2 represents schematically two very important (and simultaneous:) parameters playing a role in market penetration:

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-Time to market is a major parameter to address the whole market for a given product. Every delay in the entry will have (as shown on the figure) a significant decrease in the Serviceable Market. - The learning curve displays the decrease of cost while refinements for better yields are brought to the product in volume production. The two ingredients show how difficult the competition will be on SoC, and how important those two parameters are to high-end the Today, in consider. microprocessor business, Intel has succeeded in keeping control of those two parameters, killing completely competition by carefully adjusting the cost (tradeoff between profit and market capture). For Pentium III, in 1999, prices have been divided by 2 over a period of 5 months (starting at 800 $ per unit) [61.

Engineering

.W (2000)

1522

- complexity > 20.106 transistors, - including 8.106 in logic and 15.106 in SRAMs, - for an area of # 100 mm2. The new advanced processes will include improvements to reduce cross-talk and are targeted in 0.13 pm to reach 40 millions of gates with SILK dielectric isolation 171. An example of industrial roadmap (Figure 3) shows together with the CMOS process, the options availability to cover SOC needs. CD’wprn) 0.30

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3. PROCESS

Windows 2W-

Enabling

Product Life

Factors

EVOLUTION

CMOS process evolution is continuing similarly as in the past with some relevant differences: J a new generation of logic appears every 18 months, J the density increase ratio is close to 1.5, J the frequency increase ratio is close to 1.5. The 0.18 urn is presently in production with a capability shown below (Pentium III):

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No major breakthrough is seen during this time frame but continuous improvements are necessary in process, modeling, substrate The 100 manufacturing. material and nanometer critical dimension is associated with a gate thickness of 1 nanometer which is likely to raise difficult problems of reliability, gate currents and control (oxygen atoms in the SiO, gate thickness are today accounted in a single digit). Solutions, deviating from the “silicon oxide rule”, such as lantanum and hafnium oxides are under study (high are constant). Researchers dielectric confident in the feasibility of gate dielectrics in the 1 nm range but the solutions are likely to be brand new and need to be qualified. Device physics will be in a continuity and feasibility of early devices shows acceptable characteristics (Figure 4) as far as currents are concerned (saturation and leakage).

J. Bore1 I Microelectronic

Engineering

54 (2000)

1.5-22

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1.E.03 r, 1 E-04 1 E-05 1 E-06 r ,1 Q _D

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at L, = 105 nm Figure 5: Options on CMOS Core process

Process options will continue to keep compatibility with the CMOS digital process for design reasons (reuse of the CMOS digital libraries with every option). The merging of a given option will be product driven and flexibility of options usage is key. The SoC full process is shown in Figure 5 where the basic options available today are shown; they follow the structure of the SoC shown in Figure 1: - Information processing requires options @RAM, DRAM or non volatile). - Basic technologies extensions use Bipolar RF. - DMOS (Diffused MOS) and micromachining are shown. - The multifunction peripherals require VIP (Vertical Integrated Power in DMOS) and BCD options (Bipolar, CMOS and DMOS). - MEMS is the newcomer bringing added value to the basic process for a large range of peripherals based on mechanical or chemical properties of various add-on materials. They will have to be added on top of the siliconbased device in full process compatibility (limits can be seen as substrate coupling in case of RF, cost in assembly in case of optical interconnect.. .I.

4. ROADMAPS FOR OPTIONS Options to the core process begin to be so important for differentiated products that they are carefully planned at the same time as the process and as much as possible in concurrent development. It is to be expected that, with reference to the existing one, many additional options will appear, driven by application needs in the areas shown in Figure 6: - silicon-based options will bring more performance; - actuators and sensors will generalize their presence in SoC chips and MEMS will be a major player in that evolution (technology compatibility is often reached and MEMS are capitalizing on microelectronics processes); -thin film batteries may appear mandatory for such applications as smart cards where a high degree of protection is required (no access to the supply current); - the present bottleneck of interconnection delays can be addressed either though architectural constraints (maximum wire lengths constraints) or through future technologies such as intra chip optical communications.

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5. DEVICE AUTOMATION

Silicon based: RF, analog, DRAM, NV, ... Actuators & sensors:

Figure 6: Deep Submicron Forecasted options

CMOS

Process:

The present roadmaps address mostly the silicon based options because of the commonality of process with CMOS; the new fields mentioned in Figure 6 are still partly at research level (MEMS are the exception been have already products where manufactured in large quantities). Table 1 shows the roadmaps for DRAM, Bipolar and flash options. It is seen a delay between options and CMOS process ranging between one to two years depending on the specificity of the option development versus the core CMOS process. Table 1: CMOS Options Evolution 0.25

(Forecast) 0.18 0.12

CMOS digital CD (nm) DRAM ontion . date . cell size (um2) 1Mbit macrocell (mm? : V”, (Volt) Binolar ontion date F max (NPN) . MIM (Ff$m2) . inductor

1999 2.6 4.2 3.3

2000 0.87 1.68 1.8 I 3.3

2001 90 GHZ 2

2003 110 GHZ 4

Embeded flash option . date . cell size (um2)

1999 0.8

2001 0.7

2003 0.38 0.73 1.2 I 3.3

TBD

2003 0.5

SoC design automation will have to address complexity increase and functionality increase linked to CMOS and options evolution. Additionally there is a need to validate system specification before entering the design phase due to: - increasing difficulty due to complexity; - cost and delays associated with a redesign; -need to have a customer agreement at system level specification (feedback from the usage). Therefore there are more constraints on quality of specification definitions and validation at every level of the design phase (Figure 7). System specifications

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Figure 7: SoC Design Automation

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in 2005

5.1. Design methodology The design must be good at the first run; this means a single path from specification to PG tapes, that is to say an additional need of constraint propagation from high level down to layout which is based on system level constraints. At .system level, a virtual solution (understandable by the system customer) will allow to formalize the specifications in a way understood by the design flow (it could be a mixture of hardware and software or a pure software solution interfaced with the real world of sensors and actuators). Then the system design partitioning can

J. Bore1 I Microelectronic Engineering 54 (2000) 15-22

be completed with trade off specific to the application (speed, power consumption, reusability,. . .I and giving partitioning between software and hardware (expressed as functional for analog, MEMs, MOEMs,. . .). implementation (placement, Concurrent routing and timing closure) will achieve a single path to layout. Due to advanced mask processing techniques, a validation after mask processing will have to be done before going to manufacturing. All these steps need validation and test procedures should be implemented from system partitioning level, Specific items such as behavioral IP and dynamic libraries will help speeding up the design (behavioral IP) and making it close to full custom design (“dynamic library” generated on the fly for a specific product) 5.2. Process design gap Process development started in the early seventies and today we have a pretty good maturity of this process that changes only partially from one generation to the next (80% - 20% rule). The predictability of evolution is covered down to the 0.1 pm dimensions (for CMOS) and has given birth to the well known SIA roadmap (now ITRS). The continuation of the exponential growth of process capabilities is hardly met by design methodology evolution for many reasons: -the tools in Design Automation are not mature enough (versus process); -the tools in Design Automation are not covering all the design flow (from system level); - some tools are still to be developed and tools of virtual system (languages representation); - the “engineering” of the design solutions is weaker. This situation is shown in Figure 8 where the gap between process capability evolution (+ 60%/year) is constantly increasing. On the figure, are presented contributions to increase design efficiency in the short term:

Design Complexity (u. count linear)

I

I

95

96

97

Figure 8: Process/Design

98

99

2

Gap

- RTL to layout flow: continue to improve in moving to concurrent engineering between placement, routing and timing closure. - HW-SW design and partitioning: new solutions exist that must be fully engineered and matched to future needs (constraint propagation from system level). - IP reuse: there is a great potential (mostly in some generic fields of applications like single chips PC, disk drive circuits,...) to reuse functionalities that have been proven in earlier less complex designs (provided they can be reused at behavioral level to avoid permanent remapping on new process). - System level design where a partitioning can already be done taking into account application constraints (single processor, multiprocessor architectures, low power,. . .) and propagating these constraints along the design flow. Today a bottleneck in design performance is coming from the use of an ASIC flow mapping on a library of standard functions (a common library by construction is matching no specific application!). This ASIC flow being well engineered today would benefit of accepting constraint propagation and as mentioned earlier, mapping on a “dynamic library” of cells.

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5.3. The MEDEA EDA Roadmap In the frame of the MEDEA program (Micro-Electronics Development for European Applications), has been launched in 1998 an initiative to define an EDA roadmap as seen by the partners of this program and covering European needs. This work done in the Application Group of MEDEA included both semiconductor and system companies and led “the MEDEA Design to Automation Roadmap” (available at www.medea.org); a forum associated to the roadmap is accessible at www.medea.orgledaroadmap and allows people to interact and add their contributions. This organization was put in place with specialists contributing in the meetings and in the writing of the document, with the idea in mind that an EDA roadmap should be a living document with updates at least every year.

- IP reuse is far from being in place in current flows and should probably be revisited in association with the concept of dynamic libraries mentioned earlier. One new field of importance is the system validation level that could lead ultimately to a “system sign off’. This means that languages and dedicated developments should allow to describe virtually a system with capabilities of real world access (sensor and actuators 1 at a level where it allows to both: 01

00 Specification

2

Architectural Synthesis HW/SW codesign

PERF. EVALUATION

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1 DEBUGGERS

AUTOMATION

1

X-TALK

9

Distributed

10

Low Power Design Solutions

PROPERTY

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Low-cost Testing for SoC

INTERFACES

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CONSTRAINTS PROP.

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Design Environment

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ARCHITECTURE

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VERIF.

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VERIFICATION

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TOOLS

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1 TECHNO EVOLUTION Table 2: The MEDEA EDA Roadmap

SYNTHESIS

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CHECKING

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ANALOGUE

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RF

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IP Reuse Verification & Validation driven by functionality & System constraints

Packaging

LANGUAGE

C++ SPEC.

Parasitic Extraction

04 APPLIC.

MULTIPROCESSORS

Embedded SW Design

& RF

03

1 CO-SYNTHESIS

System to Gate HW Design Mixed Analogue/Digital

13

02

HIGH LEVEL LANG.

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IS-22

The main areas of improvement are summarized below in the various levels of designing: - specification and validation: use of several high level languages for an accurate description of the system and allowing cosimulation and synthesis (including analog); - architecture synthesis should handle multiprocessors on a single chip (cycle accurate); -hardware-software co-design is in the early phase of implementation; - back end design (from RTL to layout) has to move to fully concurrent design (between placement, routing and timing closure);

An example of the recommendations included in the 2nd release (2000) of the MEDEA design Automation Roadmap is given in Table 2.

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RF

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.I. Bore1 / Microelecrronic

_ validate the system with the (this means studying the usages, formal specifications,. . .I; -enter with a formal description flow so as to be implemented in an manner.

customer defining the EDA optimum

6. CONCLUSION Design automation is facing a difficult challenge: -move to system on a chip design capabilities, that is to say be able to handle higher level of description with a capability of virtual system representation, -better use silicon capabilities, what is not the case presently with the ASIC flow; this a global optimization capability means (architecture, algorithm, design style, silicon implementation) for specific applications (like telecoms using wireless and portability features that give strong constraints in system performance). Figure 9 shows how we are presently moving from an ASIC solution to a more silicon application type of design solution. This is becoming necessary even in the case where ratio microprocessors the of (performance/power consumption) shows clearly, in some cases, a poor use of silicon capabilities.

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Two examples are given below: - 960JT from Intel; 57 MIPS and 1.2 watt power consumption, -ARM 710 from ARM; 30 MIPS and 120 mwatt power consumption. The values in MIPS/watt are respectively 66 and 250 which depicts a 4x ratio. Some areas of applications are already moving in that direction for mostly two reasons: -because they address the mobility market (portable phones, digital assistants,. . .I and power consumption has to be minimized; - because they address the mass market and the carefully understanding of needs and habits is mandatory (knowledge of the usage). Therefore a preliminary definition of a product needs to be done with many customers through a virtual system allowing to understand the real need of the customer. It is obviously the next revolution following and overlapping the SoC revolution which is already on going (Figure 10).

Plalfwmr

Figure 10: From Evolution

Figure 9: From an ASIC Platform to a Silicon Application

Technology Platform

to Revolution

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REFERENCES

1. J. Borel, “Technologies for multimedia system on a chip”, keynote speech, ISSCC’97, Digest of Technical Papers, pp. 18-21. 2. International

Technology semiconductors, 1999, http://public.itrs.net.

Roadmap Editions

for at

3. M. R. Pinto, “Atoms to Applets: Building

system ICs in the 21”’ century”, keynote speech, ISSCC’2000, Digest of Technical Papers, pp. 26-30. 4. R. Scheuerlein et al, “A 10 ns read and

write non volatile memory using a magnetic tunnel junction and FET switch in each cell”, ISSCC’2000, paper TA 7-2, pp. 128-129. 5. C. Paz de Araujo

et al, “The Future Ferroelectric Memories”, ISSCC’2000, paper TP 16.3, pp. 268-269.

6. Microprocessor Report-Cahners, January

2000, p. 51. 7. Microprocessor

Report-Cahners, 14, Archive 5, May 2000.

Volume