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The VLSI package—an analytical review
World Abstracts on Microelectronics and Reliability features all flow from the desire to provide a constraint solver suitable for use in an "open" system, in which there are no restrictions on the form or order of the constraints. The algorithm presented meets these objectives while remaining reasonable in its use of storage and time. An extension to the class of constraints acceptable by the constraint solver is presented; the extension of the system to this added constraint class has yet to be done.
Wafer fabrication and process automation research at Stanford University. BRIAN K. REID, JOHN D. SHOTT and JAMES D. MEINDL. Solid St. Technol. 126 (July 1984). Two aspects of a Stanford University VLSI research program are highlighted in this article. The first is the development of in-house, fast turn-around, wafer fabrication capabilities which are readily accessible to local systems designers and device technologists. The second is the development of new computer systems to provide a higher degree of automation, measurement, and simulation in wafer fabrication. The computer systems work is keyed on a new computer language called Fable, which is intended for the specification of fabrication processes. The VLSI package--an analytical review. EDWARD T. LEWIS. IEEE Trans. Components Hybrids Mfg Technol. CHMT-7 (2), 197 (1984). Current very large-scale integrated (VLSI) chip packaging options, with a special emphasis on the various size and chip I/O complexity issues are reviewed, quantitatively. The two basic packaging options reviewed are the hermetic chip carrier (HCC) and the pin grid array (PGA). The impact that chip input/output (I/O) has on the "size" growth of packages as single chip enclosures, as well as that of chips themselves, is considered. It is shown that the HCC is inherently more area-efficient for almost any high I/O configured VLSI chip, especially if the chip size growth that must be anticipated is considered as l/O's of 400 are entertained. After quantitative considerations of discrete packaging options are exhausted, it is finally recommemded that a multichip VLSI module should be seriously considered as a more efficient packaging concept. This, however, requires some innovation directed toward the development of adequate prepackaged chip testing. This could be facilitated through the incorporation of physically testable I/O ports on the "passivated" VLSI chip; e.g. flip chip "bumps," tapeautomated bonding (TAB), or beam lead chip interconnects. Improving bond yields to metal package leads. DOUG DAY. Semiconductor Int. 90 (July 1984). The combination of an enhanced sensing mechanism with "table scrub" motion has helped alleviate the problems of bonding to plug-in style package leads.
587
the appropriate choice for material handling. It is shown that a flexible material handling system is cost effective.
Optimization of a photoresist process using statistical design of experiments. MICHAEL JOHNSON and KAREN LEE. Solid St. Technol. 281 (September 1984). Process optimization often requires hundreds of experiments. Statistical Design and Analysis of Experiments (SDE) can reduce the number of experiments by a factor of ten or more. While this method applies to any process, a photoresist process is used for our example. Various traditional and SDE approaches to optimization are described. The use of computer programs, some of which are available on personal computers, to evaluate the data is examined. SDE is not a substitute for good engineering; both are needed. Engineers and scientists often have a great deal of experience in process specifics but no knowledge of SDE. These subjects are an essential part of modern scientific literacy. Moisture control in hermetic leadless chip carders with silverepoxy die-attach adhesive. D. R. CARLEY, R. W. NEARHOOF and R. DENNING. RCA Rev. 45, 278 (1984). This paper describes package design and process changes in the development of an improved system for controlling internal watervapor levels below 5000 ppmv in hermetically-sealed leadless chip carriers with silver-epoxy attached silicon devices. It was shown by mass spectrometry that the silver-epoxy die-attach material releases water and unreacted monomers at about 300°C. Therefore, the high-temperature braze-seal design and process originally used in manufacturing was changed to a controlled-environment low-temperature seam-welded design. A high-temperature, pre-seal, furnace bake-out and epoxy cure process was also incorporated. Moisture levels measured for the new package and process are below the 1000ppmv level. The trials of wafer-scale integration. JACK F. MCDONALD, EDWIN H: ROGERS, KENNETH ROSE and ANDREW J. STECKL IEEE Spectrum 32 (October 1984). Although major technical problems have been overcome since WSI was first tried in the 1960s, commercial companies can't yet make it fly. Process control for semiconductor manufacturing. DAVID M. CAMPBELL and ZAHRA ARDEHALI. Semiconductor Int. 127 (June 1984). Today's semiconductor fabrication operations require automated process control capabilities, through the use of process control charts.
Emphasizing effluent gas scrubbing. PIETER BURGGRAAF.Semiconductor Int. 116 (June 1984). Success with the handling of effluent gases requires a thorough understanding of scrubber "science."
Advanced CMOS epitaxial processing for latch-up hardening and improved epilayer quality. JOHN OGAWA BORLAND and TOM DEACON. Solid St. Technol. 123 (August 1984). Use of silicon epitaxial wafers for advanced CMOS device processing has led to improved latch-up hardening. However, the heavily doped substrates used to improve latch-up hardening can also degrade epilayer quality. Improvements in epilayers have been achieved through the application of both pre- and post-epitaxy intrinsic gettering that activates the growth of oxygen related precipitates. In p+ (100) and n ÷ (100) wafers, epilayer minority carrier lifetimes were improved by as much as three orders of magnitude.
Flexible material handling automation in wafer fabrication. JAMES G. HARPER and Louis G. BAILEY.Solid St. Technol. 89 (July 1984). The relationship between the need for increased integration of electronic functions, chip cost, and the value of automation is developed. High yield is the requirement for economical production of integrated circuits and the factors which contribute to low yield are delineated. Particulate contamination is a prime cause of yield loss and a significant portion of this contamination is contributed by people. Automation can decrease the number of people and particles and can improve yield as well as productivity, cycle time, and also can reduce inventory. Due to the continuing change in wafer fabrication factories, automation which is flexible in nature is
New applications of tape bonding for high lead count devices. JAMES F. MARSHALL. Solid St. Technol. 175 (August 1984). Development work and use of tape automated bonding (TAB) have been accelerating due to the requirement for improved performance in the interconnection of complex VLSI devices. VHSIC speeds are forcing new approaches to packaging and interconnection. TAB offers a practical solution to many of these performance problems. TAB leads offer improved electrical, thermal and mechanical properties in addition to doubling the I/O density capability for perimeter pad configurations compared to conventional wirebonding. Furthermore, TAB technology can accommodate I/O pads anywhere on the surface of the device through the-
Polyimides in semiconductor manufacturing. RON ISCOFF.Semiconductor Int. 116 (October 1984). Polyimides are finding a broad, new range of applications in the manufacture of integrated circuits.
Wafer fabrication and process automation research at Stanford University. BRIAN K. REID, JOHN D. SHOTT and JAMES D. MEINDL. Solid St. Technol. 126 (July 1984). Two aspects of a Stanford University VLSI research program are highlighted in this article. The first is the development of in-house, fast turn-around, wafer fabrication capabilities which are readily accessible to local systems designers and device technologists. The second is the development of new computer systems to provide a higher degree of automation, measurement, and simulation in wafer fabrication. The computer systems work is keyed on a new computer language called Fable, which is intended for the specification of fabrication processes. The VLSI package--an analytical review. EDWARD T. LEWIS. IEEE Trans. Components Hybrids Mfg Technol. CHMT-7 (2), 197 (1984). Current very large-scale integrated (VLSI) chip packaging options, with a special emphasis on the various size and chip I/O complexity issues are reviewed, quantitatively. The two basic packaging options reviewed are the hermetic chip carrier (HCC) and the pin grid array (PGA). The impact that chip input/output (I/O) has on the "size" growth of packages as single chip enclosures, as well as that of chips themselves, is considered. It is shown that the HCC is inherently more area-efficient for almost any high I/O configured VLSI chip, especially if the chip size growth that must be anticipated is considered as l/O's of 400 are entertained. After quantitative considerations of discrete packaging options are exhausted, it is finally recommemded that a multichip VLSI module should be seriously considered as a more efficient packaging concept. This, however, requires some innovation directed toward the development of adequate prepackaged chip testing. This could be facilitated through the incorporation of physically testable I/O ports on the "passivated" VLSI chip; e.g. flip chip "bumps," tapeautomated bonding (TAB), or beam lead chip interconnects. Improving bond yields to metal package leads. DOUG DAY. Semiconductor Int. 90 (July 1984). The combination of an enhanced sensing mechanism with "table scrub" motion has helped alleviate the problems of bonding to plug-in style package leads.
587
the appropriate choice for material handling. It is shown that a flexible material handling system is cost effective.
Optimization of a photoresist process using statistical design of experiments. MICHAEL JOHNSON and KAREN LEE. Solid St. Technol. 281 (September 1984). Process optimization often requires hundreds of experiments. Statistical Design and Analysis of Experiments (SDE) can reduce the number of experiments by a factor of ten or more. While this method applies to any process, a photoresist process is used for our example. Various traditional and SDE approaches to optimization are described. The use of computer programs, some of which are available on personal computers, to evaluate the data is examined. SDE is not a substitute for good engineering; both are needed. Engineers and scientists often have a great deal of experience in process specifics but no knowledge of SDE. These subjects are an essential part of modern scientific literacy. Moisture control in hermetic leadless chip carders with silverepoxy die-attach adhesive. D. R. CARLEY, R. W. NEARHOOF and R. DENNING. RCA Rev. 45, 278 (1984). This paper describes package design and process changes in the development of an improved system for controlling internal watervapor levels below 5000 ppmv in hermetically-sealed leadless chip carriers with silver-epoxy attached silicon devices. It was shown by mass spectrometry that the silver-epoxy die-attach material releases water and unreacted monomers at about 300°C. Therefore, the high-temperature braze-seal design and process originally used in manufacturing was changed to a controlled-environment low-temperature seam-welded design. A high-temperature, pre-seal, furnace bake-out and epoxy cure process was also incorporated. Moisture levels measured for the new package and process are below the 1000ppmv level. The trials of wafer-scale integration. JACK F. MCDONALD, EDWIN H: ROGERS, KENNETH ROSE and ANDREW J. STECKL IEEE Spectrum 32 (October 1984). Although major technical problems have been overcome since WSI was first tried in the 1960s, commercial companies can't yet make it fly. Process control for semiconductor manufacturing. DAVID M. CAMPBELL and ZAHRA ARDEHALI. Semiconductor Int. 127 (June 1984). Today's semiconductor fabrication operations require automated process control capabilities, through the use of process control charts.
Emphasizing effluent gas scrubbing. PIETER BURGGRAAF.Semiconductor Int. 116 (June 1984). Success with the handling of effluent gases requires a thorough understanding of scrubber "science."
Advanced CMOS epitaxial processing for latch-up hardening and improved epilayer quality. JOHN OGAWA BORLAND and TOM DEACON. Solid St. Technol. 123 (August 1984). Use of silicon epitaxial wafers for advanced CMOS device processing has led to improved latch-up hardening. However, the heavily doped substrates used to improve latch-up hardening can also degrade epilayer quality. Improvements in epilayers have been achieved through the application of both pre- and post-epitaxy intrinsic gettering that activates the growth of oxygen related precipitates. In p+ (100) and n ÷ (100) wafers, epilayer minority carrier lifetimes were improved by as much as three orders of magnitude.
Flexible material handling automation in wafer fabrication. JAMES G. HARPER and Louis G. BAILEY.Solid St. Technol. 89 (July 1984). The relationship between the need for increased integration of electronic functions, chip cost, and the value of automation is developed. High yield is the requirement for economical production of integrated circuits and the factors which contribute to low yield are delineated. Particulate contamination is a prime cause of yield loss and a significant portion of this contamination is contributed by people. Automation can decrease the number of people and particles and can improve yield as well as productivity, cycle time, and also can reduce inventory. Due to the continuing change in wafer fabrication factories, automation which is flexible in nature is
New applications of tape bonding for high lead count devices. JAMES F. MARSHALL. Solid St. Technol. 175 (August 1984). Development work and use of tape automated bonding (TAB) have been accelerating due to the requirement for improved performance in the interconnection of complex VLSI devices. VHSIC speeds are forcing new approaches to packaging and interconnection. TAB offers a practical solution to many of these performance problems. TAB leads offer improved electrical, thermal and mechanical properties in addition to doubling the I/O density capability for perimeter pad configurations compared to conventional wirebonding. Furthermore, TAB technology can accommodate I/O pads anywhere on the surface of the device through the-
Polyimides in semiconductor manufacturing. RON ISCOFF.Semiconductor Int. 116 (October 1984). Polyimides are finding a broad, new range of applications in the manufacture of integrated circuits.