Ultrathin high-K metal oxides on silicon: processing, characterization and integration issues

Microelectronic Engineering 59 (2001) 341–349 www.elsevier.com / locate / mee

Ultrathin high-K metal oxides on silicon: processing, characterization and integration issues a, a a b a E.P. Gusev *, E. Cartier , D.A. Buchanan , M. Gribelyuk , M. Copel , a a H. Okorn-Schmidt , C. D’Emic a

IBM Research, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY 10598, USA b IBM Analytical Services, Hopewell Junction, NY 12533, USA

Abstract ˚ films of metal oxides deposited on silicon for advanced gate An overview of our recent work on ultrathin ( , 100 A) dielectrics applications will be presented. Data on ultrathin Al 2 O 3 , ZrO 2 , HfO 2 , and Y 2 O 3 will be shown to illustrate the complex processing, integration and device-related issues for high dielectric constant (‘high-K’) materials. Both physical and electrical properties, as well as the effects of pre- and post-deposition treatments will be discussed.  2001 Elsevier Science B.V. All rights reserved. Keywords: High-k gate dielectrics; Al 2 O 3 ; ZrO 2 ; HfO 2 ; Y 2 O 3

1. Introduction Until very recently, the (evolutionary) scaling of the gate dielectric (and ULSI devices in general) has been made by shrinking physical dimensions. As the physical thickness of SiO 2 gate oxides ˚ a number of fundamental problems (such as high gate leakage current and oxide approaches | 20 A, reliability) arise [1–3]. To overcome these fundamental limits for SiO 2 -based device scaling, new (non-SiO 2 ) materials have to be investigated and then integrated with silicon technology. To reduce the leakage current, the ‘physical’ thickness of the dielectric (stack) should be kept large while the capacitance still should scale (increase). This can be accomplished by the use of dielectric materials with high permittivity. Typically, for high-K materials under investigation (e.g. ZrO 2 [4–8], HfO 2 [6,9], TiO 2 [10], Ta 2 O 5 [11,12], Y 2 O 3 [6,13–15], Al 2 O 3 [16–20], Gd 2 O 3 [14,21], La 2 O 3 [15] , Hf or Zr silicates [22], La silicates [23] and Gd silicates [24]), the dielectric constant (ehighK ) is in the 10–40 range, a factor of approximately 3–10 higher than that of SiO 2 , eSiO 2 5 3.8. Unfortunately, for most high-K materials the higher dielectric constant comes at the expense of narrower band gap, 5–6 eV [25], i.e. lower * Corresponding author. E-mail address: [email protected] (E.P. Gusev). 0167-9317 / 01 / $ – see front matter PII: S0167-9317( 01 )00667-0

 2001 Elsevier Science B.V. All rights reserved.

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barrier height for tunneling. The lower barrier height tends to compensate the benefit of the higher dielectric constant (thicker dielectric layer). Nevertheless, for many high-K materials, the net effect is a reduced leakage current. One should note the reliability [19] and mobility [19] and charge trapping [26] issues of the high-K dielectrics are still poor understood at this stage. Needless to say, the search for the high-K candidate to replace conventional SiO 2 based gate dielectrics is an enormous task. In a very short timeframe, a perfect system like SiO 2 on Si should be replaced with a high-K material for the sole reason of the higher dielectric constant. It is the purpose of this paper to illustrate complex issues for the use of high-K materials for gate dielectric applications. Binary metal oxides of ZrO 2 , HfO 2 , Y 2 O 3 and Al 2 O 3 will be discussed. These materials are predicted to be thermodynamically stable on Si [27] and have reasonably high band gap (barrier height) [25]. We found all four materials exhibited gate leakage much lower than that of conventional SiO 2 of the same equivalent electrical thickness (capacitance) and good interface quality (after post-deposition anneals). We further discuss some integration issues, in particular thermal stability. ˚ 2. Fundamental limits for SiO 2 -based gate dielectrics scaling below 20 A Below we briefly discuss the main roadblocks for SiO 2 dielectric scaling, namely high gate leakage current, oxide breakdown and channel mobility. More technical details and discussion on the limit of SiO 2 gate oxide scaling can be found elsewhere [1–3]. When the physical thickness between the gate electrode and silicon substrate becomes thinner than ˚ the direct tunneling dominates leakage current [1,28]. The tunneling current exponentially | 30 A, increases with decreasing oxide thickness. (see solid line in Fig. 3). Even for low operation voltages ˚ the gate leakage becomes very ( | 1–1.2 V), when the thickness of the SiO 2 film approaches | 15 A 2 high, | 1 A / cm . One should note leakage specs are device design and application dependent. For example, for portable (battery-operated) devices, the leakage current requirement is even more severe. While travelling through the SiO 2 layer electrons may create defects (electron traps, interface states, etc.) [29]. Once the concentration of induced defects reaches a critical value (Nbd ) the insulating properties of the oxide (catastrophically) fail, i.e. the oxide breaks down. According to the percolation model, the concentration of Nbd decreases rapidly with decreasing oxide thickness. In other words, ˚ thickness range), reliability well-known for its excellent breakdown properties (in the . 100 A ˚ range and a matter of (lifetime) of ultrathin SiO 2 is a big concern for oxide scaling into the sub-20 A intense discussions [1,30–32]. The speed of MOSFETs is defined by how fast conduction electrons / holes can travel in the (inverted) channel between the source and drain regions of the transistor. In ultrasmall devices, the electrons in the channel are located very close to the very heavily doped gate, source and drain regions and, as a result, the electrostatic potential (and its fluctuations) in the gate and source / drain regions can extend into the channel. The long-range electrostatic interactions between these charges ˚ may have a negative impact on the performance of devices with channel length shorter than | 400 A ˚ [33]. and gate oxides thinner than | 25 A 3. Experimental The high-K films of Al 2 O 3 , ZrO 2 , HfO 2 , and Y 2 O 3 were deposited on bare silicon (after HF last pre-clean) or ultrathin thermally grown interlayer. Interface engineering is an important part of high-K

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stack integration. The interlayer helps to improve interface quality and therefore device characteristics (Dit , mobility, etc.). On the other hand, being a lower-K material with e | 4–7 (for example, SiO 2 , SiO x N y , SiN x ) it results in a lower capacitance (thicker EOT) of the whole gate stack due to series capacitance. The films studied in this work were deposited by atomic layer deposition (ALD) [34] using the following chemistries ZrCl 4 1 H 2 O; HfCl 4 1 H 2 O; Y(thd) 3 1 O 3 ; and Al(CH 3 ) 3 1 H 2 O. ˚ range. In some cases, the low temperature Physical thickness of the high-K layer was in the 15–100 A (300–4008C) ALD deposition step was followed by oxygen, nitrogen and / or forming gas anneals performed either in a furnace or an RTP reactor. Capacitor (and in some cases transistor) structures were then fabricated on both n- and p-type Si wafers for electrical measurements. Aluminum or poly-Si (if thermal stability allows, see discussion below) gates were employed. Capacitance–voltage (C–V ) measurements were used to obtain equivalent electrical thickness of the high-K gate stack, flatband / threashold voltage, interface quality (interface defects) and hysterisis. Electrical thickness (Tqm) was calculated from capacitance in accumulation using quantum-mechanical corrections [1] Current–voltage (I–V ) characteristics were taken to understand leakage current properties of the insulators studied. Electrical measurements were complimented by physical analysis [5] with the help of cross-sectional electron microscopy (HRTEM), medium energy (100–200 keV) ion scattering (MEIS) [35–37], photoemission spectroscopy (XPS), atomic force microscopy (AFM), nuclear reaction analysis (NRA) [17,36], ellipsometry and other analytical tools.

4. Results and discussions High-frequency and quasi-static CV characteristics of a ZrO 2 film deposited on a thin SiO 2 interlayer is shown in Fig. 1. Good interface quality comparable to that of pure SiO 2 can be seen. By measuring films of different thickness and plotting electrical (quantum-mechanical) thickness versus physical thickness, the dielectric thickness of |20–24 was obtained (see Figs. in Ref. [6]). The ˚ thickness of interfacial oxide in this experiment was varied from close to zero to as much as 15 A,

Fig. 1. High-frequency, 100 kHz, (solid symbols) and quasi-static (open symbols) capacitance-voltage curves for Al / ZrO 2 / SiO 2 /n-Si(100) stack capacitors. Good interface quality (with Dit ,1310 11 cm 22 ) can be concluded.

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Fig. 2. Current-voltage characteristics of annealed ZrO 2 / SiO 2 gate stacks with different thickness of the ZrO 2 layer. The measurements were taken in accumulation on both n- and p- type Si wafers. An asymmetry of the positive vs. negative bias comes from different barrier heights at the gate electrode / gate dielectric and gate dielectric / Si substrate interfaces.

depending on processing conditions. Most thickness increase comes from SiO x growth at the interface after oxygen anneals. From CVs (Fig. 1), a negative flatband voltage shift of | 2400–500 meV (with respect to the ideal Al gated MOS case) is observed. The magnitude of the shift depends on the thickness of the bottom interlayer as well as on postdeposition anneal conditions [6]. Leakage current of ZrO 2 / SiO 2 gate stacks is found to be low (Fig. 2), |4–5 orders of magnitude lower than SiO 2 of equivalent electrical thickness (Fig. 3). However, films deposited on hydrogen terminated Si (after

Fig. 3. Gate leakage current density of ZrO 2 gate stacks as a function of equivalent electrical (quantum mechanical) thickness. Dashed line is a guide for eye only. Current density was extracted from I–V data (see Fig. 2) in accumulation at 1 V above flatband. SiO 2 data is also shown for comparision (solid line).

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HF-last preclean) exhibit poor gate leakage characteristics [6]. We attribute this to the nucleation problem observed in our recent MEIS and HRTEM experiments [4,5]. More details on the physical analysis of the stoichiometric ZrO 2 ALD films can be found elsewhere [4–6]. HfO 2 films behave quite similar to ZrO 2 due to the similarities in the ALD chemistries and materials properties. We found that good quality HfO 2 gate stacks could be fabricated with significantly reduced leakage current, consistent with other reports in the literature [9]. In analogy to ZrO 2 , poor nucleation of HfO 2 on hydrogen terminated surface was observed by MEIS, HRTEM and also supported by electrical measurements. We discuss more results on HfO 2 in a forthcoming paper. In both the HfO 2 and ZrO 2 cases we found uniform continuous ultrathin high-K layers can be deposited on thin SiO 2 film. Due to a different ALD chemistry used for Y 2 O 3 depositions, specifically the high reactivity of the ozone and carbon-containing metal precursor, we found the films to be oxygen-rich with some (up to |6%) residual carbon. No significant difference in depositions on HF-last Si surface and SiO 2 interlayers was observed. This could be explained by SiO 2 formation at the interface from the ozone ˚ of exposures or SiO 2 growth during sample exposure to air. In fact, in both cases |11–14 A interfacial oxide was deduced from HRTEM, MEIS, and XPS experiments [6]. The presence of SiO 2 ˚ (EOT). Electrically the films show low may limit the scalability of Y 2 O 3 grown by ALD to 10 A leakage (Fig. 4). When compared to SiO 2 (solid bench line on the Fig), gate leakage is reduced by approximately four to five decades. As discussed above, a thin interlayer of SiO x is often present between high-K layer(s) and the Si substrate, either as a result of the deposition reaction or as a necessary ‘template’ to achieve uniform depositions. Minimizing the thickness of the interlayer is important to reduce a parasitic effect of series capacitance in the gate stack. Recently, we demonstrated [17] that Al 2 O 3 can be deposited uniformly directly on Si without an interlayer (Fig. 5). The leakage current is lower than that of SiO 2 [19],though not as much as in the case of ZrO 2 , HfO 2 , and Y 2 O 3 (because of the lower dielectric constant). The dielectric constant was obtained by measuring capacitors of different thickness (Fig. 6) and plotting the data in the electrical thickness vs. physical thickness coordinates (Fig. 7). From CV

Fig. 4. Leakage current summary for Y 2 O 3 high-K gate dielectrics.

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Fig. 5. HRTEM image taken from a poly-Si /A 2 O 3 / Si transistor.

measurements (Fig. 6), one should note a positive shift (|300–400 meV), also reported in our previous publication [19]. Another difference between Al 2 O 3 and ZrO 2 , HfO 2 , Y 2 O 3 depositions is that as-deposited Al 2 O 3 films are amorphous (Fig. 5) whereas the other three films show a microcrystalline structure. Upon annealing at high temperatures, Al 2 O 3 film undergoes a structural transformation too (Fig. 8). More details on materials and electrical properties of ultrathin ALD Al 2 O 3 films can be found in our other recent publications [5,6,17–20]. Thermal stability of high-K gate dielectrics (especially in the contact with Si) is an important issue

Fig. 6. A family of C–Vs curves for n 1 poly-Si /Al 2 O 3 / p-Si capacitor with various thickness of the Al 2 O 3 layer.

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Fig. 7. Equivalent electrical thickness of poly-Si gated Al 2 O 3 gate dielectric devices as a function of the physical thickness of the Al 2 O 3 layer. A least-squares fit to the data shows the dielectric constant (calculated from the slope of the fit) of the high-K layers is approximately 11.

since high temperature (.10008C) activation anneals are required for conventional (poly-Si) CMOS process flow. Our studies show that not all the materials satisfy these requirements. For example, ZrO 2 films react with the Si substrate forming zirconium silicide [4]. Of the four materials studied, Al 2 O 3 exhibits best thermal ‘robustness’. In fact, we fabricated short-channel poly-Si gated transistors with Al 2 O 3 gate stack using conventional process flow [19]. Lower thermal budget process schemes (e.g. replacement gate) are under investigation for materials with lower thermal stability. Another important (desired) parameter of high-K films is diffusion barrier properties, in particular with respect to dopant penetration and resistance to SiO x formation at the silicon interface. Boron penetration was recently reported for PFET devices with Al 2 O 3 gate dielectrics [38]. Many binary metal oxides are known to be good ionic conductors implying that conductivity of ions can be high.

Fig. 8. Refractive index of a thick Al 2 O 3 layer after postdeposition anneals in nitrogen.

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Table 1 Some important properties of selected high-K metal oxides grown by atomic layer deposition a High-K material

Dielectric constant

Leakage current reduction (wrt SiO 2 )

Thermal stability, T max , C (MEIS data)

ZrO 2 HfO 2 Y2O3 Al 2 O 3

|23 |20 |15 |10

310 4 310 4 310 4 310 2

|900 |950 silicate formation |1000

–10 5 –10 5 –10 5 –10 3

a

Leakage current values were deduced from Al gated capacitors in accumulation at 1V above flatband. Thermal stability data was obtained with the help of MEIS on uncapped (i.e. vacuum / high-K / Si) structures.

High diffusivity of oxygen was observed for thin ZrO 2 layers on Si [39]. We found the growth of ˚ when thin Al 2 O 3 layers were exposed at 6008C to low interfacial SiO 2 of the thickness of |4 A 24 partial pressures of oxygen, as low as 10 Torr [18]. While this effect may be insignificant for thicker films, it can not be ignored for ultrathin films where the thickness (capacitance) of the SiO 2 layer will dominate the capacitance of the gate stack. Depending on high-K material and its thickness, bottom interface, and oxidation conditions, we observed an increase of equivalent electrical thickness on the ˚ during mild (500–7008C) post deposition anneals, an effect also seen by other order of 3–5 A research groups. In summary, an analysis of basic physical and electrical properties of ultrathin ZrO 2 , HfO 2 , Y 2 O 3 , and Al 2 O 3 gates has been performed. Some important properties of the materials are summarized in Table 1. Acknowledgements The authors would like to thank B. He (summer intern, presently with IBM Microelectronics in East Fishkill), S. Sayan (summer intern, Rutgers University) for their help with measurements, and M. Tuominen, M. Jussila, and S. Haukka (ASM Microchemistry) for depositions, and A. Callegari, S. Guha, D. Neumayer, P. Kozlowski for discussions. References [1] D. Buchanan, IBM J. Res. Develop. 43 (1999) 245. [2] M.L. Green, E.P. Gusev, R. Degraeve, E. Garfunkel, J. Appl. Phys. (Review) 90 (2001), in press. [3] E.P. Gusev, Ultrathin oxide films for advanced gate dielectrics applications: recent progress and future challenges, in: G. Pacchioni et al. (Ed.), Defects in SiO 2 and Related Dielectrics, Science and Technology, Kluwer, Dordrecht, 2000, p. 557. [4] M. Copel, M. Gribelyuk, E.P. Gusev, Appl. Phys. Lett. 76 (2000) 436. [5] E.P. Gusev, M. Copel, E. Cartier, D.A. Buchanan, H. Okorn-Schmidt, M. Gribelyuk, D. Falcon, R. Murphy, S. Molis, I.J.R. Baumvol, C. Krug, M. Jussila, M. Tuominen, S. Haukka, Physical characterization of ultrathin films of high dielectric constant materials on silicon, in: H.Z. Massoud, E.H. Poindexter, M. Hirose, I.J.R. Baumvol (Eds.), The Physics and Chemistry of SiO 2 and the Si–SiO 2 Interface –4, The Electrochemical Soc, Pennington, NJ, 2000, p. 477.

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