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Worst-case analysis and statistical simulation of MOSFET devices based on parametric test data
Solid-State Electronics 45 (2001) 1537±1547
Worst-case analysis and statistical simulation of MOSFET devices based on parametric test data Qiang Zhang a, Juin J. Liou a,*, John McMacken b, J. Ross Thomson b, Kevin Stiles b, Paul Layman b a
Department of Electrical and Computer Engineering, School of EE and CS, University of Central Florida, Orlando, FL 32816, USA b Microelectronics Group, Agere Systems, Orlando, FL 32819, USA Received 17 February 2001; accepted 14 April 2001
Abstract A practical and ecient approach for estimating the MOSFET device and circuit performance distributions is presented. The proposed method is based on the Latin hypercube sampling technique and direct extracting and utilizing the statistical information obtained from a population of parametric test data. Using this approach, a set of worst-case models taking into account data correlations and equal probability constraints is developed. The procedure allows for a systematical and accurate way to predict the performance spread and worst case of MOSFET circuits, as well as a greatly reduced computation time for statistical simulation. Measured data of two digital circuits are included in support of the modeling work. Ó 2001 Elsevier Science Ltd. All rights reserved. Keywords: Worst-case analysis; Statistical simulation; Parametric test data; BSIM3v3 model; Principal component analysis; Latin hypercube sampling; MOSFET devices; Digital circuits
1. Introduction The performance of any MOS devices and integrated circuits exhibits global chip-to-chip variations due to fabrication process variation. To predict statistical device and circuit performance spreads, worst-case analysis and statistical (Monte Carlo) simulation are generally used [1±9]. Most previous studies conduct statistical analysis on chip-to-chip variation in the device parameter space, which involves extracting device model parameters from a large number of chips gathered over a period of time, and analyzing the variance±covariance of the extracted model parameters. The information obtained is then statistically analyzed to generate meaningful device models for statistical circuit simulation, or
*
Corresponding author. Tel.: +1-407-823-2786; fax: +1-407823-5835. E-mail address: [email protected] (J.J. Liou).
is used to specify parameter deviations from nominal values to represent certain extremes of circuit performances in worst-case design. In these approaches, the detailed parameter extraction procedure, the ``noise'' from optimization, and the nonlinear relationship among model parameters may aect the parameter statistics. Hence, considerable eorts are needed to ensure the device models generated from the statistics are valid, accurate, and physical. Furthermore, because of the complicated correlation and relationship between device model parameters and circuit performances, the model parameters that lead to worst-case circuit performances are not necessarily located at the parameter extremes. To obtain realistic worst-case models, an approximated relationship between circuit performances and device model parameters has to be sought ®rst, which may require extensive circuit simulations. The worst-case models obtained in this rigorous way can be accurate but are not generalized (i.e., it is circuit con®guration speci®c), therefore the procedure needs to be repeated for each of the primitive functional cells [11]. As a result,
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it is a common practice to supply a set of worst-case models to the manufacturing library, and such worstcase models can only give a qualitative indication of product parametric yield. The objective of this study is to develop a generalized, straightforward, and practical approach for worstcase analysis and statistical simulation for estimating product parametric yield. The modeling approach is based on a set of key device I±V characteristics, such as saturation current ION and threshold voltage VT , which are routinely collected at the end of line for process monitoring. This data accurately re¯ects the process and device behavior variations and, especially, could give direct indication and important information of circuit performances [11±13]. These measurements of device I±V characteristics are called the parametric test data. Although we used a particular set of parametric tests in this work, the methodology is general and it certainly can be modi®ed to include other prominent parametric tests. In our approach, a set of simulated test data is extracted ®rst from the parametric test data using appropriate statistical analysis. Such a data set has a much smaller size than the parametric test data, yet still accurately represents the MOS behavior. The simulated test data is then optimized and used to generate a set of critical parameters of a MOS model, such as BSIM3v3. Circuit simulations are then carried out to predict the circuit performance spreads. Fig. 1 shows the ¯owchart of the present method (solid arrows) and conventional methods (dashed arrows). While both methods use similar statistical ana-
Fig. 1. Flowchart for conventional statistical modeling approaches ( Numbers are shown for illustration purpose.
lysis, the main dierence is that in the present approach the simulated test data (i.e., D in ¯owchart) is ®rst extracted from measurements, whereas in the conventional approach the device model (i.e., BSIM3v3) parameters (i.e., P in ¯owchart) are ®rst optimized from measurements. Using the matrix size given in the ¯owchart, it is evident that the present approach can greatly reduce the number of optimizations needed to generate the MOS models for circuit simulation. Also, the optimized device models (i.e., P in ¯owchart) resulting from the present approach can better re¯ect the physical behavior of the MOS devices measured. The organization of the paper is as follows. The MOSFET model parameter extraction procedure will be described in Section 2. In Section 3, the worst-case and statistical models will be developed based on the principal component analysis (PCA) [14] and Latin hypercube sampling (LHS) technique [15]. The models developed will then be applied to a 0:25 lm CMOS process, and comparisons between the measured and simulated MOS device variations will be presented. In Section 4, two MOSFET digital circuits will be considered, and their simulated and measured delay time variations will be compared.
2. MOSFET model parameter extraction The compact MOSFET model used in this study is the BSIM3v3 model [16]. A technique for selecting and extracting critical BSIM3 model parameters via opti-
) and present statistical modeling approach (
).
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mization algorithms from the parametric test data will be discussed in this section. Extracting device model parameters is actually the last step in our statistical modeling approach, but to explain the modeling methodology, it will be described ®rst in this section. Generally, the functional performances of MOSFET digital circuits are determined by three transistor characteristics: saturation current ION , transconductance b, and threshold voltage VT . For NMOS devices, they are de®ned as (body bias is zero in all cases, i.e. Vbs 0 V):
Table 2 BSIM model parameters categorized into three groups based on their associated physics and the MOS geometry
· ION is the saturation current, which is de®ned as the drain current at both drain voltage Vds and gate voltage Vgs equal to the supply voltage. max max · b is a factor de®ned as b gm 106 =Vds , where gm is the maximum transconductance in the low drain voltage triode region. · VT is the threshold voltage, which is de®ned as VT V1 Vds =2 Vds 0:1 V), where V1 is the linear extrapolation from the point of maximum transconductance.
to their nominal values, as they have no eect on the bias points of interests. Thus, the number of the parameters that may be utilized to ®t the measurements is reduced to around 20. We have found, and experimentally veri®ed later, that a set of nine critical parameters is sucient to ®t the nine bias points. The nine critical parameters that result in minimum root mean square (RMS) of error were selected as follows. Instead of trying all possible parameter combinations, we simpli®ed the problem by categorizing these 20 parameters into three groups according to their physical meaning and the geometry to which they are most sensitive (Table 2). Then, three parameters are chosen from each group at a time, and they are used to ®t a small set of representative data generated using an advanced sampling technique, which will be described later. The set of parameters that produces minimum RMS is chosen and used in the subsequent optimization procedure. From this procedure, nine BSIM3 model parameters vth0, u0, a0, dvt0, pclm, lint, k3, b0, and wint were extracted and selected separately from their relevant geometries:
A complementary set of de®nitions can be set for PMOS devices. This data is typically measured on ®ve chips per wafer. On each chip, transistors of various geometries are measured, and NMOS and PMOS transistors having the following three geometries are considered: longchannel/wide-channel, short-channel/wide-channel, and short-channel/narrow-channel devices (e.g. see Table 1). They consist of two dierent channel lengths and two dierent channel widths. For the three data points (i.e. ION , b and VT ) of interest, there are nine measured data points for each die. A complete extraction of a BSIM3v3 model requires full I±V characterization of many transistors of varying geometries and body biases. Since we are only interested in the three MOSFET characteristics mentioned earlier, we may just extract a few critical BSIM3 model parameters that have the most impact on these device characteristics. To this end, we ®x the parameters associated with body bias eects to their nominal values since the body bias is zero in our measurements. Furthermore, the parameters aecting the drain current in the noncritical regions of operation (i.e., subthreshold region and transition region) can be ®xed
Table 1 NMOS and PMOS device geometries considered for the extraction of the critical BSIM3 model parameters MOS type
Long/ wide (lm)
Short/ wide (lm)
Short/narrow (lm)
NMOS PMOS
15/15 15/15
0.32/15 0.28/15
0.32/0.64 0.28/0.64
Geometry
Model parameters
Long/wide Short/wide
vth0, u0, vsat, a0 dvt0, dvt1, k1, pclm, ua, ub, pvag, ags, rdsw, nlx, lint dvt0w, dvt1w, k3, b0, b1, w0, wint
Short/narrow
1. vth0, u0 and a0 from long-wide device; 2. dvt0, pclm and lint from short-wide device; 3. k3, b0, and wint from short-narrow device. A general nonlinear least square optimization package available in SPLUS [17] is used. Finally, the nine parameters were optimized simultaneously to obtain minimum RMS error. On average, the sum of error squares is well below 10 12 , thereby suggesting that the model with the extracted parameters can match very closely the device performance at measured bias points. It should be pointed out that the approach developed is not restricted to these nine parameters selected, and other sets of parameters may be used to carry out the statistical simulation, as long as the parameters selected can provide an accurate playback of the MOS device characteristics. In other words, there is a ¯exibility in choosing the device model parameters, and the reason we selected the set of nine parameters is because it is an optimal set determined from our optimization process and it yields good accuracy. Fig. 2 shows excellent agreement between the simulated and the measured I±V
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Fig. 2. Comparison of I±V curves of NMOS and PMOS with three dierent geometries obtained from measurements (symbols) and simulated from BSIM3 model using the extracted critical parameters (lines).
characteristics of MOS devices having three dierent geometries. 3. Worst-case analysis and statistical simulation The product parametric yield is de®ned as the percentage of well functioning circuits that meet all design speci®cations, and can be estimated by using either the worst-case analysis or Monte Carlo simulation. In the worst-case analysis, the parametric yield is estimated by comparing the proposed performance boundary with the design speci®cation windows. In the Monte Carlo simulation, a number of ``random'' model samples is produced according to a certain statistical distribution and subsequently used in circuit simulations. If the number
of samples is suciently large, the parametric yield can be estimated by Yield
number of circuits whose y 2 X total number of circuit samples
1
where y represents circuit performances and X represent speci®cation window. 3.1. Worst-case analysis A conventional method to generate worst-case models used in industry is based on extraction from extensive measurements of devices with various sizes and temperatures on a sample wafer [10,18]. Next, worstcase polygons are speci®ed as ``fast'' or ``slow'' based on
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Fig. 3. Example showing qualitatively the worst-cases of NMOS and PMOS, using the six nonnominal device models.
skew corners of some electrical parameters, such as VT , b, and ION . A fast device has low VT , high b and high ION , whereas a slow device has high VT , low b and low ION . Correspondingly, the worst-case polygons consist of the following six device models in addition to the nominal model: N±N H±H L±L H±LT
L±HT HT±L LT±H
nominal NMOS and PMOS models fast NMOS and fast PMOS models slow NMOS and slow PMOS models fast NMOS model and corresponding slow PMOS model. This and the following three cases are intended to account for the global mismatch between NMOS and PMOS. slow NMOS model and corresponding fast PMOS model slow PMOS model and corresponding fast NMOS model fast PMOS model and corresponding slow NMOS model
Fig. 3 illustrates qualitatively the worst cases of VT and ION for NMOS and PMOS using the concept of the above mentioned six device models. Such an approach, while encapsulating information about correlation between n-type devices and p-type devices, completely neglects all other correlations. Furthermore, it provides no information on the probability of the worst-case corners. Here, we propose a method to select worst-case corners on a equidensity surface in the parametric test data space, taking into account all correlations between the parametric test data. The joint distributions of both the parametric test data can be determined using a multivariate v2 test [14]. It has been shown that, if y has an n-variate normal distribution with mean l and variance±covariance matrix R, then C y l0 R 1 y l is distributed as a v2 probability distribution with ndegree of freedom. We found that the multivariate normal distribution is a good approximation in our case, as
Fig. 4. The C y l0 R 1 y l distribution (Ð) of the standardized test data y as compared with the hypothesized v2 distribution (- - -). The solid line is the empirical probability distribution of the y l0 R 1 y l distribution, and the doted line is the hypothesized v2 distribution. The good agreement justi®es our assumption of multivariate normal distribution.
evidenced by the comparison of the distribution of standardized test data and v2 distribution shown in Fig. 4. Hence, the equal-density contours of the data and the parameter distributions can be visualized as hyperellipsoids. Using the PCA, the correlated device parameters can be eectively transformed to k uncorrelated components. If the device parameters are standardized to have zero mean and unit variance, the original 3r hyper-ellipsoid in device parameter space is now transformed to a k-dimensional hyper-sphere. We selected a set of worst cases by maximizing or minimizing device characteristics VT , b, and ION with the constrain of the parameters on the desired equal-density surface of the hyper-sphere, such as 3r surface. Thus, the optimization problem becomes:
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2
3 y1 6 y2 7 6 7 \max"F y 6 . 7 f p1 ; p2 ; . . . ; pm 4 .. 5 yn
where p R x;
x21 x22 x2k 3r2
2
where y is the vector of circuit performances, ``max'' stands for either minimizing or maximizing the corresponding yi simultaneously, p is the matrix of parametric test data VT , b and ION , R is the transformation matrix from PCA, x represents the principal components, and k 6 m. In our case, n and m are equal to 18, taking into account both NMOS and PMOS. In fact, Eq. (2) is a multiobjective optimization problem, which does not have a global solution. In some digital applications where one prominent circuit performance can be approximately modeled by the device characteristics VT , b and ION using regression analysis, the regression model can be used as a single objective function F(y) to be optimized. Then, a set of worst-case models can be selected for that particular application by optimizing the objective function. Thus, the problem can be expressed as: min F y w1 p1 w2 p2 with y f p R x;
1
w n pn 3
and jxj2 3r2 where y inside [ ] 1 is the objective needs to be maximized and weights wI are regression coecients. In our work, we took a dierent approach in which the worst-case corners were chosen from the equidensity data surface so that these corners span most of the measured device variations. In other words, the worstcase corners were extracted by optimizing certain cumulative probability (i.e., optimizing the proportion of devices satisfying certain speci®cations). For example, the ``fast'' case is de®ned as the model leads to fVT , b , ION g that maximizes
Fig. 5. Example of the grids of two principal components. Under equal-probability requirement, grid fB , D , F , H g are selected instead of fB, D, F , Hg. The grid O (0, 0) represents the nominal case.
to zero equal 0, otherwise x 9=u1=2 , where u is the number of x that are not zero. Suppose there are k principal components used and each component is quantized into three levels, then the worst cases are to be sought from 3k grids according to their corresponding de®nitions. A simple qualitative example with two principal components is given in Fig. 5. To further illustrate this quantitatively, we used seven principal components to model the corners of the test data measured in a month. As can be seen from Fig. 6, the ®rst
proportion VT n > VT n ; Ion n < Ion n ; b:n < b n ; VT p > VT p ; Ion p < Ion p ; b p < b p ; . . . 4 Eq. (4) incorporates joint cumulative proportion for all nine parametric test data. For computational eciency, we further simpli®ed the problem by quantizing the principal components x onto a ®nite grid. Note that the corners generated by simply combining these grids are not on the same equal-probability surface. Hence, the grid is chosen in the following fashion: 1) each component is ®rst quantized into three levels f 1; 0; 1g; and 2) in a combination f1; 0; . . . ; 1g, all x that corresponds
Fig. 6. Variance of one month of test data obtained from the principal component analysis, where seven principal components can explain more than 90% variance of the test data, and nine principal components can explain more than 95% variance of the test data.
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seven principal components explain more than 90% of the variance in the test data. From all those 37 combinations of the seven components, six worst-case models were selected. Fig. 7 shows the worst-case distributions obtained from the measured test data and simulated from the present worst-case model. For comparison, the results of the worst cases predicted from the existing method are also included in the ®gure. The existing worst-case model was generated by optimization of model parameters to make the model hits speci®ed (i.e., 95%) variations in the threshold voltage VT . The ellipses represent the 3r con®dence regions of the corresponding test data by assuming bivariate distribution. The unshaded poly-
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gons represent the device variation extent estimated by the existing worst-case model. The vertices of the shaded polygons are the projections of the proposed model on an equal-probability hyper-ellipse. As can be seen from the ®gure, the present worst-case models give a good indication for the range of device characteristics while capturing correctly the correlations, whereas the existing worst-case model grossly overestimates those cases. 3.2. Statistical simulation The goal of the statistical model is to generate a few but statistically sucient numbers of device models that can resemble the device statistics extracted from large
Fig. 7. Comparison of the variance region obtained from the proposed worst-case models (shaded polygons), the existing worst-case models (unshaded polygons), and 3r con®dence region (dashed ellipses) of the test data.
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keep a low variance of the estimator. An advanced sampling technique, LHS technique [15], was used in this study in order to reduce the number of simulation samples. The LHS technique has been successfully used in studies of simulating and modeling process variation to reduce simulation cost [9,10]. By using the LHS, we are able to use only a few tens of samples to achieve the same eect that would require hundreds of samples using simple random sampling. We applied the statistical models to a 0.25 lm CMOS process at Lucent Technologies. Test data was collected on 9000 die fabricated during one month from a single fabrication line, and analyzed using the principal component analysis. Then, each principal component was sampled using the LHS technique and transformed back to device data. Fig. 8 compares the measured and simulated distributions of the device characteristics. The
PMOS.lon
PMOS.Vt
sets of measurements. These device models, when implemented in circuit simulation, shall be able to predict the variance of circuit performance. Though much less ecient than the worst-case analysis, the statistical simulation renders quantitative and more precise information to circuit designers when the decision must be made to make appropriate tradeos between circuit performance and yield. As described previously, our statistical analysis is directly based on the statistics of the parametric test data, as discussed in Section 1 and shown in Fig. 1. To improve circuit simulation eciency, the sample of device models should be as few as possible while maintaining valid device statistics. In the conventional Monte Carlo simulation, each principal component is sampled using a simple random sampling technique. The simple random sampling requires a large number of samples to
NMOS.Vt
NMOS.lon
Fig. 8. Variance of MOS performance simulated from the present model using 100 sample data (dotted ellipses) and using 30 sample data (solid ellipses). Also shown are the distributions of the actual measured data (dashed ellipses).
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Fig. 9. Device variations predicted by the statistical model (solid lines) and obtained from measurements (bars and dashed lines) for two MOSFET devices with device geometries dierent from the ones considered in BSIM3 model parameter extraction.
dashed ellipses represent 3r con®dence regions of the test data, and the dotted and solid con®dence ellipses represent simulated MOS performance using 100 and 30 simulated samples, respectively. The results suggested that the number of samples can be as few as 30 while the simulated distribution still matches reasonably well with the measurements. Nonetheless, when the sample size becomes smaller, there are more chances to have spurious correlations between the principal components so that the distribution of the simulated data no longer matches the measured distribution. Special care must be taken to minimize the spurious correlation as much as possible. Thus, we were able to accurately represent the distributions of the test data with only a small number of simulated data. The transistor models derived from this approach can then be incorporated into circuit simulation. While the statistical model was developed based on the parameters extracted from the three MOS geome-
tries (see Section 1 and Table 1), it should provide good approximations for devices with other medium geometries as well. To verify this, we have shown in Fig. 9 the measured and simulated VT and ION distributions of NMOS having the geometries of 1=15 and 5=5 not considered in Table 1. Good agreement is found between the measured and simulated data. 4. Model applications in digital circuits To illustrate the applications in circuit design, the proposed worst-case model was applied to estimate the delay time bounds of two CMOS ring oscillator circuits. One circuit consists of 501 stages of inverters, and the other consists of 501 stages of NAND gates. In both circuits, the size (width/length) of the NMOS is 2.66/ 0.32, and the size (width/length) of the PMOS is 3.66/ 0.28. Figs. 10 and 11 show the histogram plots of the
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Fig. 10. Measured delay time spreads, and the delay time bounds predicted by the proposed and existing worst-case analyses for the 501 stage inverter ring oscillator. Fig. 12. Measured delay time distribution (bars and the dotted line) of a 501 stage inverter ring oscillator compared with the results of the statistical simulation (solid line). Both lines were obtained by ®tting with normal distribution. The upper and lower worst-case bounds are also shown.
Fig. 11. Measured delay time spread, and the delay time bounds predicted by the present and existing worst-case analyses for the 501 stage NAND ring oscillator.
circuit delay times measured from about 700 inverter ring oscillator circuits and NAND ring oscillator circuits, respectively. All transistors of the same channel type are assumed identical within a circuit, i.e. no intradie variation considered. Also included in the ®gures are the results obtained from the proposed and the existing worst-case models. Clearly, the proposed model generates more accurate bounds than the existing model, but the bounds obtained from the proposed model are still too wide compared to the measured values. This is due to the assumption of simple linear relation between parametric data and circuit performance used in the model development. Nevertheless, the model provides reasonable worst-case predictions and is useful for simple estimate of parametric yield in process monitoring and control. The delay time spreads of the two oscillators were also simulated using statistical simulation with 30 sample
Delay time of NAND Ring Oscillator (ps)
Fig. 13. Measured (bar and dotted line) delay time distribution of the 501 stage NAND ring oscillator circuit compared with the results of statistical model (solid line).
devices, as shown in Figs. 12 and 13. It is demonstrated that the statistical model is in good agreement with the measured delay time spread and gives much more quantitative and precise predictions than the worst-case analysis. Moreover, this is achieved with a minimal computation resource of only 30 sample devices. 5. Conclusions In summary, we have developed an ecient and practical statistical modeling approach based on the
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statistics of three parametric test data. While some particular parametric tests were used in this study, the modeling methodology applies generally to other parametric tests. Using this method, an improved worst-case analysis was developed by taking into account the data correlation and equal-probability constraints. An improved statistical model was also constructed using the combination of the PCA and the LHS technique to reduce the number of samples and thus the computation required. It was suggested that a sample size of 30±100 is sucient to represent the joint distribution of actual test data. The proposed worst-case and statistical models have been applied to a 0.25 lm CMOS technology. The delay time distributions of two ring oscillator circuits were measured and simulated. The results indicated that the present worst-case analysis compares more favorably with measurements than the existing ones. In addition, it was demonstrated that the statistical model developed compares favorably with measurements and provides more accurate, precise, and detailed information on the circuit performance spreads than the worstcase analysis.
[6] [7]
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[10] [11] [12]
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Worst-case analysis and statistical simulation of MOSFET devices based on parametric test data Qiang Zhang a, Juin J. Liou a,*, John McMacken b, J. Ross Thomson b, Kevin Stiles b, Paul Layman b a
Department of Electrical and Computer Engineering, School of EE and CS, University of Central Florida, Orlando, FL 32816, USA b Microelectronics Group, Agere Systems, Orlando, FL 32819, USA Received 17 February 2001; accepted 14 April 2001
Abstract A practical and ecient approach for estimating the MOSFET device and circuit performance distributions is presented. The proposed method is based on the Latin hypercube sampling technique and direct extracting and utilizing the statistical information obtained from a population of parametric test data. Using this approach, a set of worst-case models taking into account data correlations and equal probability constraints is developed. The procedure allows for a systematical and accurate way to predict the performance spread and worst case of MOSFET circuits, as well as a greatly reduced computation time for statistical simulation. Measured data of two digital circuits are included in support of the modeling work. Ó 2001 Elsevier Science Ltd. All rights reserved. Keywords: Worst-case analysis; Statistical simulation; Parametric test data; BSIM3v3 model; Principal component analysis; Latin hypercube sampling; MOSFET devices; Digital circuits
1. Introduction The performance of any MOS devices and integrated circuits exhibits global chip-to-chip variations due to fabrication process variation. To predict statistical device and circuit performance spreads, worst-case analysis and statistical (Monte Carlo) simulation are generally used [1±9]. Most previous studies conduct statistical analysis on chip-to-chip variation in the device parameter space, which involves extracting device model parameters from a large number of chips gathered over a period of time, and analyzing the variance±covariance of the extracted model parameters. The information obtained is then statistically analyzed to generate meaningful device models for statistical circuit simulation, or
*
Corresponding author. Tel.: +1-407-823-2786; fax: +1-407823-5835. E-mail address: [email protected] (J.J. Liou).
is used to specify parameter deviations from nominal values to represent certain extremes of circuit performances in worst-case design. In these approaches, the detailed parameter extraction procedure, the ``noise'' from optimization, and the nonlinear relationship among model parameters may aect the parameter statistics. Hence, considerable eorts are needed to ensure the device models generated from the statistics are valid, accurate, and physical. Furthermore, because of the complicated correlation and relationship between device model parameters and circuit performances, the model parameters that lead to worst-case circuit performances are not necessarily located at the parameter extremes. To obtain realistic worst-case models, an approximated relationship between circuit performances and device model parameters has to be sought ®rst, which may require extensive circuit simulations. The worst-case models obtained in this rigorous way can be accurate but are not generalized (i.e., it is circuit con®guration speci®c), therefore the procedure needs to be repeated for each of the primitive functional cells [11]. As a result,
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it is a common practice to supply a set of worst-case models to the manufacturing library, and such worstcase models can only give a qualitative indication of product parametric yield. The objective of this study is to develop a generalized, straightforward, and practical approach for worstcase analysis and statistical simulation for estimating product parametric yield. The modeling approach is based on a set of key device I±V characteristics, such as saturation current ION and threshold voltage VT , which are routinely collected at the end of line for process monitoring. This data accurately re¯ects the process and device behavior variations and, especially, could give direct indication and important information of circuit performances [11±13]. These measurements of device I±V characteristics are called the parametric test data. Although we used a particular set of parametric tests in this work, the methodology is general and it certainly can be modi®ed to include other prominent parametric tests. In our approach, a set of simulated test data is extracted ®rst from the parametric test data using appropriate statistical analysis. Such a data set has a much smaller size than the parametric test data, yet still accurately represents the MOS behavior. The simulated test data is then optimized and used to generate a set of critical parameters of a MOS model, such as BSIM3v3. Circuit simulations are then carried out to predict the circuit performance spreads. Fig. 1 shows the ¯owchart of the present method (solid arrows) and conventional methods (dashed arrows). While both methods use similar statistical ana-
Fig. 1. Flowchart for conventional statistical modeling approaches ( Numbers are shown for illustration purpose.
lysis, the main dierence is that in the present approach the simulated test data (i.e., D in ¯owchart) is ®rst extracted from measurements, whereas in the conventional approach the device model (i.e., BSIM3v3) parameters (i.e., P in ¯owchart) are ®rst optimized from measurements. Using the matrix size given in the ¯owchart, it is evident that the present approach can greatly reduce the number of optimizations needed to generate the MOS models for circuit simulation. Also, the optimized device models (i.e., P in ¯owchart) resulting from the present approach can better re¯ect the physical behavior of the MOS devices measured. The organization of the paper is as follows. The MOSFET model parameter extraction procedure will be described in Section 2. In Section 3, the worst-case and statistical models will be developed based on the principal component analysis (PCA) [14] and Latin hypercube sampling (LHS) technique [15]. The models developed will then be applied to a 0:25 lm CMOS process, and comparisons between the measured and simulated MOS device variations will be presented. In Section 4, two MOSFET digital circuits will be considered, and their simulated and measured delay time variations will be compared.
2. MOSFET model parameter extraction The compact MOSFET model used in this study is the BSIM3v3 model [16]. A technique for selecting and extracting critical BSIM3 model parameters via opti-
) and present statistical modeling approach (
).
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mization algorithms from the parametric test data will be discussed in this section. Extracting device model parameters is actually the last step in our statistical modeling approach, but to explain the modeling methodology, it will be described ®rst in this section. Generally, the functional performances of MOSFET digital circuits are determined by three transistor characteristics: saturation current ION , transconductance b, and threshold voltage VT . For NMOS devices, they are de®ned as (body bias is zero in all cases, i.e. Vbs 0 V):
Table 2 BSIM model parameters categorized into three groups based on their associated physics and the MOS geometry
· ION is the saturation current, which is de®ned as the drain current at both drain voltage Vds and gate voltage Vgs equal to the supply voltage. max max · b is a factor de®ned as b gm 106 =Vds , where gm is the maximum transconductance in the low drain voltage triode region. · VT is the threshold voltage, which is de®ned as VT V1 Vds =2 Vds 0:1 V), where V1 is the linear extrapolation from the point of maximum transconductance.
to their nominal values, as they have no eect on the bias points of interests. Thus, the number of the parameters that may be utilized to ®t the measurements is reduced to around 20. We have found, and experimentally veri®ed later, that a set of nine critical parameters is sucient to ®t the nine bias points. The nine critical parameters that result in minimum root mean square (RMS) of error were selected as follows. Instead of trying all possible parameter combinations, we simpli®ed the problem by categorizing these 20 parameters into three groups according to their physical meaning and the geometry to which they are most sensitive (Table 2). Then, three parameters are chosen from each group at a time, and they are used to ®t a small set of representative data generated using an advanced sampling technique, which will be described later. The set of parameters that produces minimum RMS is chosen and used in the subsequent optimization procedure. From this procedure, nine BSIM3 model parameters vth0, u0, a0, dvt0, pclm, lint, k3, b0, and wint were extracted and selected separately from their relevant geometries:
A complementary set of de®nitions can be set for PMOS devices. This data is typically measured on ®ve chips per wafer. On each chip, transistors of various geometries are measured, and NMOS and PMOS transistors having the following three geometries are considered: longchannel/wide-channel, short-channel/wide-channel, and short-channel/narrow-channel devices (e.g. see Table 1). They consist of two dierent channel lengths and two dierent channel widths. For the three data points (i.e. ION , b and VT ) of interest, there are nine measured data points for each die. A complete extraction of a BSIM3v3 model requires full I±V characterization of many transistors of varying geometries and body biases. Since we are only interested in the three MOSFET characteristics mentioned earlier, we may just extract a few critical BSIM3 model parameters that have the most impact on these device characteristics. To this end, we ®x the parameters associated with body bias eects to their nominal values since the body bias is zero in our measurements. Furthermore, the parameters aecting the drain current in the noncritical regions of operation (i.e., subthreshold region and transition region) can be ®xed
Table 1 NMOS and PMOS device geometries considered for the extraction of the critical BSIM3 model parameters MOS type
Long/ wide (lm)
Short/ wide (lm)
Short/narrow (lm)
NMOS PMOS
15/15 15/15
0.32/15 0.28/15
0.32/0.64 0.28/0.64
Geometry
Model parameters
Long/wide Short/wide
vth0, u0, vsat, a0 dvt0, dvt1, k1, pclm, ua, ub, pvag, ags, rdsw, nlx, lint dvt0w, dvt1w, k3, b0, b1, w0, wint
Short/narrow
1. vth0, u0 and a0 from long-wide device; 2. dvt0, pclm and lint from short-wide device; 3. k3, b0, and wint from short-narrow device. A general nonlinear least square optimization package available in SPLUS [17] is used. Finally, the nine parameters were optimized simultaneously to obtain minimum RMS error. On average, the sum of error squares is well below 10 12 , thereby suggesting that the model with the extracted parameters can match very closely the device performance at measured bias points. It should be pointed out that the approach developed is not restricted to these nine parameters selected, and other sets of parameters may be used to carry out the statistical simulation, as long as the parameters selected can provide an accurate playback of the MOS device characteristics. In other words, there is a ¯exibility in choosing the device model parameters, and the reason we selected the set of nine parameters is because it is an optimal set determined from our optimization process and it yields good accuracy. Fig. 2 shows excellent agreement between the simulated and the measured I±V
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Fig. 2. Comparison of I±V curves of NMOS and PMOS with three dierent geometries obtained from measurements (symbols) and simulated from BSIM3 model using the extracted critical parameters (lines).
characteristics of MOS devices having three dierent geometries. 3. Worst-case analysis and statistical simulation The product parametric yield is de®ned as the percentage of well functioning circuits that meet all design speci®cations, and can be estimated by using either the worst-case analysis or Monte Carlo simulation. In the worst-case analysis, the parametric yield is estimated by comparing the proposed performance boundary with the design speci®cation windows. In the Monte Carlo simulation, a number of ``random'' model samples is produced according to a certain statistical distribution and subsequently used in circuit simulations. If the number
of samples is suciently large, the parametric yield can be estimated by Yield
number of circuits whose y 2 X total number of circuit samples
1
where y represents circuit performances and X represent speci®cation window. 3.1. Worst-case analysis A conventional method to generate worst-case models used in industry is based on extraction from extensive measurements of devices with various sizes and temperatures on a sample wafer [10,18]. Next, worstcase polygons are speci®ed as ``fast'' or ``slow'' based on
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Fig. 3. Example showing qualitatively the worst-cases of NMOS and PMOS, using the six nonnominal device models.
skew corners of some electrical parameters, such as VT , b, and ION . A fast device has low VT , high b and high ION , whereas a slow device has high VT , low b and low ION . Correspondingly, the worst-case polygons consist of the following six device models in addition to the nominal model: N±N H±H L±L H±LT
L±HT HT±L LT±H
nominal NMOS and PMOS models fast NMOS and fast PMOS models slow NMOS and slow PMOS models fast NMOS model and corresponding slow PMOS model. This and the following three cases are intended to account for the global mismatch between NMOS and PMOS. slow NMOS model and corresponding fast PMOS model slow PMOS model and corresponding fast NMOS model fast PMOS model and corresponding slow NMOS model
Fig. 3 illustrates qualitatively the worst cases of VT and ION for NMOS and PMOS using the concept of the above mentioned six device models. Such an approach, while encapsulating information about correlation between n-type devices and p-type devices, completely neglects all other correlations. Furthermore, it provides no information on the probability of the worst-case corners. Here, we propose a method to select worst-case corners on a equidensity surface in the parametric test data space, taking into account all correlations between the parametric test data. The joint distributions of both the parametric test data can be determined using a multivariate v2 test [14]. It has been shown that, if y has an n-variate normal distribution with mean l and variance±covariance matrix R, then C y l0 R 1 y l is distributed as a v2 probability distribution with ndegree of freedom. We found that the multivariate normal distribution is a good approximation in our case, as
Fig. 4. The C y l0 R 1 y l distribution (Ð) of the standardized test data y as compared with the hypothesized v2 distribution (- - -). The solid line is the empirical probability distribution of the y l0 R 1 y l distribution, and the doted line is the hypothesized v2 distribution. The good agreement justi®es our assumption of multivariate normal distribution.
evidenced by the comparison of the distribution of standardized test data and v2 distribution shown in Fig. 4. Hence, the equal-density contours of the data and the parameter distributions can be visualized as hyperellipsoids. Using the PCA, the correlated device parameters can be eectively transformed to k uncorrelated components. If the device parameters are standardized to have zero mean and unit variance, the original 3r hyper-ellipsoid in device parameter space is now transformed to a k-dimensional hyper-sphere. We selected a set of worst cases by maximizing or minimizing device characteristics VT , b, and ION with the constrain of the parameters on the desired equal-density surface of the hyper-sphere, such as 3r surface. Thus, the optimization problem becomes:
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2
3 y1 6 y2 7 6 7 \max"F y 6 . 7 f p1 ; p2 ; . . . ; pm 4 .. 5 yn
where p R x;
x21 x22 x2k 3r2
2
where y is the vector of circuit performances, ``max'' stands for either minimizing or maximizing the corresponding yi simultaneously, p is the matrix of parametric test data VT , b and ION , R is the transformation matrix from PCA, x represents the principal components, and k 6 m. In our case, n and m are equal to 18, taking into account both NMOS and PMOS. In fact, Eq. (2) is a multiobjective optimization problem, which does not have a global solution. In some digital applications where one prominent circuit performance can be approximately modeled by the device characteristics VT , b and ION using regression analysis, the regression model can be used as a single objective function F(y) to be optimized. Then, a set of worst-case models can be selected for that particular application by optimizing the objective function. Thus, the problem can be expressed as: min F y w1 p1 w2 p2 with y f p R x;
1
w n pn 3
and jxj2 3r2 where y inside [ ] 1 is the objective needs to be maximized and weights wI are regression coecients. In our work, we took a dierent approach in which the worst-case corners were chosen from the equidensity data surface so that these corners span most of the measured device variations. In other words, the worstcase corners were extracted by optimizing certain cumulative probability (i.e., optimizing the proportion of devices satisfying certain speci®cations). For example, the ``fast'' case is de®ned as the model leads to fVT , b , ION g that maximizes
Fig. 5. Example of the grids of two principal components. Under equal-probability requirement, grid fB , D , F , H g are selected instead of fB, D, F , Hg. The grid O (0, 0) represents the nominal case.
to zero equal 0, otherwise x 9=u1=2 , where u is the number of x that are not zero. Suppose there are k principal components used and each component is quantized into three levels, then the worst cases are to be sought from 3k grids according to their corresponding de®nitions. A simple qualitative example with two principal components is given in Fig. 5. To further illustrate this quantitatively, we used seven principal components to model the corners of the test data measured in a month. As can be seen from Fig. 6, the ®rst
proportion VT n > VT n ; Ion n < Ion n ; b:n < b n ; VT p > VT p ; Ion p < Ion p ; b p < b p ; . . . 4 Eq. (4) incorporates joint cumulative proportion for all nine parametric test data. For computational eciency, we further simpli®ed the problem by quantizing the principal components x onto a ®nite grid. Note that the corners generated by simply combining these grids are not on the same equal-probability surface. Hence, the grid is chosen in the following fashion: 1) each component is ®rst quantized into three levels f 1; 0; 1g; and 2) in a combination f1; 0; . . . ; 1g, all x that corresponds
Fig. 6. Variance of one month of test data obtained from the principal component analysis, where seven principal components can explain more than 90% variance of the test data, and nine principal components can explain more than 95% variance of the test data.
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seven principal components explain more than 90% of the variance in the test data. From all those 37 combinations of the seven components, six worst-case models were selected. Fig. 7 shows the worst-case distributions obtained from the measured test data and simulated from the present worst-case model. For comparison, the results of the worst cases predicted from the existing method are also included in the ®gure. The existing worst-case model was generated by optimization of model parameters to make the model hits speci®ed (i.e., 95%) variations in the threshold voltage VT . The ellipses represent the 3r con®dence regions of the corresponding test data by assuming bivariate distribution. The unshaded poly-
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gons represent the device variation extent estimated by the existing worst-case model. The vertices of the shaded polygons are the projections of the proposed model on an equal-probability hyper-ellipse. As can be seen from the ®gure, the present worst-case models give a good indication for the range of device characteristics while capturing correctly the correlations, whereas the existing worst-case model grossly overestimates those cases. 3.2. Statistical simulation The goal of the statistical model is to generate a few but statistically sucient numbers of device models that can resemble the device statistics extracted from large
Fig. 7. Comparison of the variance region obtained from the proposed worst-case models (shaded polygons), the existing worst-case models (unshaded polygons), and 3r con®dence region (dashed ellipses) of the test data.
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keep a low variance of the estimator. An advanced sampling technique, LHS technique [15], was used in this study in order to reduce the number of simulation samples. The LHS technique has been successfully used in studies of simulating and modeling process variation to reduce simulation cost [9,10]. By using the LHS, we are able to use only a few tens of samples to achieve the same eect that would require hundreds of samples using simple random sampling. We applied the statistical models to a 0.25 lm CMOS process at Lucent Technologies. Test data was collected on 9000 die fabricated during one month from a single fabrication line, and analyzed using the principal component analysis. Then, each principal component was sampled using the LHS technique and transformed back to device data. Fig. 8 compares the measured and simulated distributions of the device characteristics. The
PMOS.lon
PMOS.Vt
sets of measurements. These device models, when implemented in circuit simulation, shall be able to predict the variance of circuit performance. Though much less ecient than the worst-case analysis, the statistical simulation renders quantitative and more precise information to circuit designers when the decision must be made to make appropriate tradeos between circuit performance and yield. As described previously, our statistical analysis is directly based on the statistics of the parametric test data, as discussed in Section 1 and shown in Fig. 1. To improve circuit simulation eciency, the sample of device models should be as few as possible while maintaining valid device statistics. In the conventional Monte Carlo simulation, each principal component is sampled using a simple random sampling technique. The simple random sampling requires a large number of samples to
NMOS.Vt
NMOS.lon
Fig. 8. Variance of MOS performance simulated from the present model using 100 sample data (dotted ellipses) and using 30 sample data (solid ellipses). Also shown are the distributions of the actual measured data (dashed ellipses).
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Fig. 9. Device variations predicted by the statistical model (solid lines) and obtained from measurements (bars and dashed lines) for two MOSFET devices with device geometries dierent from the ones considered in BSIM3 model parameter extraction.
dashed ellipses represent 3r con®dence regions of the test data, and the dotted and solid con®dence ellipses represent simulated MOS performance using 100 and 30 simulated samples, respectively. The results suggested that the number of samples can be as few as 30 while the simulated distribution still matches reasonably well with the measurements. Nonetheless, when the sample size becomes smaller, there are more chances to have spurious correlations between the principal components so that the distribution of the simulated data no longer matches the measured distribution. Special care must be taken to minimize the spurious correlation as much as possible. Thus, we were able to accurately represent the distributions of the test data with only a small number of simulated data. The transistor models derived from this approach can then be incorporated into circuit simulation. While the statistical model was developed based on the parameters extracted from the three MOS geome-
tries (see Section 1 and Table 1), it should provide good approximations for devices with other medium geometries as well. To verify this, we have shown in Fig. 9 the measured and simulated VT and ION distributions of NMOS having the geometries of 1=15 and 5=5 not considered in Table 1. Good agreement is found between the measured and simulated data. 4. Model applications in digital circuits To illustrate the applications in circuit design, the proposed worst-case model was applied to estimate the delay time bounds of two CMOS ring oscillator circuits. One circuit consists of 501 stages of inverters, and the other consists of 501 stages of NAND gates. In both circuits, the size (width/length) of the NMOS is 2.66/ 0.32, and the size (width/length) of the PMOS is 3.66/ 0.28. Figs. 10 and 11 show the histogram plots of the
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Fig. 10. Measured delay time spreads, and the delay time bounds predicted by the proposed and existing worst-case analyses for the 501 stage inverter ring oscillator. Fig. 12. Measured delay time distribution (bars and the dotted line) of a 501 stage inverter ring oscillator compared with the results of the statistical simulation (solid line). Both lines were obtained by ®tting with normal distribution. The upper and lower worst-case bounds are also shown.
Fig. 11. Measured delay time spread, and the delay time bounds predicted by the present and existing worst-case analyses for the 501 stage NAND ring oscillator.
circuit delay times measured from about 700 inverter ring oscillator circuits and NAND ring oscillator circuits, respectively. All transistors of the same channel type are assumed identical within a circuit, i.e. no intradie variation considered. Also included in the ®gures are the results obtained from the proposed and the existing worst-case models. Clearly, the proposed model generates more accurate bounds than the existing model, but the bounds obtained from the proposed model are still too wide compared to the measured values. This is due to the assumption of simple linear relation between parametric data and circuit performance used in the model development. Nevertheless, the model provides reasonable worst-case predictions and is useful for simple estimate of parametric yield in process monitoring and control. The delay time spreads of the two oscillators were also simulated using statistical simulation with 30 sample
Delay time of NAND Ring Oscillator (ps)
Fig. 13. Measured (bar and dotted line) delay time distribution of the 501 stage NAND ring oscillator circuit compared with the results of statistical model (solid line).
devices, as shown in Figs. 12 and 13. It is demonstrated that the statistical model is in good agreement with the measured delay time spread and gives much more quantitative and precise predictions than the worst-case analysis. Moreover, this is achieved with a minimal computation resource of only 30 sample devices. 5. Conclusions In summary, we have developed an ecient and practical statistical modeling approach based on the
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statistics of three parametric test data. While some particular parametric tests were used in this study, the modeling methodology applies generally to other parametric tests. Using this method, an improved worst-case analysis was developed by taking into account the data correlation and equal-probability constraints. An improved statistical model was also constructed using the combination of the PCA and the LHS technique to reduce the number of samples and thus the computation required. It was suggested that a sample size of 30±100 is sucient to represent the joint distribution of actual test data. The proposed worst-case and statistical models have been applied to a 0.25 lm CMOS technology. The delay time distributions of two ring oscillator circuits were measured and simulated. The results indicated that the present worst-case analysis compares more favorably with measurements than the existing ones. In addition, it was demonstrated that the statistical model developed compares favorably with measurements and provides more accurate, precise, and detailed information on the circuit performance spreads than the worstcase analysis.
[6] [7]
[8] [9]
[10] [11] [12]
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