MOSFET test structures for two-dimensional device simulation

.%/id-State Electronics Vol. 38, No. 1, pp.69-73, 1995

Pergamon

Copyright 0 1995 Elsevier Science Ltd Printed in Great Britain. All rights reserved

0038-1101(94)E0050-0

0038-l101195 $9.50+ 0.00

MOSFET TEST STRUCTURES FOR TWO-DIMENSIONAL DEVICE SIMULATION SAMAR SAHA Technology CAD, National Semiconductor Corporation, 2900 Semiconductor Drive, Santa Clara, CA 95052-8090, U.S.A. (Received

16 November

1993; in revised form 27 January 1994)

Abstract-This paper describes a quantitative methodology for the selection of simulation space and the generation of MOSFET mesh for two-dimensional device simulation. Simple mathematical expressions for the selection of two-dimensional device geometries are presented. A set of grid specifications was generated for simulation accuracy and computational efficiency of a device simulation program. These grid specifications were used in conjunction with the grid generation algorithm in the device simulation program MEDlCI to generate two-dimensional nMOSFET test structures of different channel lengths. A methodology to verify the robustness of the test structures is also described.

1. INTRODUCTION

2.

DEVICE DIMENSIONS

The selection of device dimensions is of utmost importance for accurate simulation of device characteristics. The main selection criteria are: (i) the selected geometries must model the real devices fabri-

The mathematical model for analysis of an arbitrary semiconductor structure consists of three partial differential equations (PDEs) describing the electrostatic potential (Y), the electron concentration (n), and the hole concentration (p)[l]. In a device simu-

cated in silicon and (ii) must be simple for computational efficiency. This can be achieved by selecting application specific test structures which accurately model the real devices and the physical processes in silicon for the desired device characteristics. An idealized Lightly Doped Drain (LDD) type MOSFET structure shown in Fig. 1 was used for the simulation of channel current and hot carrier effects[3]. In order to select the lateral dimension (x) of the simulation space, the appropriate layout design rules for the target technology was considered. Thus, the lateral dimension is given by:

lation program like MEDICI[2], these differential equations are discretized on a simulation grid to obtain solution for the variable set {Y, n,pj. The correct allocation of grid is crucial issue in device simulation. For simulation accuracy, the number of grid points (N) allocated in a test structure must be maximized. On the other hand, for computational efficiency, N must be minimized. Therefore, it is necessary to allocate fine grid in some regions of test structure and coarse grid in the regions where it is unnecessary. In addition, for accurate modeling of carrier flows the grid structure must accurately represent the real device. Incorrect grid structure will result in inaccurate prediction of device characteristics which in turn will provide inaccurate and unphysical device models. Thus, the generation of accurate mesh for device simulation is crucial for the successful applications of device simulation manufacturing programs in solving day-to-day problems. Ideally, a set of grid specifications are desirable to generate mesh for device simulation similar to the generation of layout design rules for device fabrication. This paper reports a systematic methodology to select two-dimensional device geometry and to create grid specifications for the generation of nMOSFET mesh for device simulation by using MEDICI. A procedure to verify the robustness of the generated mesh is also presented.

x =x,,+x,,+L+.Q+X,d,

(1)

where x,, and x,, are the source and the drain contact widths respectively, L is the drawn length of the poly gate, and xgs and xgd are the distances between the poly gate to the source and the drain contacts respectively (Fig. 1). In general, x,, = x,,, = x, and xgs= xgd= x2, and therefore, x is given by: x = L + 2(x, +x2).

(2)

The vertical dimension (0 was selected so that under the maximum operating bias the depletion region is contained within the structure. Ify,,,, is the maximum depth of the depletion region into the device under the maximum reverse bias between the drainsubstrate p-n junction, then [ is given by: i > 69

Yde,,

.

(3)

IQ

I

SAMARSAHA

/

/

-IPI

-

.

I

Channel

p- SUBSTRATE

Fig. 1. Two-dimensional cross-section of an idealized LDD type nMOSFET for device simulation. It,= width of the pinch-off region near the drain end of the device. x, and x, are the source and the drain contact widths respectively. The layout design rules, xgsand x8,,are the distances between the poly gate to the source and the drain contacts respectively. Vu, V,, Vs and VB are the biases applied to drain, gate, source and substrate respectively.

For nMOSFETs of the submicron technology under study, x2 = 1.05 pm and at the bias point (Vo, = Vu, = 5 V, Pa, = 0), ydcp,= 2.8 pm. Now, if we consider x, = 0.60 pm and L = 0.8 pm, then from eqn (2), x = 4.1 pm and from relation (3), we can consider [ = 3.0 pm for simulation of device characteristics under the biasing conditions Vos < 5 V and va, = 0. 3. GRID SPECIFICATIONS

The accuracy of the simulated device characteristics depends on the accurate representation of the input impurity profiles to the actual process technology. In this study, the input impurity profiles were generated by using the calibrated process models[rl,S] of the process simulation program SUPREM-3[6]. Then a set of grid specifications was created to reproduce these impurity profiles in the test structures for device simulation. The details procedure to create grid specifications for the generation of nMOSFET test structures of a submicron CMOS technology is described below. 3.1. Vertical grid (Y.GRID) Channel region: The overall grid allocation principle for the generation of MOSFET test structures for device simulation is primarily dependent on the distribution of the channel impurity profile. Figure 2 shows a typical impurity concentration (p) vs depth (r) plot of an nMOSFET channel region. It is seen from Fig. 2 that there is rapid variation in the concentration gradient (@/&) in the regions (a, A),

(b, B) and (c, C) of the impurity profile. In order to reproduce this profile accurately in the test structures for device simulation, fine Y.GRID must be allocated in these regions as long as the variation in 8pJdr is significant. In the regions where aplar approaches a constant value, relatively coarse grid will accurately reproduce the impurity distribution. Depending on the magnitude of variation in apjar, the values of Y.GRID allocated in the regions (a, A), (b, B) and (c, C) of the test structures were 200, 500 and 1000 A respectively. For depth > 1.65 pm, ap/& + const. and therefore, a uniform Y.GRID = 1500 A was allocated in the region beyond C of the test structures. Again, for accurate device simulation the PDEs must be solved in the inversion layer of MOSFETs. Therefore, fine Y.GRID < the width of the inversion layer (yin,) must be allocated from the gate oxidesilicon interface to a depth y > yinY of MOSFETs. Since Yin”o 30 A[7], a uniform Y.GRID = 12 A was allocated from the gate oxide-silicon interface to a depth y = 60 A. Thus, the vertical grid specifications in the most critical regions of the n MOSFET channel represented by the impurity distribution shown in Fig. 2 are given by: Y.GRID = 12 A,

for 0 > y 2 yin”,

Y.GRID = 200 A,

for Y, >y

>

Y.GRID = 500 A,

for y&>y

>YBt

Y.GRID = 1000 A,

for y, > y 2 y,-,

(7)

Y.GRID = 1500 A,

for y 2 y,-,

(8)

YAP

(4) (5) (6)

where y,, y,, y,, y,, y, and y, are the values of y at the locations represented by the points a, A, b, B, c and C of the impurity distribution in Fig. 2 respectively. In the regions (Yin,, Y,), (YA, Yb) and (YB, Y,) of the channel where ap/dr - const., the variable grid generation parameter (RATIO) in MEDIC1 could be

l”k-v

3.00 Depth

(Microns)

Fig. 2. A typical one-dimensional SUPREMImpurity distribution of an nMOSFET channel region. The regions between the points (a, A), (b, B) and (c, C) represent the regions of the rapid variation in the concentration gradient. The one-dimensional MEDIC1 impurity profile along the channel is superimposed for comparison.

Test structure for 2D MOSFET simulation used to extend the Y.GRID by specifying appropriate values of 1.5 > RATIO > 1 to avoid sudden change in grid spacings in the test structures. In order to create a general set of grid specifications, uniform grids were used in this study. Thus, Y.GRID = 500 A was used from y, to y,. Then, the expression (6) can be expressed as: Y.GRID = 500 A,

for y, > y > y,.

(9)

In the region, yi,, < y < y, near the inversion layer of MOSFETs, the grid specification used is given by: Y.GRID = 70 A,

for yin” < y < y,.

(10)

In Fig. 2, the MEDIC1 generated impurity profile is also superimposed on the SUPREMimpurity profile showing that the SUPREMprofile is accurately reproduced in the test structure. Source-drain regions: The value of threshold voltage (Vru) of advanced MOSFETs depends on the LDD junction depth (yj) of the sourcedrain region[8]. Therefore, the sourcedrain impurity distributions and the locations of the junctions must be accurately reproduced in the test structures for device simulation. For the target technology, the sourcedrain junctions were formed with the impurity profile in Fig. 2 in the region between the points (A, b). Following the grid allocation procedure in the channel region, it is found that Y.GRID = 250 A was necessary for accurate representation of the sourcedrain impurity distribution in the nMOSFET test structures. This can be represented by: Y.GRID = 250 A,

for 0 > y > yb.

(11)

Again, from Fig. 2 and relation (5) it is seen that Y.GRID = 200 A was necessary for accurate representation of the channel impurity profile from y, to y, . Therefore, for simplicity of grid allocations in the entire structure, Y.GRID = 200 A was also used in the source-drain regions of the test structure for y, 3 y > y,. This can be represented by: Y.GRID = 200 A,

for y, > y > y,.

(12)

For y yb, the same values of Y.GRID were used in both the channel and the source-drain regions of the test structures. In addition, vertical nodes were allocated at the locations yj and Yj, and the REGRID statement in MEDIC1 was used for accurate representation of the sourccdrain junctions in the test structures. Here Y, denotes the junction depth of the heavily doped sourcedrain region. Thus, the vertical grid specifications for the generation of n MOSFET test structures of the target submicron technology for 0 < x < x can be represented by:

SSE3811-F

Y.GRID = 12 A,

forO>y

Y.GRID = 70 A,

for&

a_Vi”,* <.Y <.Y,,

71

Y.GRID = 200 A,

fory, >y >Y,,

Y.GRID = 500 A,

fory,>y

Y.GRID = 1000 A,

for y, > y 2 yc,

Y.GRID=

a~,,

15OOA, for y,,
<{.

(13)

3.2. Lateral grid (X.GRID) Channel region: In MOSFET test structures for device simulation, the locations of the source-drain lateral junctions must be reproduced accurately for accurate prediction of channel current. In addition, the width of the pinch-off region (I,,) near the drain end of MOSFETs must be determined accurately for accurate prediction of I-V characteristics at saturation[9, lo]. Therefore, by assuming lateral diffusion same as the vertical diffusion, fine X.GRID must be allocated from the left edge of the poly gate to a distance x 2 y, in the channel region near the source end of MOSFETs and, line X.GRID must be allocated from the right edge of the poly gate to a distance x > y, + 1, near the drain end of the channel. It is seen from the expression (11) that Y.GRID = 250 A was necessary for accurate representation of the source-drain vertical impurity distribution, therefore, X.GRID = 250 A was allocated from the left edge of the poly gate to x > yj near the source end and from the right edge of the poly gate to x 2 x, + I, near the drain end of the channel region respectively. The lateral grid in the remaining channel region was allocated so that the occurrence of obtuse triangles was minimized. Since obtuse triangles cause unphysical spikes in the solution with disastrous effects on convergence rate[l], the occurrence of obtuse triangles was minimized by allocating X.GRID z Y.GRID. It is seen from Fig. 2 that for accurate representation of the impurity distribution in the channel region, Y.GRID < 500 A was used for 0 > y 2 ye. Therefore, a uniform X.GRID = 500 A was used in the channel region from the oxide-silicon interface to a depth y > y,. Thus, the lateral grid specifications in the channel region for 0 > y 2 yB can be represented by: X.GRID = 250 A, for (x,, + xgs) 2 x 2 (x,, + xgs+ ,; L

(14)

X.GRID = 500 A, for (& + Xgs+

yj)

<

X <

(X,,

+

Xg, +

L

-

.I’, -

I, ),

(15) X.GRID = 250 A, for

(Xc, +

Xgs +

L

-

yj -

I,)

2 X 2

(Xc, +

Xgs +

L 1. (16)

For the target submicron technology, y, g 0.25 pm and lr = 0.14 pmm[9,IO], therefore, X.GRID = 250 A was allocated from the left edge of the poly gate to x = 0.4 pm in the channel region near the source end,

72

S~ht4R SAHA

and X.GRID = 250 A was allocated from the right edge of the poly gate to x = 0.5 pm in the channel near the drain end of the structures. The depth of X.GRID < 500 A was extended to y = 0.5 pm. Source-drain regions: The lateral grid in the source-drain regions of the test structures was allocated to minimize the occurrence of the number of obtuse triangles in the mesh. Since in the source-drain regions Y.GRID < 500 A was used for 0 > y > y,, and X.GRID = 500 8, was allocated in the channel region, therefore, for simplicity of grid allocation in the complete structure, X.GRID = 500 A was also used in the source-drain regions of the test structures. Then, the lateral grid specifications in the source-drain regions for 0 > y > y, can be represented by: X.GRID = 500 A,

for 0 < x < (x,, + x,,).

X.GRID = 500 A,

for (x,, + .xga+ L) < x < x. (18)

(17)

Thus, for 0 > y > 0.5 pm ( - yB), the expressions (14)-(18) represent the complete set of the lateral grid specifications for the generation of nMOSFET test structures of the target submicron technology. For computational efficiency of MEDICI. coarse lateral grid was allocated for 0.5 pm
0.00

1.00

4. FINAL

The above grid specifications were used to generate nMOSFET test structures by using MEDICI. Figure 3 shows the test structure for an L = 0.8 pm nMOSFET. The total number of grid points generated in the mesh was 3737 and the number of obtuse triangles occurred was 1.3% of the total grid points. The typical computation time for the simulation of a typical I-V curve of the device in IBM RS6000 Model 980 workstation was about 7min. It is seen from Fig. 3 that the fine Y.GRID = 12A at the oxide-silicon interface was not eliminated from the source-drain regions of the test structure. This is because the additional nodes do not make any significant change in the computation time. The fine grids in the gate oxide region, shown in Fig. 3, were allocated for accurate simulation of gate oxide capacitance. In order to determine the robustness of the generated test structures, MEDIC1 was used to generate Z-V characteristics of the structures by varying the grid specifications in the most sensitive regions of the devices. The I-V characteristics for L = 0.8 pm nMOSFETs (Fig. 4) shows the sensitivity of Y.GRID at the gate oxide-silicon interface. It is seen from Fig. 4 that for Y.GRID d 200 8, the magnitude of

2.00

Distance

MESH AND ROBUSTNESS

3.00

4.00

(Microns)

Fig. 3. Final mesh for Lightly Doped Drain type nMOSFETs of L = 0.8 ilrn and gate oxide thickness = 150 A generated

by MEDICI. The total number of grid points generated in the structure number of obtuse triangles generated = 1.3% of total grid points.

= 3737 and the

Test structure for 2D MOSFET simulation 0.020 -

0 Measurement

. -

0

Y.GRID = 12 A

.“.... Y.GRID = 35 A 2

0.015

-

-----’ Y.GRID I 100 A

.

.‘-‘... Y.GRID = 140 A z t 2 u

---‘Y.GRID=2OOA -

O.OlO- -

Y.GRID = 250 A Y.GRID = 300 A

.9 d

0.005-

0.0004---~ 0

. 1

1 1 . 2 3 Gate Voltage (V)

1 4

5

0

1

2 Gate Voltage

4

3

5

(V)

Fig. 4. Plot of I,, vs Vo, for LDD type nMOSFETs of L = 0.8 pm, W = 40 pm and gate oxide thickness = 150 A with different Y.GRID in the inversion layer of the channel keeping all other grid specifications the same. The simulated data were obtained by two-dimensional device simulation program MEDICI. All data were obtained under V, = V, = 0 and V, = 5 V.

Fig. 5. Plot of I,, vs V,, for LDD type nMOSFETs of L = 0.8 pm, W = 40 pm, and gate oxide thickness = 150 A with different X.GRID in the channel region keeping all other grid specifications the same. The simulated data were obtained by two-dimensional device simulation program MEDICI. All data were obtained under V, = VB = 0 and v,=sv.

the channel current attains a maximum value and the electrical characteristics become insensitive to the values of Y.GRID at the surface. Figure 4 also shows that the magnitudes of the measured and the simulated data agree very well for Y.GRID < 200 A.. Thus, Y.GRID = 12 A at the surface near the gate oxide-silicon interface generates robust test structures for device simulation. Figure 5 shows the simulated Z-V characteristics for L = 0.8 pm nMOSFETs as a function of X.GRID in the channel region. It is also seen from Fig. 5 that for X.GRID Q 300 A, the magnitude of the channel current attains a maximum value and the device characteristics are independent of X.GRID. It is obvious from Fig. 5 that the simulated and the measured electrical data are in close agreement for X.GRID < 300 A. Thus, X.GRID = 200 A used in this study reduces the uncertainty in the simulated electrical characteristics due to incorrect grid allocations and generates robust test structures for device simulation.

devices. For simulation accuracy and computational efficiency, fine grid was allocated only in the regions of most physical importance. The procedure to verify the robustness of the generated mesh by studying the electrical behavior as a function of grids tiinimizes the probable errors in the simulated data due to incorrect grid allocation, and therefore, provides an accurate calibration of the fundamental material parameters for device simulation. Acknowledgements-Grateful Gadepally and Dr C. S. Yeh encouragements and support Development Technology are

REFERENCES

A quantitative methodology is developed to obtain a set of grid specifications for the generation of application specific nMOSFET test structures for device simulation. The basic idea is similar to the generation of layout design rules for device fabrication. The simulation space was selected so that the test structures accurately model the real silicon

Rafferty, M. R. Pinto and R. W. Dutton, IEEE Trans. Electron Devices ED-30, 2018 (1983). TMA MEDICI, Version 1. Technology Modeling Associates Inc., Palo Alto (1992). W. Fichtner, D. J. Rose and R. E. Bank, IEEE Trans. Electron Devices ED-30, 1018 (1983). S. Saha, C. S. Yeh and B. Gadepally, Solid-St. Electron. 36, 1429 (1993). S. Saha, C. S. Yeh and B. Gadepally, Proc. Int. Electron Devices and Materials Symp. pp. 68-71. National

1. C. S.

2. 3. 4.

5. CONCLUSION

thanks are due to Mr B. for valuable discussions. The of the Office of the Product also gratefully acknowledged.

5.

Taiwan University, Taipei (1992). 6. TMA SUPREM-3, Version 6. Technology Modeling Associates, Inc., Palo Alto (1993). 7. P. M. Solomon, Proc. IEEE 70, 489 (1982). 8. L. D. Yau, Solid-St. Electron 17, 1059 (1974). 9. S. Saha, CAD for IC’s-Process, Device, Circuits, and Virtual Factory-Industrial use of TCAD. Stanford Univ. (1993). 10. S. Saha, Solid-St. Electron. 37, 1786 (1994).