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device simulation of MOSFET characteristics
0038-1101182/03M01~3sO3.00/0 0 1982 Pergamon Press Ltd.
Soli&St~fc Eleclmnics Vol. 25. No. 3. pp. 201-203, 1982
Printed in Great Britain
APPLICATION OF FLETCHER-POWELL’S OPTIMIZATION METHOD TO PROCESS/DEVICE SIMULATION OF MOSFET CHARACTERISTICS KIYOYUKIYOKOYAMA, AKIRA YOSHII, TOHRU ADACHI and RYOTA KASAI
Musashino Electrical Communication Laboratory, Nippon Telegraph and Telephone Public Corporation, Musashino-shi, Tokyo, 180,Japan (Received 9 June 1981) Al&a&-This paper proposes a process/device optimization technique which is well suited for determining outimum orocess conditions for MOSFETs. After lit&inn urocess simulator SUPREM II and device simulator FEDAS, process conditions which realize desirable de&e performance can be obtained by introducing the optimizatiom procedure. The Fletcher-Powell method, one of the most efficient optimization techniques now available, is applied to the present simulator. The validity of the algorithm is successfully demonstrated by the determination of channel doping conditions, such as implanted boron dose and annealing temperature. The present simulator is expected to be an important tool for device design.
1. INTRODUCTION
parameters can be performed
Device simulators have recently become an indespensable tool for device design. General purpose device simulators [l, 21 and FEDAS (Field Effect Device Analysis System)[3], which is very effective for use with MOSFETs, have been developed. If the device structure is closely related to fabrication process simulator, it would be possible to design desired device performance through optimized fabrication process and device structure . A process simulator SUPREM II [4] has been reported as a very efficient tool to simulate device structure through various fabrication processes. The FEDAS and SUPREM linkage is considered to make the overall device and process optimization possible. To make use of the SUPREM II which adopts one-dimensional model, it is assumed that MOSFETs are divided into three regions, source, channel and drain. By applying SUPREM II to these three regions, one-dimensional impurity profiles can be obtained in each region. Pseudo-two-dimensional impurity profiles can be synthesized from these results. Present simulator is valid in the case of not so short channel devices, as lateral spread being taken into account by rotation at the mask edge. After such treatment, the two-dimensional device simulator FEDAS can analyze device performance. Process parameters have usually been modified in a manner which depends on the engineer’s intuition and experience, until the difference between actual and desired characteristics is reduced below some tolerance level. A way to arrange process conditions that brings about desired device performance realization can be automatically obtained by introducing an optimization procedure [5]. The Fletcher-Powell method [6], commonly used in circuit design, one of the most efficient optimization techniques, is applied to the present simulator. The numerical calculation of the Jacobian matrix for a few 201
practically
owing to the
progress in the computer facilities. This paper is concerned with these recent developments in computational capability, for simplification the discussion being restricted to channel doping conditions, proposes a new approach to the process/device optimization method. 2. PROCESS OFTIMIZATION SIMULATOR Figure
1 shows a flow chart for the present optimization simulator. The least-squares performance function can be written as f =
T
((Xi
-
4)
’ WiY7
(1)
where xi is the analyzed device performance such as threshold voltage characteristics corresponding to the design goal $, and wi is a weighting function. In the present paper, device performance is determined by the IDS vs V,, characteristics in MOSFETs, which are very important figures for discussing threshold voltage and sub threshold characteristics. Therefore, eqn
m Fig. 1. Present simulator flow chart.
202
K. YOKOYAMAet
al.
(1) can be concretely represented as
Table 1. Device design parameters Effective
f = c ((MP)
- i;,
(2)
. W”)‘.
Oxide
Channel
(3)
q = In (P).
We wish to find an iterative scheme for altering initial parameters. After the ith.iteration, the estimate of the vector is qi+l = qi + Aqi.
(4)
Here, considering the Taylor series expansion of the performance function about q, the gradient of the performance function with respect to all designable parameters can be numerically calculated by the following equation
=c
W,,(P)
- Zz9,~
K
aLxw/aP~
Pi
2.0 pm 35 nm
1015cn-3
Density
Substrate
Here, Zzs represents the design goal already simulated by the known process conditions in order to demonstrate the validity of the present simulator. In the following discussion, attention is focused on the channel doping conditions, such as implanted boron dose a$ annealing temperature in order to realize the same Z,, vs VGs characteristics. The problem at hand is to find the optimum values of designable process parameters p, that is, those values which result in a minimum value for the performance function defined in eqn (2). The parameters can be transformed into logarithms in order to improve the convergence rate and to conserve the initial condition sign, in such a manner that
Length
Thickness
Junction
Depth
Implanted
pm
0.20
Boron (dose)
5.0 x
(energy)
15 Ke"
lOI1 atoms/cm2
Anealing (temperature)
1000
(time)
20
"C
minutes
teristics calculated from the channel doping condition listed in Table 1. Figure 2 indicates the result of the iteration process for the performance function, and the determination of the implanted dose value. The final dose value, 4.9999 x 10” atoms/cm*, was successfully found for the initial value of 4.0 x 10” atoms/cm*. The present simulator was also effective with respect to annealing temperature, time and implanted dose energy. Figure 3 indicates the CPU time dependence on the initial value in the case of annealing temperature determination. It can be seen from the figure that the solution convergency is guaranteed from the initial value of 820°C to that of 14oo”C, and that the CPU time also closely depends on initial value. The engineer can easily predict initial value in this temperature range.
(5)
I i
\
I I
\, The multidimensional minimization techniques just described can be reduced to a search for the minimization of the performance function along a given direction s. Therefore, parameters can be updated by a onedimensional search along si after the ith iteration, so that pi+l = pi . exp (ai sJ.
-10
/
‘\.
1
0
I
2
3
4
5
4o
6
Iteration Fig. 2. Dose value and performance for a one-parameter
function iteration process problem.
(6)
Davison’s cubic interpolation[7] is employed for onedimensional search. The optimum process simulator consists of the above mentioned optimization procedure, as a supervisor, and the process/device analysis program. 3. RESULTS AND DISCUSSIONS The present process/device optimization simulator was applied to MOSFETs in order to demonstrate the validity of the algorithm. Considering the limitation for short channel effects, typical device design parameters were selected as shown in Table 1. As the simplest example, a one parameter problem was looked at. The design goals are IDS vs VGs charac-
=:
l
$lO-
d 3
1
'\
E F
./ Desi
2 5-
nGoal
‘\
,
7, 0
800
1000 lmtd
1200 Temperature
,
, 1400 ( lC )
Fig. 3. CPU time dependence on initial value in the case of annealing temperature determination.
203
Simulation of MOSFET characteristics Table 2. Optimization results Initial Boron
dose
Temperature
4.0
Value x
1011
960
Final 4.9975
Value +
Fig. 4. IDS vs V,, characteristics. (a) Initial conditions (dose, 4 x IO” cm*; temperature, %O”C). (b) Design goal conditions (dose, 5 x 10” cm-*; temperature, IWC).
A second,
two-parameter problem, implanted dose value and annealing temperature, was also considered. Drain current calculated by the initial conditions was about one order of magnitude more than the results
obtained by the design goal conditions as shown in Fig. 4. Table 2 shows the optimization results and Fig. 5 indicates the iteration process for this problem. The
results gave good evidence of the suitability of the present simulator. Coupling the FEDAS with a two-dimensional process simulator[S], instead of SUPREM II, enables the discussion on factors down to short channel devices. The Jacobian matrix of the variable with respect to all parameters was calculated numerically. Therefore, computational time rapidly increases with parameter increase. There is also the risk involving the search local minimum value in the case of all process parameters decision. From a practical point of view, however, the present simulator is expected to be a very efficient tool for process/device optimum design through the development of array processors and so on. 4. SUMMARY
A process/device optimization simulator has been developed. As a result of this development, it is now possible to obtain optimum process conditions for realizing desired device performance, which is less dependent upon the engineer’s capability or work load.
atoms/cm2
999.2
OC
0
q!i+e-& Gate Voltage(V)
Units
1011
2
4
6
8
10
12
Iteration Fig. 5. Iteration process for performance function, and implanted dose value and annealing temperature.
The Fletcher-Powell method was introduced as the optimization technique, Application of the present simulator to channel doping conditions for MOSFETs, such as implanted boron dose and annealing temperature, demonstrated the validity of the algorithm. Although problems involving increased computational time and instability in multidimensional search still remain to be solved, it was confirmed that the present simulator was effective for optimum process control of LSI devices.
Acknowledgements-The authors are grateful to Dr. M. Watanabe, Dr. T. Sudo and Dr. S. Horiguchi for their encouragement and guidance throughout this study, and to Dr. M. Tomizawa for valuable technical discussions. RRFERRNCFS
1. T. Adachi, A. Yoshii and T. Sudo, lf?Ef? Trans. Electron Dev., ED-X, 1026(1979). 2. A. Yoshii, S. Horiguchi and T. Sudo, Tech. Digest of ISSCC, p. 80 (1980). 3. K. Yokoyama, A. Yoshii and S. Horiguchi, IEEE Trans. Elecrron Deu., ED-27, 1509(1980). 4. D. A. Antoniadis, S. E. Hansen and R. W. Dutton, Stanford Uniuersify Tech. Rep., SEL-78-020,Stanford Electronics Laboratories.(1978). 5. S. W. Director,IEEE Trans. Cir. Theory, CT-l& 3 (1971).
6. R. Fletcher and M. J. D. Powell, Comput. J., 6, 163(l%3). 7. W. C. Davidon, AEC Res. Develop. Rep. ANL-5990 revised (1959). 8. B. R. Penumalli, Tech. Digest oflSSCC, p. 213 (1981).
Soli&St~fc Eleclmnics Vol. 25. No. 3. pp. 201-203, 1982
Printed in Great Britain
APPLICATION OF FLETCHER-POWELL’S OPTIMIZATION METHOD TO PROCESS/DEVICE SIMULATION OF MOSFET CHARACTERISTICS KIYOYUKIYOKOYAMA, AKIRA YOSHII, TOHRU ADACHI and RYOTA KASAI
Musashino Electrical Communication Laboratory, Nippon Telegraph and Telephone Public Corporation, Musashino-shi, Tokyo, 180,Japan (Received 9 June 1981) Al&a&-This paper proposes a process/device optimization technique which is well suited for determining outimum orocess conditions for MOSFETs. After lit&inn urocess simulator SUPREM II and device simulator FEDAS, process conditions which realize desirable de&e performance can be obtained by introducing the optimizatiom procedure. The Fletcher-Powell method, one of the most efficient optimization techniques now available, is applied to the present simulator. The validity of the algorithm is successfully demonstrated by the determination of channel doping conditions, such as implanted boron dose and annealing temperature. The present simulator is expected to be an important tool for device design.
1. INTRODUCTION
parameters can be performed
Device simulators have recently become an indespensable tool for device design. General purpose device simulators [l, 21 and FEDAS (Field Effect Device Analysis System)[3], which is very effective for use with MOSFETs, have been developed. If the device structure is closely related to fabrication process simulator, it would be possible to design desired device performance through optimized fabrication process and device structure . A process simulator SUPREM II [4] has been reported as a very efficient tool to simulate device structure through various fabrication processes. The FEDAS and SUPREM linkage is considered to make the overall device and process optimization possible. To make use of the SUPREM II which adopts one-dimensional model, it is assumed that MOSFETs are divided into three regions, source, channel and drain. By applying SUPREM II to these three regions, one-dimensional impurity profiles can be obtained in each region. Pseudo-two-dimensional impurity profiles can be synthesized from these results. Present simulator is valid in the case of not so short channel devices, as lateral spread being taken into account by rotation at the mask edge. After such treatment, the two-dimensional device simulator FEDAS can analyze device performance. Process parameters have usually been modified in a manner which depends on the engineer’s intuition and experience, until the difference between actual and desired characteristics is reduced below some tolerance level. A way to arrange process conditions that brings about desired device performance realization can be automatically obtained by introducing an optimization procedure [5]. The Fletcher-Powell method [6], commonly used in circuit design, one of the most efficient optimization techniques, is applied to the present simulator. The numerical calculation of the Jacobian matrix for a few 201
practically
owing to the
progress in the computer facilities. This paper is concerned with these recent developments in computational capability, for simplification the discussion being restricted to channel doping conditions, proposes a new approach to the process/device optimization method. 2. PROCESS OFTIMIZATION SIMULATOR Figure
1 shows a flow chart for the present optimization simulator. The least-squares performance function can be written as f =
T
((Xi
-
4)
’ WiY7
(1)
where xi is the analyzed device performance such as threshold voltage characteristics corresponding to the design goal $, and wi is a weighting function. In the present paper, device performance is determined by the IDS vs V,, characteristics in MOSFETs, which are very important figures for discussing threshold voltage and sub threshold characteristics. Therefore, eqn
m Fig. 1. Present simulator flow chart.
202
K. YOKOYAMAet
al.
(1) can be concretely represented as
Table 1. Device design parameters Effective
f = c ((MP)
- i;,
(2)
. W”)‘.
Oxide
Channel
(3)
q = In (P).
We wish to find an iterative scheme for altering initial parameters. After the ith.iteration, the estimate of the vector is qi+l = qi + Aqi.
(4)
Here, considering the Taylor series expansion of the performance function about q, the gradient of the performance function with respect to all designable parameters can be numerically calculated by the following equation
=c
W,,(P)
- Zz9,~
K
aLxw/aP~
Pi
2.0 pm 35 nm
1015cn-3
Density
Substrate
Here, Zzs represents the design goal already simulated by the known process conditions in order to demonstrate the validity of the present simulator. In the following discussion, attention is focused on the channel doping conditions, such as implanted boron dose a$ annealing temperature in order to realize the same Z,, vs VGs characteristics. The problem at hand is to find the optimum values of designable process parameters p, that is, those values which result in a minimum value for the performance function defined in eqn (2). The parameters can be transformed into logarithms in order to improve the convergence rate and to conserve the initial condition sign, in such a manner that
Length
Thickness
Junction
Depth
Implanted
pm
0.20
Boron (dose)
5.0 x
(energy)
15 Ke"
lOI1 atoms/cm2
Anealing (temperature)
1000
(time)
20
"C
minutes
teristics calculated from the channel doping condition listed in Table 1. Figure 2 indicates the result of the iteration process for the performance function, and the determination of the implanted dose value. The final dose value, 4.9999 x 10” atoms/cm*, was successfully found for the initial value of 4.0 x 10” atoms/cm*. The present simulator was also effective with respect to annealing temperature, time and implanted dose energy. Figure 3 indicates the CPU time dependence on the initial value in the case of annealing temperature determination. It can be seen from the figure that the solution convergency is guaranteed from the initial value of 820°C to that of 14oo”C, and that the CPU time also closely depends on initial value. The engineer can easily predict initial value in this temperature range.
(5)
I i
\
I I
\, The multidimensional minimization techniques just described can be reduced to a search for the minimization of the performance function along a given direction s. Therefore, parameters can be updated by a onedimensional search along si after the ith iteration, so that pi+l = pi . exp (ai sJ.
-10
/
‘\.
1
0
I
2
3
4
5
4o
6
Iteration Fig. 2. Dose value and performance for a one-parameter
function iteration process problem.
(6)
Davison’s cubic interpolation[7] is employed for onedimensional search. The optimum process simulator consists of the above mentioned optimization procedure, as a supervisor, and the process/device analysis program. 3. RESULTS AND DISCUSSIONS The present process/device optimization simulator was applied to MOSFETs in order to demonstrate the validity of the algorithm. Considering the limitation for short channel effects, typical device design parameters were selected as shown in Table 1. As the simplest example, a one parameter problem was looked at. The design goals are IDS vs VGs charac-
=:
l
$lO-
d 3
1
'\
E F
./ Desi
2 5-
nGoal
‘\
,
7, 0
800
1000 lmtd
1200 Temperature
,
, 1400 ( lC )
Fig. 3. CPU time dependence on initial value in the case of annealing temperature determination.
203
Simulation of MOSFET characteristics Table 2. Optimization results Initial Boron
dose
Temperature
4.0
Value x
1011
960
Final 4.9975
Value +
Fig. 4. IDS vs V,, characteristics. (a) Initial conditions (dose, 4 x IO” cm*; temperature, %O”C). (b) Design goal conditions (dose, 5 x 10” cm-*; temperature, IWC).
A second,
two-parameter problem, implanted dose value and annealing temperature, was also considered. Drain current calculated by the initial conditions was about one order of magnitude more than the results
obtained by the design goal conditions as shown in Fig. 4. Table 2 shows the optimization results and Fig. 5 indicates the iteration process for this problem. The
results gave good evidence of the suitability of the present simulator. Coupling the FEDAS with a two-dimensional process simulator[S], instead of SUPREM II, enables the discussion on factors down to short channel devices. The Jacobian matrix of the variable with respect to all parameters was calculated numerically. Therefore, computational time rapidly increases with parameter increase. There is also the risk involving the search local minimum value in the case of all process parameters decision. From a practical point of view, however, the present simulator is expected to be a very efficient tool for process/device optimum design through the development of array processors and so on. 4. SUMMARY
A process/device optimization simulator has been developed. As a result of this development, it is now possible to obtain optimum process conditions for realizing desired device performance, which is less dependent upon the engineer’s capability or work load.
atoms/cm2
999.2
OC
0
q!i+e-& Gate Voltage(V)
Units
1011
2
4
6
8
10
12
Iteration Fig. 5. Iteration process for performance function, and implanted dose value and annealing temperature.
The Fletcher-Powell method was introduced as the optimization technique, Application of the present simulator to channel doping conditions for MOSFETs, such as implanted boron dose and annealing temperature, demonstrated the validity of the algorithm. Although problems involving increased computational time and instability in multidimensional search still remain to be solved, it was confirmed that the present simulator was effective for optimum process control of LSI devices.
Acknowledgements-The authors are grateful to Dr. M. Watanabe, Dr. T. Sudo and Dr. S. Horiguchi for their encouragement and guidance throughout this study, and to Dr. M. Tomizawa for valuable technical discussions. RRFERRNCFS
1. T. Adachi, A. Yoshii and T. Sudo, lf?Ef? Trans. Electron Dev., ED-X, 1026(1979). 2. A. Yoshii, S. Horiguchi and T. Sudo, Tech. Digest of ISSCC, p. 80 (1980). 3. K. Yokoyama, A. Yoshii and S. Horiguchi, IEEE Trans. Elecrron Deu., ED-27, 1509(1980). 4. D. A. Antoniadis, S. E. Hansen and R. W. Dutton, Stanford Uniuersify Tech. Rep., SEL-78-020,Stanford Electronics Laboratories.(1978). 5. S. W. Director,IEEE Trans. Cir. Theory, CT-l& 3 (1971).
6. R. Fletcher and M. J. D. Powell, Comput. J., 6, 163(l%3). 7. W. C. Davidon, AEC Res. Develop. Rep. ANL-5990 revised (1959). 8. B. R. Penumalli, Tech. Digest oflSSCC, p. 213 (1981).