Solid-State Electronics Vol. 36, No. 5, pp. 749-151, 1993
0038-I lOI/
FURNACE
N,O OXIDATION PROCESS FOR MOSFET DEVICE APPLICATIONS
HYUNSANG HWANG’,
$6.00 + 0.00
Copyright 0 1993 Pergamon Press Ltd
Printed in Great Britain. All rights reserved
SUBMICRON
MING-YIN
HAO’, JACK LEE’, VIJU MATHEWS*,PIERRE C. FAZAN* and CHUCK DENNI~~N* ‘Microelectronics Research Center, The University of Texas at Austin, TX 78712 and *Micron Technology, Inc., Boise, ID 83706, U.S.A. (Received 25 July 1992; in revised form
18 November
1992)
Abstract-The mobility and reliability characteristics of submicron nMOSFETs with oxynitride gate dielectric of various oxide thicknesses (SO, 80 and 120 A), and oxidation temperatures (907, 957 and 1057°C) grown in a conventional furnace have been investigated. Oxynitride gate devices show higher mobility than that of control oxide devices under high normal field. The oxynitride devices exhibit much less degradation (AG,/G, and AV,) under channel hot-electron stress. Based on lifetime extrapolation, non-LDD MOSFETs using this new oxynitride dielectrics are predicted to have lifetime substantially longer than 10 years under 3.3 V operation.
I.
INTRODUCEION
devices prepared at higher temperature (1057°C) exhibit over two orders of magnitude longer lifetime than that of control oxide.
Scaling of VLSI devices down to the submicron regime requires better quality gate dielectrics than conventional thermally grown oxide. We have reported the excellent characteristics of new oxynitride gate dielectrics grown in N,O using rapid thermal processing [l-3]. The oxidation in N,O shows significantly lower oxidation rate with increasing time, thus better control in oxide thickness especially in the thin thickness region (< lOOA). Compared with conventional rapid thermally grown oxide, the new oxynitride dielectrics show very large charge-tobreakdown, lower charge trapping, and interface state generation under constant current stress and X-ray irradiation. The oxynitride also exhibits excellent diffusion barrier to dopant (BF,) for dual gate CMOS application. AES nitrogen depth profile shows nitrogen pile-up (~3 at. %) at the Si/SiO, interface, which is believed to be responsible for the improved integrity of oxynitride dielectric. Although rapid-thermal processing is a promising alternative to a conventional tube furnace, the latter is still the dominant component in today’s integrated circuit process. Therefore, the process controllability and dielectric integrity of these new ultrathin N,O dielectrics grown in conventional furnace are important issues. In this letter, the electrical and reliability characteristics of submicron nMOSFETs with oxynitride gate dielectric grown in a conventional furnace have been studied. Various dielectric thicknesses (SO, 80 and 120 A), oxidation temperatures (907, 957 and 1057”Q and combination of 0, and N,O oxidation processes were used. Compared with conventional thermally grown oxide, oxynitride samples show significantly lower degradation under hot electron stress. According to lifetime calculation, oxynitride
2. EXPERIMENTAL Submicron n MOSFETs were fabricated using standard LOCOS-isolated self-aligned polysilicon gate process. Table 1 shows various gate oxidation processes used in the experiment. For N,O oxidation, two different temperatures (957 and 1057°C) were compared, while for 0, oxidation, 907°C was utilized. For films of 120A total thickness, various ratios of N20/02 oxidation thickness were used. After a 500 8, polysilicon layer was gate oxidation, deposited, followed by boron channel implant (dose = 3.8 x lO”/cm*, energy = 35 keV). An additional 3500 A-thick polysilicon layer was deposited and doped. The source/drain regions were formed by arsenic implant (dose = 5 x 10’5/cm2, energy = 30 keV) followed by annealing in N, at 950°C for 30 min. Conventional BPSG passivation layers were used. For mobility characteristics, devices with WpalylLpoly= 15.75 pm/15.75 pm were used. For hotelectron stress characterization, devices with Wpoly/ L po,y= 15.75~m/0.44~m, and 15.75 pm/O.69 pm were used. In addition, conventional polysilicon gate capacitors with various areas were fabricated for thickness monitors and defect density studies. 3. RESULTS
AND DISCUSSION
Figure 1 shows G,, x T,,, vs electric field for z 120A-thick oxide with various oxidation processes, where G,, is the transconductance in the linear region and To, is the oxide thickness. The oxide thickness (To,) was calculated using the capacitance 749
750 Table
HVUNSANG HWANG I. Gate oxidation conditions for different and oxidation temperatures
Thickness
Wafer
#
0,.oxidation
120A
: e f :
I
8OA
:
I
5OA
m n
oxide thicknesses
NOoxidation
120 A/907 ‘C 100 A/907”C 80 A/907”C 60 A/907’ C IO0A/907’ c 80 A/907’ C 60 z&/907’C No 80 A/907 C No No 50A:‘907 c No No
:
No 20 Q957“C. 20 min 40 &957”C, 60 min 60 &957-C, 180 min 20 A/l057 C, 10 min 40&1057’C. 60 min 60&1057’C, 180min 120&1057 C. 180min No 80 &957’C, 130 min 80 A/l057 C, 20 min No 50 A/957 c, 20 mill so A/l057 c. IO mill
method. The NzO oxidation improves transconductance at high field with degradation in the peaktransconductance. The characteristics are similar to those of reoxidized-nitrided oxides [45]. Figure 2(a) shows device lifetime vs inverse drain bias for z 120 A-thick oxide under channel hot electron stress. Polysilicon gate width/length were 15.75 pm/O.44 pm. The gate bias for peak-l,,, condition was used at each drain bias with grounded source and substrate. The device lifetime was defined as the time at which there is 10% degradation of peak-transconductance (AG,jG,). Compared with the control oxide, partial NzO oxidation at 957 C shows a small improvement of device lifetime. However, combinations of O2 and N,O oxidation at 1057°C shows approximately 2-orders of magnitude longer lifetime. As the ratio of NzO to O? oxide thickness increases, lifetime increases slightly. This improvement in lifetime can be explained by nitrogen concentration at different oxidation temperature [2]. We believe that nitrogen concentration of oxide nitrided at 957°C is too low to improve device reliability. Figure 2(b) shows device lifetime vs inverse drain bias for z 80 A and 50 A-thick oxide under channel hot electron stress. Compared with control oxide, over two orders of magnitude longer lifetime was observed for oxynitride gate dielectric grown at 1057°C. Based on this extrapolation, non-LDD
14
(I
Electric
Fig. 1. The product
I
I
I
1
1
1
2
3
4
5
field
=
et al
(Vs-V,)/T,,
of linear region
6
(MVicm)
transconductance
and
oxide thickness (C,, x T,,) as a function of electric field for z 120 A-thick oxide with various oxidation/nitridation cesses. (W/L = 15.75 pm/15.75pm).
pro-
1057°C / x0 A oxynitride 957°C I x0 A oxynitride Control
i XII A
(AGJG,,,,,).
MOSFETs using this oxynitride dielectrics are predicted to have lifetime substantially longer than IO years under 3.3 V operation. Figure 3(a) shows the transconductance degradation of n MOSFETs with 80 A-thick oxide as a function of gate bias after 3000 s hot-carrier stressing. The maximum transconductance degradation which is related to interface state generation was observed at peak Isub condition. Compared with control oxide, oxynitride devices show significantly lower transconductance degradation. Figure 3(b) shows threshold voltage shift (AV,) after 3000 s stress. At peak Irub condition, AV, for oxynitride is less mainly due to lower interface state generation. However, under low V, condition, oxynitride shows small amount of negative shift (hole trapping). In addition. under high V, condition. electron trapping of oxynitride is slightly higher than that of control oxide. Furthermore, cumulative percentage of breakdown vs electric field for capacitors (area = 5.2 mm’) were studied to compare defect density (Fig. 4). Compared with control oxide, oxynitride shows lower initial early breakdown (E,, < 6 MVjcm) which indicates lower defect density (e.g. for 80 A process,
N,O oxidation
process
for MOSFETs
751
(a) 8
T ox = 80 A
= 4.8 v: control = 5 V; oxynitride
6
0
4
I
oxide
Control
2
-0.5
0
l .*
!, Oxynlfride
Ii 1057’(Z
0
4
6
Electric
field
(
,
,
10
12
-1.0
-2 0
1
2
3
Gate
bias
4
6
5
(VP) (V)
8
(MV/cm)
Fig. 4. A Weibull plot of the cumulative breakdown percentage (denoted asp) vs electric field for capacitors with an area of 5.2 mm* [Weibull (p) = log [ - In( 1 - p)]]. Compared with control oxide, oxynitride shows lower initial early breakdown which indicates a lower defect density.
(b) 15 -
2
T ox = 80 A, 3000 s = 4.8 V: control = 5 V; oxynitride
10 -
oxynitride -5 0
I
I
I
I
I
1
2
3
4
5
Gate
bias
I 6
(VP) (V)
Fig. 3. (a) Transconductance degradation (AG,/G .), (b) threshold voltage shift (AV,) of nMOSFET with 80 l-thick oxide as a function of gate bias after 3000 s hot-carrier stressing. Drain bias for control/oxynitride was 4.8 V/5 V to maintain same Irub. Polysilicon gate width/length were 15.75 pm/O.69 pm.
the self repair
model
of defects.
on volume
expansion
of Si during
which
can
effectively
reduce
defect
density
of oxynitride
This
weak
model
is based
nitridation spots.
process The
lower
is also due to the same
mechanism. 4. CONCLUSIONS
N,O oxynitride gate dielectric grown in a conventional tube furnace was used in nMOSFETs to study the hot-cariier immunity and current drive capability. Although for low oxidation temperatures, the peak mobility of oxynitride gate dielectric devices
is slightly lower than that of control oxide devices under low normal fields, the N,O oxynitride devices show higher mobility under high normal fields. Peak transconductance degradation (A&,/G,) and threshold voltage shift (AV,) under hot-electron stress were found to be lower in oxynitride devices. Device lifetime of oxynitride samples is over two orders of magnitude longer than that of the control oxide counterpart. We believe that the improved device reliability of oxynitride devices is due to the nitrogen pile-up at the interface which enhances the resistance of hot-carrier stressing. Acknowledgement-This SRCjSEMATECH under
work contract
was supported No. 88-MC-505.
by
REFERENCES
1. H. Hwang, W. Ting, B. Maiti, D. L. Kwong and J. Lee, Appl. Phys. Left. 57, 1010 (1990). 2. H. Hwang, W. Ting, D. L. Kwong and J. Lee, IEEE IEDM Tech. Dig. 1990, 421 (1990). 3. H. Hwang, W. Ting, D. L. Kwong and J. Lee, IEEE Electron Detrice Lelt. EDL-12, 495 (1991). 4. T. Hori, IEEE Trans. Electron Devices ED-37, 2058 (1990). 5. A. T. Wu, T. Y. Chan, V. Murali, S. W. Lee, J. Nulman and M. Garner, IEEE IEDM Tech. Dig. 1989, 271 (1989). 6. T. Kaga, T. Hagiwara, IEEE Trans. Electron Det!ices ED-35, 929 (1988).