Low-temperature plasma-assisted oxidation of Si: a new approach for creation of device-quality SiSiO2 interfaces with deposited dielectrics for applications in Si MOSFET technologies

I O U R N A L OF

NON-CRYST~LINSE OLIDS ELSEVIER

Journal of Non-CrystallineSolids 179 (1994) 354-366

Low-temperature plasma-assisted oxidation of Si: a new approach for creation of device-quality S i - S i O 2 interfaces with deposited dielectrics for applications in Si MOSFET technologies G. Lucovsky *, T. Yasuda, Y. Ma, S. Hattangady, V. Misra, X.-L. Xu, B. Hornung, J.J. Wortman Departments of Physics, Materials Science and Engineering, and Electrical and Computer Engineering, North Carolina State Unicersity, Raleigh, NC 27695-8202, USA

Abstract

Stacked-gates incorporating thin Si-SiO 2 heterostructures by combinations of plasma-assisted and rapid thermal processing were fabricated. A pre-deposition low- temperature, 300°C, plasma-assisted oxidation step which (i) removes residual C-atom contamination and (ii) generates ~ 0.5-0.6 nm of oxide which serves as a platform for the S i O 2 deposition, also produces a n S i - S i O 2 interface with electrical properties equivalent to interfaces formed by conventional furnace thermal oxidation of Si. This pr,z-deposition oxidation step has been integrated into a process for fabricating MOS devices, which has also be extended to include oxynitride and oxide-nitride-oxide (ONO) dielectrics.

1. Introduction

The excellent electrical properties of Si-SiO 2 interfaces formed during the high-temperature thermal oxidation of crystalline Si have been one of the significant factors in the development of VLSI device technology. The Si-SiO 2 interface is continuously regenerated during the oxidation, and optimization of interracial electrical properties generally requires processing temperatures of approximately 1000°C. Since device dimensions are decreased into the deep sub-micrometer scale for ULSI circuits, the high temperatures required

* Corresponding author. Tel: + 1-919 515 3468. Telefax: + 1-919 515 7331.

for thermally grown oxides and other process steps become increasing incompatible with maintenance of sub-micrometer device dimensions; e.g., dopant diffusion at high temperatures can spread internal device boundaries. This puts limitations on processing temperatures a n d / o r thermal budgets, and has stimulated research on deposited dielectrics which can be produced at temperatures a n d / o r thermal budgets lower than for thermally grown oxides. This paper demonstrates that the integration of deposited dielectrics it~:.Si device technology requires at least a two-step approach to form the Si-SiO 2 heterostructure. These key process steps are (i) formation of the Si-SiO 2 interface, and (ii) deposition of the die!ectric thin film. We emphasize single-layer SiSiO 2 dielectrics, where intermediate-tempera-

0022-3093/94/$07.00 © 1994 Elsevier Science B.V. All rights reserved SSDI 0022-3093(94)00265-0

G. Lucovsky et al. / Journal of Non-Crystalline Solids 179 (1994) 354-366

ture, 600-800°C, rapid thermal chemical vapor deposition (RTCVD) [1,2] and low-temperature, 200-300°C, plasma-enhanced CVD (PECVD) [35] have emerged as promising approaches for depositing ultra-thin SiP2 films. A two-step, 300°C process [4], consisting of remote-plasma-assisted (i) oxidation and (ii) deposition separately controls the respective interface and film properties yielding device-quality interfaces with breakdown fields > 10 MV cm-l, and mid-gap interface defect state densities, Dit, ~ 1 - 3 x 10 ~° cm -2 eV-1. This two step process has been incorporated into the fabrication of F E T devices, which in addition requires post-deposition processing at temperatures up to 900°C. This approach has yielded NMOS devices with peak channel mobilities of ~ 400 cm2/V s for a substrate doping of 2 × 1017 cm -3 [6]. A significant advantage of the two-step approach to forming the Si-SiO2 heterostructures is the independent processing control of the electrical properties of the Si-SiO 2 interface by the oxidation step, and of the bulk oxide by the deposition step [4]. Studies have shown that improvements in the reliability of these devices with respect to those processed at temperatures < 500°C are correlated with annealing during the post-deposition thermal exposures at temperatures of ~ 900°C, as for example in the high-temperature process used for the POCI 3 doping of the poly-Si gate electrode [6]. The eventual development of low temperature processes (e.g., up to 800°C) to (i) deposit in situ doped poly-Si a n d / o r (ii) fabricate raised source-drain contacts means that any necessary annealing of Si-SiO 2 heterostructures at ~ 900°C must be accomplished during or immediately after their formation, since it will no longer be accomplished during the downstream processing. This has prompted the exploration of processing protocols for deposited dielectrics that separately control interface formation and bulk dielectric properties, and also incorporate the rapid thermal annealing (RTA) steps necessary to insure device reliability. The substitution of RTA steps for higher temperature oxide growth provides a significant reduction in the thermal budget; e.g. 30 s RTAs at temperatures up to ~ 950°C have a significantly reduced impact on the ther-

355

mal budget as compared with rapid thermal oxidations (RTO) at temperatures in excess of 1000°C. This paper reviews a newly developed process for the formation of gate oxide heterostructures by a combination of plasma-assisted and rapid thermal techniques that (i) separates interface formation from bulk oxide film deposition as in Ref. [4] and (ii) also integrates an RTA step into the process. The constituent steps in this process are (i) low-temperature, 300°C, plasma-assisted oxidation [4], (ii) an in situ RTA at ~ 950°C, (iii) an 800°C RTCVD SiP 2 deposition and (iv) either a post-deposition 900°C RTA a n d / o r an anneal at 900°C during the doping of the poly-Si gate. The post-oxidation 950°C anneal promotes bonding rearrangements at the Si-SiO 2 interface which reduce the density of Si dangling bond defects contributing to Dit [7]. The oxidation and the deposition steps for the oxide and poly-Si have been performed in situ and sequentially in a single-chamber, UHV-compatible RTP reactor that has been modified for the pre-deposition plasma-assisted oxidation [8]. FET devices formed in this way display peak field effect and effective mobilities,/ZFE and/zef f, respectively, comparable to those of control devices incorporating conventional furnace-grown oxides [8]. The control oxides in our experiments were grown in dry 0 2 with 4% HCI at a temperature of 900°C. The objectives of this research are (i) to define the nature of the process steps necessary to form device-quality gate stacks using deposited, rather than conventional furnaces-oxides, (ii) to identify a specific process for gate stacks with oxide dielectrics and finally (iii) to demonstrate that the approaches in (i) and (ii) can be extended to other dielectric materials and structures including oxynitrides and oxide-nitride-oxide (ONO) stacks.

2. Experimental procedures: gate stack processing for oxide dielectrics This section of the paper describes procedures for fabricating MOS capacitors and FETs with oxide dielectrics formed by the plasma-oxida-

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G. Lucovsky et al. / Journal of Non-Crystalline Solids 179 (1994) 354-366

tion/RTCVD processes identified above. These studies compare Si-SiO2 interface formation by three techniques: (i)wet-chemical oxidation that incorporates the second sacrificial oxide of a hotRCA clean into the gate-dielectric [9], (ii) oxidation that takes place at the initiation of the RTCVD process and (iii) low-temperature plasma-assisted oxidation prior to the oxide deposition (see Fig. 1) [4]. The Si substrates were p-type Si(100) wafers doped with boron to provide a room-temperature hole concentration of ~ 2 x 1017 cm -3. The wafers were wet-chemically processed using a conventional hot-RCA clean [9], after which a 200 nm field oxide was formed by conventional high-temperature furnace oxidation. The wafers were then patterned and etched by standard techniques to identify the Si surface areas where MOS capacitors and FETs would be formed. The exposed Si surfaces were processed a second time by a hot-RCA clean, and the wafers were separated in two batches. Some of the wafers were first rinsed in 1 : 30 H F : H 2° for ~ 15 s, and then in running de-ionized water for ~ 5 s and blown dry with filtered, dry N 2. This removed the wet-chemical oxide formed during the second oxidation of the RCA clean, and produced a H-atom terminated Si surface in the regions of the wafer allocated for gate oxide depositions. Si-SiO 2 interfaces were formed on these surfaces in two different ways: (i) by the plasma-assisted oxidation process of Ref. [4] and (ii) at the initiation of the RTCVD oxide deposition process. The HF rinse was omitted on the remaining wafers so that the second wet-chemical oxide of the RCA clean then served as the platform for the deposition of the RTCVD oxide films. A schematic diagram of the dual-function remote plasma-oxidation/RTCVD cold-wall reactor is shown in Fig. 2. This illustrates the connection of a fused silica tube at one end of the ultra-high vacuum (UHV) compatible stainlesssteel system with a substrate introduction loadlock. Flanges with differentially-pumped double O-rings seals are used to couple the fused silica chamber and plasma generation tube to the stainless steel system. The plasma generation tube is connected upstream from the processing chamber

SILICON/SILICON DIOXIDE INTERFACES Thermal Oxidation of Silicon

,

m

~

~

~

t

SiliconSurface ~

ThermallyGrown Oxide

Silicon/Silicon Dioxide Interface

Oxide Deposited onto Si Surface ~

'

x

~

Deposited Oxide

Silicon Surface

t

Silicon/Silicon Dioxide Interface

Wet-Chemical Oxide Template

Deposited Oxide Wet-Chemical

oxde

::::::::::::::::::::::::::::::::::::::::::: SiliconSurface Silicon/Silicon Dioxide Interface

Two-Step Oxidation/Deposition Process

~vN~N~N~

Deposited Oxide

~--._-._--.-_.---"-----'-'-'-'-'~;--'-'--------" .......

SiliconSurface

Silicon/Silicon

o~x ~ Plasma-Grown Di ide Interface Oxide

Fig. 1. Formation of Si-SiO 2 interfaces by: (i) conver'tional thermal oxidation in which the Si-SiO 2 interface is ct~,ntinuously regenerated as the oxide grows; (ii) deposition of an RTCVD oxide onto a H-terminated Si surface where the interface forms at the metallurgical boundary between the Si and the SiO2; (iii) a wet-chemical oxide that serves as a template for the RTCVD oxide deposition that overcoats the Si-SiO 2 interface formed by wet-chemistry; and (iv) the multi-step process highlighted in this paper - a 300°C plasma-assisted oxidation followed by an RTA and then an oxide deposition by an RTCVD process. Process (iv) has previously been employed using oxide layers deposited by remote PECVD [4,6]. The interface for (iv) is formed by the plasma-assisted oxidation and therefore lies just below the original Si surface.

and provides the capability for the remote plasma-excitation used in the pre-deposition oxidation [4]. The process gases for this oxidation, as well as for the RTCVD SiO2 and poly-Si depositions, are introduced through gas feed lines connected at the end of the plasma-generation tube. The substrates are positioned in the processing chamber region where they can be heated by the

G. Lucovskyet aL/ Journalof Non-CrystallineSolids179 (1994)354-366 coaxial lamp array. CVD deposition takes place only at the heated substrates insuring a relatively clean processing environment in the sense that the walls of the reactor are not overcoated during the oxide and poly-Si depositions. Process gases not consumed in the oxidation and deposition steps, e.g., the inert carrier gases and reaction by-products, are pumped out of the processing chamber by a dry mechanical process pump, an Edwards Drystar 40. This use of this pump eliminates hydrocarbon contamination problems that can occur using oil-based pumping systems. Substrate heating by the external lamps to approximately _+.,cot, ,~ can be obtait~ed over a temperature range from about 300 to 1100°C. The symmetric co-axial heating arrangement of the lamps simplifies the internal construction of the reactor, and in particular the placement of the silicon substrates in a way that ensures approximately uniform heating. Using a turbomolecular pump, a base pressure of ,-. 10 -8 Torr is obtained prior to processing and in between the processing steps.

357

The design of the chamber, and in particular the method of substrate ileating, does not provide a capability for plasma-assisted depositions, because a PECVD process, either remote or direct, generally leads to deposition on the chamber walls and fixtures as well as the deposition substrate. This type of deposition process would then make it impossible for RTCVD processing without using a separate chamber cleaning step after the PECVD deposition. We first discuss devices from which the wetchemical oxide was removed from the Si substrate by the rinse in dilute HF. After insertion into the processing chamber portion of the reactor, some of these substrates were ramped up to the 800°C RTCVD temperature and oxide layers were deposited as described below. The other wafers of this group were ramped up to an oxidation temperature of 300-400°C in an Ar atmosphere prior to RTCVD oxide deposition. Previous studies have shown that a 300°C pre-deposition oxidation minimized the density of interfa-

DUAL RTP-RPECVD R E A C T O R RG#. LOAD.LOC:X L#MP #JtP.AY ELASMAll,mE

I QINilZ~ MAG ROD

t |

REACTOR ATTRIBUTES: UHV capability

I w

UltracleanQuartzChamber Load-lockentry

Dry (oil-free) pumps ExternalLampHeating

I KEY FEATURES:

Remote-plasma

Ultraclean Process Process Flexibility Multi-process Capability

Fig. 2. Schematic of the dual-function processing system with capabilities for (i) plasma-assisted oxidation, (ii) RTCVD oxide and poly-Si deposition and (iii) intermediate or end-of-process rapid thermal annealing.

G. Luco~:sky et al. / Journal of Non-Crystalline Solids 179 (1994) 354-366

358

cial defects, D i t , when followed by a plasma-deposition at ~ 300°C [4]; in these instances, the waf¢~rs were not subjected to a temperature in excess of 400°C, the temperature of the postmetallization anneal (PMA). The oxidation step in the studies reported here was carried out at 300 and 400°C to determine whether post-oxidation processing at elevated temperatures, ~ 800900°C, would anneal away higher density defects at the Si-SiO2 interface and in the thin plasmagrown oxide as previously observed for the 400°C pre-deposition oxidations that were followed by plasma-depositions [4]. The temperature ramp-up for the oxidation step was carried out at an Ar flow rate of 200 sccm and a chamber pressure of ~ 0.30 Torr, over a period of ~ 2 min. An O 2 / A r mixture was then introduced through the plasmageneration tube at a flow rate of 10 seem. An rf plasma, at frequency of 13.65 MHz, was maintained at a power level of 30 W, and the regions of the patterned wafer exposed for MOS and FET devices were subjected to a 15 s plasma-assisted ofidation [4]. Plasma-activated species for this process were transported out of the plasmageneration region into a plasma-free region of the processing chamber, so that the plasma-assisted oxidation was remote in the sense desci!bed in Ref. [4]; i.e., the substrate was outside of the plasma generation region. The O 2 / A r gas flow and the substrate heater lamps were cut off following the oxidation, and the chamber was evacuated to its base pressure by the turbomolecular pump. Following this, an SiP 2 film, ~ 11 nm

thick, was deposited by RTCVD. This deposition was performed at a substrate temperature of 800°C, a process pressure of 3 Torr, and with flow rates of 500 seem for the O-atom source gas, N20, and 25 seem for the Si-atom source gas, Sill 4, diluted to 10% in Ar. These gases were introduced through the plasma generation tube; however, they were not plasma-activated, so that the driving force for the oxide deposition was the substrate temperature of 800°C. Under these process conditions the deposition rate was ~ 0.1 nm s -~ (-- ,~ s-l), so that a film ~ 11-12 nm thick was deposited in 115 s. For some of the wafers, a 90 s in-process RTA, at either 800 or 950°C, and at the system base pressure, was inserted following the plasma-assisted oxidation, and prior to the SiP 2 deposition. Other wafers that retained the wet-chemical oxide of the RCA clean were inserted into the RTP system, and an oxide layer was deposited at 800°C by the RTCVD process using the wet-chemical oxide as a deposition platform. As indicated in Tables 1 and 2, pre-deposition RTAs were performed for some of the MOS devices in which interface formation took place (i) during the plasma-assisted oxidation process, (ii) at the initiation of the RTCVD oxide deposition or (iii) during the second wet-chemical oxidation step cf the RCA clean. MOS capacitors and FETs were formed by convention.d device fabrication techniques. Sputtered AI was used as the gate electrode material for the MOS capacitors. A 30 min off-line PMA was performed in a forming-gas ambient of 10%

Table 1 Properties of MOS capacitors with AI gate electrodes Pre-deposition plasma-oxidation (following rinse in dilute HF)

No pre-deposition oxidation

oxidation temp.

no H F rinse

no vacuum anneal

800°C anneal

Control thermal oxide

H F rinse

(*C) Midgap interface state densities, Dit (+_ I × 101° cm - 2 e V - t) 300 400

3.7-3.8 4.8-5.0

3.8-4.1 4.6-4.8

5.1-7.0

7.1-12.0

5.4-6.0

Flatband voltage, ~ b (+- 0.3 V) 300 400

- 0.86 - 0.88

a _ 0.87, after 800°C vacuum anneal.

- 0.87 - 0.88

- 0.78 a

-- 0.98

-- 0.88

G. Lucovsky et al. ~Journal of Non-Crystalline Solids 179 (1994) 354-366 Table 2 Properties of MOS FETs with polysilicon gate electrodes Wafer process

Thermal oxidation Dry at 900°C RTCVD deposited oxide (i) wet-oxide interface (ii) oxidation during RTCVD (iii) plasma-oxide interface no pre-deposition anneal 800°C anneal 950°C anneal

Peak effective

359

crated during thermal oxidation process (see Fig. 1).

Threshold

voltage a

mobility a

VT

/~FE (_+8 cm2/V s)

( _ 0.06 V)

3. Experimental results 3.1. MOS capacitors

416

0.68

380 387

0.88 0.63

410 415 402

0.79 0.79 0.65

a Averaged over four FET devices.

H 2 and 90% N 2, at a temperature of 400°C.

Standard photolithography and etching procedures were used to complete the MOS devices. The FETs devices had phosphorus-doped poly-Si gate electrodes. These were formed by in situ RTCVD deposition of a 200 nm undoped poly-Si layer immediately following the RTCVD SiO 2 depositions. This was done with a 306 sccm flow of a 10% Sill 4, 90% Ar mixture, at a process pressure of 5 Torr and a substrate temperature of 700°C. The gate stacks were then removed from the dual-function chamber, and FETs were completed off-line by (i) patterning to define the source, drain and gate regions, (ii) a POCI 3 dopant drive-in and activation process at 900°C, (iii) Ti and Al metallization over the doped poly-Si and (iv) a PMA in forming gas at 400°C for 30 min. MOS and FET device structures were prepared with three different types of interface formation process as described above. Within these groups, some of the Si-SiO 2 interfaces were subjected to RTAs prior to the RTCVD deposition. Control devices for comparisons of electrical performance were prepared on Si wafers doped to the same carrier concentration, and using conventional 900°C furnace oxidations in a mixture of 0 2 and 4% HCI to grow the SiO 2 films. The Si-SiO 2 interface in the control devices was gen-

MOS capacitors with AI electrodes have been studied by capacitance-voltage, C-V, measurements, based on the conventional high-frequency, 1 MHz, and quasi-static techniques and using standard Hewlett-Packard test equipment [4]. The C - V data were obtained with a voltage sweep rate of 35 mV s -1 for MOS capacitors with Si-SiO 2 interfaces formed by the three different interface formation procedures discussed above (see Fig. 1). C - V curves were analyzed to obtain values for (i) the fiat-band voltage, Vfb, and (ii) the interface defect state density at mid-gap, Dit [10]; these are summarized in Table 1. For a p-type Si substrate wi:h a hole concentration of ~ 2 × 1017 c m - 3 and at: Al electrode, the anticipated value for Vro is -.0.85 _+ 0.05 V. For this doping, a conservative est;mate of the minimum detectable value for Dit at :hid-gap is ~ 2 × 101° cm -2 eV -1 [10]. This estimate is based on the ability to measure small differences in capacb tance between the quasi-strait and high frequency C - V data, and is theregore a function of the oxide thickness and the capacitance meter sensitivity. For the oxide thickne,=ses of ~ 10 nm used in these studies, a more realistic value is slightly lower, ~ 1 x 101° cm -2 e\ ,r-1. The C - V results for control devices incorporating thermally grown oxides, and averaged over four devices, are Dit = 5 _ 1 × 101° c m - 2 e V -1, consistent with the anticipated sensitivity, and Vro-- - 0 . 8 8 _+ 0.03 V, also in close agreement with the expected value. The flat band voltages for the MOS devices ranged from ~ - 0 . 8 to -1.0 V, and the mid-gap Dit levels ranged from ~ 3.5 × 101° c m - 2 eV-1 to 12 × 101° cm -2 eV -1 The pre-deposition, plasma-oxidized wafers displayed the lowest values of Dit, and had the smallest spread in Vn, In addition, Vro values for these devices were, to the accuracy of the measurements, the same as those obtained for control

360

G. Lucovsky et al. ~Journal of Non-Crystalline Solids 179 (1994) 354-366

chemical oxide of the RCA clean (i) the Dit values were higher than those of the plasma processed and control wafers, and these were not reduced by the insertion of an 800°C vacuum pre-deposition anneal, and (ii) the Vro values were about 0.1 V more positive, Vfb ~ --0.78 + 0.03 V as compared with ~ - 0 . 0 8 V for the control wafers. The Vfb values for these devices recovered to the expected values when the in situ 800°C pre-deposition vacuum anneal was inserted into the process. For wafers from which the last RCA clean sacrificial oxide had been removed, the values of Dit were higher than for any of the other pre-deposition processing. In addition, the Vro values were more negative than anticipated, about ~ -0.98 V, indicative of a positive fixed charge in the oxide layer in the immediate vicinity of the Si-SiO 2 interface.

devices with thermal oxides. This Vfb behavior is consistent with these two groups of devices having about the same doping profile in the Si substrate in the immediate vicinity of the Si-SiO 2 interface, and also with there being no significant contributions to Vn, from Dit or fixed charge within the respective oxide layers. Finally, the higher values of Dit for the wafers subjected to the 400°C pre-deposition oxidation are consistent with the results of previous studies [4], which showed that pre-deposition oxidations at temperatures > 350°C produced significant increases in Dir However, these studies indicated a smaller ratio of Dit between the 400 and 300°C oxidations than for the previous studies, so that some the interface states generated during the 400°C oxidation were annealed away by post-oxidation thermal exposures during either (i) the 800°C oxide, a n d / o r the 7000C poly-Si depositions, or (ii) the 9000C poly-Si doping process. Significant differences in MOS device performance, relative to the control devices, were found for wafers not subjected to the pre-deposition plasma-assisted oxidation. For the wafers n o t subjected to the HF rinse which retained the final

MOSFET

3.2. M O S F E T

The I - V characteristics of the FETs were measured by standard techniques, and the values of the transconductance, gm, and the field effect and effective channel mobility, /~FE and /.telf,

CHARACTERISTICS

[]

[]

•

o

& A

characterization

-- Interface

Effects

D09: Thermal oxide (t = 11.0 nm) 1:)06: Plasma-oxide interface (t = 12.0 nm) D03: Wet-chem oxide interface (t = 11.8 nm)

500

: i Z = 100 ;trn ~EGO

~ . 400-

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300

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200 mm

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1

IN

100 0 ...... -1.0E+6

• , 0.0E+0

"%

1.0E+6

2.0E+6

(Vg s" VT) I tox

Fig. 3./z~= and//'eft versus the field at the Si surface, E s -- (Vgs effects of different interface formationprocesses.

VT)/tox.

~l,eff

~ ~m~.

3.0E+6

mmmm E mmm

m

4.0E+6

(Vlcm)

The three sets of data includedin this plot illustrate the

G. Lucovsky et aL /Journal of Non-Crystalline Solids 179 (1994) 354-366

361

MOSFET CHARACTERISTICS -- Annealing Effects []

[]

D09: Thermal oxide (t = 11.0 nm)

A

A

D06: Plsm-ox interface (t = 12.0 nm)

•

O

1:)08: Plsrn-ox interface + 950C RTA (t = 11.8 nm)

500 A

~

~s41qDO, = ==, -lilt q

!

300

mmm amm

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400

E o

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200

0

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100

~°I~"A~°AmOA~AUAUuUnn

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0 -1.0E+6

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2.0E+6

3.0E+6

4.0E+6

(Vgs-VTlltox (Vlcm) Fig. 4. #'FE and/L/,eff versus the field at the Si surface, E s = (Vgseffects of different post-oxidation annealing.

VT)/tox.

The three sets of data included in this plot illustrate the

drive current, IdlCox, as a function of the source-drain potential difference, Vds, for different values of the gate voltage, Vg, and (ii) the

respectively, w e r e also c o m p u t e d in the usual ways [10,11]. In this p a p e r we focus on several aspects o f F E T p e r f o r m a n c e : (i) t h e n o r m a l i z e d

MOSFET OUTPUT CHARACTERISTICS D09:Thermaloxide (tox=11.0nm) D08:Plsm-oxirderrace+ 950Canneal (fox=11.8nm).~..~ 1600,

D04:Plsm-oxinterfa0e+800Canneal(tox=12.4nm) ~

z.~

/r~

V_= 4 V g

.7.-~-

v

---

1400~'

1200-

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10008006002"~

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0.5

1

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1.5

7__~-..2__ ~ 7~ . " - ~ ' - _ _

2

2.5

---

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--~---~-

4

Vds (V) Fig. 5. Drive current characteristics, lds/Cox, a s a function of Vds for several va~.ues of Vg.

362

G. Lucovsky et al. / Journal of Non-Crystalline Solids 179 (1994) 354-366

behaviors of ].I,FE and /~eff as a functions of the electric field at the Si-SiO 2 interface: I d is the drive current and Cox is the oxide capacitance per unit area. For small lids = 0.05 V, the field at the Si-SiO 2 interface is approximated by ( V ~ V x ) / t o x , where Vgs is the potential difference between the gate and source, V x is the threshold voltage and tox is the oxide thickness. Expressions for V x, ~FE and/z~ff are given in standard texts [10,I1]. Table 2 summarizes (i) the peak values of the field effect mobility,/ZVE, derived from g,~ in the linear region of the current-voltage transfer characteristics for lids= 0.05 V, as well ~ts (ii) values of V x. Note that the peak values of /~FE are equal to those of /zeff, and in Table 2, we have designated these as a channel mobility, ~c. Figs. 3 and 4 show the variations in /~rE and ~eff as a function of the effective field at the Si-SiO 2 interface for different interface formation and ther~nal treatments, respectively, while Fig. 5 presents transfer characteristics, the normalized drain current, I j C o x , versus Vds for increasing values of Vg. All of these data are averaged over at least four samples. Since the differences in threshold voltage for all of the processing variations used in this study are small, < 0.2 V, we have not renormalized the transfer curves for these small differences in V x. The more exact method would be to use V g - V x instead of Vg for comparing drive currents in devices prepared by the different processing techniques. For the devices examined in these studies, all of the determinations of relative performance would be the same for both methods of plotting the transfer characteristics. Consider first the variation of the peak values of ~FE and /zeff with respect to surface processing conditions. Referring to "Fable 2, the peak values,/z¢ are smallest for the FETs in which the Si-SiO 2 interface was formed either by the wetchemical oxide of the RCA clean, or at the initial stages of the RTCVD oxide deposition, by factors of ~ 8 and 7%, respectively. On the other hand, the average values of/z c for the devices th~.t used the plasma-assisted oxidation to form the Si-SiO 2 interface are about 1-3% lower than ~¢ for the control devices with the thermal oxides. There

are similar trends in the values of the threshold voltage. Vx is significantly higher for the FETs with the RCA clean oxide as compared with the control FETs with the thermally grown oxides. On the other hand, the values of Va. for the FETs with the interfaces formed during the oxide deposition, and for the devices with the plasmaoxide interface subjected to the 950°C vacuum anneal are essentially the same as those of the control devices, while the values of Va- for the devices with the plasma-oxide that had not been vacuum annealed or had been subjected to an 800°C vacuum anneal were both the same, and about 15% larger than those of the control oxides. Based on the trends noted above, we have focused on the field dependence of ]£FE a n d / z a f for the structures which employed the plasma-assisted oxidation process, with comparisons to interfaces formed with the control thermal oxides, and the RCA clean wet-chemical oxide. Fig. 3 shows that the fall-off in jI£FE and /Xeu with interface field occurs zt a faster rate than for the control FET, and Fig. 5 demonstrates that the normalized drive current relative to the control device is lower for this same processing condition. From Table 2, we note that there is a modest increase in the peak value o f / z c when the wetchemical oxide is removed prior to the RTCVD SiO 2 deposition. For the FET devices that incorporate plasma-assisted interfacial oxides, we found higher values of/z c that are comparable to those of the control devices. As shown in Fig. 3, the fall-offs of/~vE and /Zeu with field are less than that observed for the wet-chemical oxide interfaces, but are still faster than the control oxide. This is also seen in the transfer characteristics shown in Fig. 5. The value of VT for the FET with the plasma-assisted Si-SiO 2 interface formation process is closer to the value obtained for the control device with the thermal oxide, ~ 0.1 V as compared with 0.2 V for the wetchemical interface. The comparisons in Table 2 and Figs. 3 and 5 establish that a wet-chemical native oxide interface is detrimental to FET device performance, supporting the obse~ations made from the studies on the MOS capacitors discussed above. There are modest improvements

G. Lucovsky et al. /Journal of Non-Crystalline Solids 179 (1994) 354-366

in all aspects of FET performance when the wet-chemical oxide of the RCA clean is removed by a rinse in dilute HF, and the interfacial oxide is formed at the initiation of the RTCVD process cycle during the temperature ramp-up in the N 2 0 / S i H 4 ambient; however, the performance of these devices is generally not as good as in devices where the wet-chemical oxide was removed, and where the plasma-assisted oxidation step was inserted prior to RTCVD oxide deposition. We now address the effects of an in situ RTA of the interfacial plasma-oxide performed at the base-pressure of the processing chamber, and immediately before the RTCVD oxide deposition. We have investigated the e~ects of this anneal on the peak values of /~FF and /zeff, and VT, the fall-off of/~FE and/x~ff with electric field, and on the I - V character!stics, as shown respectively in Table 2 and Figs. 4 and 5. The data displayed in Figs. 4 and 5 include (i) control FETs with the thermally grown oxides, as well as (ii) FETs with plasma-assisted interface formation process (a) with no additional thermal processing between the oxidation and RTCVD depositions, and (b) with an in situ, 90 s RTA at 800 and 950°C between the oxidation and RTCVD steps. Annealing of the interfacial plasma-oxide at 800°C showed little change in the peak values of /ZFE and //'eft and VT, and in the data displayed in Figs. 4 and 5 as compared with not having an RTA at all, but having an Si-SiO 2 interface formed by plasma-assisted oxidation. In this context, it is important to note that for all of the devices studied some degree of post-deposition thermal annealing at ~ 700°C occurred in situ during the poly-Si deposition and at ~ 900°C during the ex situ dopant drive-in process. On the other hand, an intentionally added annealing step at 950°C, while promoting a small decrease the peak value of/z~ff, ~ 2-3% with respect to the control device, showed two important improvements: (i) a decrease in the fall-off characteristic as evidenced from the slope of the datapoints in Fig° 4, and (ii) a value of V x that approached that of the control devices with thermally grown oxides (see Table 2). Based on these exploratory studies, we feel that post-oxidation annealing

363

processes must be addressed in more detail in future studies, particularly in FET devices that employ ultra-thin gate dielectrics ~ 5-6 nm and less.

4. Discussion

The results presented in this paper show that low-temperature, 300°C predeposition plasma-assisted oxidation process can be combined in situ with intermediate-temperature, 700-800°C, rapid thermal depositions of SiO 2 and poly-Si thin films to yield high performance stacked gate structures. In particular, Si-SiO2 heterostructures with properties similar to those formed by conventional thermal-oxidation techniques have been formed using a multi-step low-thermal budget process separates interface formation from bulk oxide film formation. The key elements of the process are (i) a low-temperature, 300°C, plasmaassisted oxidation of the Si, (ii) a post-deposition, in situ RTA at 950°C, (iii) an 800°C RTCVD SiO2 deposition and (iv) a 700°C RTCVD poly-Si deposition. The plasma oxidation pre-treatment (a) removes residual carbon contamination from the Si surface, (b) forms an ~ 0.6 nm SiO 2 layer that creates the Si-SiO2/S~ interface, and also serves as a platform for the RTCVD oxide, and (c) forms an Si-SiO, interface with consistently low Dit values and a consistently high/.telf. The postoxidation/pre-deposition RTA promotes bonding rearrangements in immediate vicinity of the Si-SiO 2 interface, reducing Dit, and the fixed oxide charge that contributes to the larger values of V x observed when this step is omitted (see Table 2). All of the gate stack processing, except the poly-Si gate electrode doping, has been performed in situ and sequentially in a single-chamber reactor. This aspect of integrated processing is essential for preserving the chemical integrity of the superficially oxidized surface prior to the RTA and RTCVD processes. Our results emphasize that it is crucial to remove the wet-chemical native oxide before commencing any processing, and additionally that it is beneficial to passivate the RCA-cleaned surface with a plasma-oxide prior to the RTCVD processing [12]. We are

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G. Lucovsky et aL / Journal of Non-Crystalline Solids 179 (1994) 354-366

investigating other Si-SiO 2 interface formation processes that can be integrated into a process protocol that includes the RTCVD oxide and poly-Si depositions; e.g., RTO steps that are used in, prior to or following the RTCVD oxide depositions steps [13]. Both of these approaches have yielded FET devices with properties comparable to those of the control FETs with thermally grown oxides, and similar to those obtained in the present study for processing that included the predeposition oxidation and the post-oxidation, preRTCVD oxide deposition anneal. The recent exploratory experiments discussed in this paper, and as yet unreported studies [13] coupled with the more extensive studies of pre-deposition plasma-assisted oxidation [4,6], have shown that separate control of Si-SiO 2 interface formation

FORMATION OF SILICON/SILICON DIOXIDE INTERFACES Thermal OxidaUon of Silicon ~

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and bulk oxide deposition are essential in a gatestack processing protocol that includes deposited oxide dielectrics. All of these studies demonstrate that there are advantages in performing all these steps in situ, in which case the electronically significant interfaces are created and encapsulated in the process sequence before the wafer is exposed to any ambient outside of the processing chamber. We have also prepared MOS capacitors and FETs using plasma-deposited oxides, including the two-step plasma-assisted oxidation/deposition process, and have obtained device performance that is comparable to what is obtained with the RTCVD oxides using the pre-deposition plasma-assisted oxidation step [6]. However, the formation of a complete gate stack including RTCVD deposition of tk~ poly-S; gate electrode could not be performed in situ due to limitations imposed by the processing chamber design. We have also used the fabricated gate stacks using oxide-r~;tride-oxide (ONO) and oxynitride alloy dielectrics [14,15] and in each instance have used a plasma-assisted oxidation step to form the Si-SiO 2 interface (see Fig. 6). The ONO and oxynitride dielectrics in these studies were deposited by a 300°C remote PECVD process. Interfacial and bulk dielectric electrical properties were evaluated by C - V measurements on the as-deposited structures and on structures that were subjected to a post-deposition 30 s RTA at

G. Lucovsky et al./ Journal of Non-Crystalline Solids ]79 (1994) 354-366 10 ~2

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900°C. Al electrodes were used for both the asdeposited and annealed Si-dielectric heterostructures. For all of the samples studied, there was a significant improvement in the electrical characteristics after the RTA step (see Figs. 7 and 8). These studies were performed on ~ 10 II cm p-type Si(100) wafers, and the values of Dit at mid-gap and Vfb after the RTA were essentially the same as those for oxide dielectrics where the oxide heterostructures have also been subjected to a post-deposition RTA. These results are consistent with what we have previously reported for gate stacks oxide dielectrics prepared by remote PECVD [4] and with what we have discussed above for gate stacks with RTCVD oxide dielectrics; i.e., the interfacial electrical properties are determined by the pre-deposition oxidation step, and the insertion of an annealing step at a temperature of about 900°C improves interfacial electrical properties.

5. Conclusions

We have demonstrated that stacked-gates incorporating thin Si-SiO 2 heterostructures can be fabricated in situ by combinations of plasma-assisted and rapid thermal processing, and display electrical performance comparable to devices in which the Si-SiO 2 heterostructures were formed by conventional techniques employing higher pro-

365

cessing temperatures a n d / o r thermal budgets. A pre-deposition low-temperature, 300°C, plasmaassisted oxidation step, which (i) removes residual C-atom contamination, (ii) creates the metallurgical Si-SiO 2 interface, (iii) generates ~ 0.5-0.6 nm of oxide and (iv) serves as a platform for the S i P 2 deposition, is critical in the formation of an Si-SiO 2 interface with device-quality electrical properties. This pre-deposition oxidation step has been integrated into a process for fabricating MOS devices which utilizes three rapid thermal process steps', (i) a post-oxidation RTA, and (ii) two RTCVD films depositions for the oxide and poly-Si layers. The combination of the pre-deposition plasma-assisted oxidation process, coupled with film deposition by remote PECVD, has been extended to oxynitride and oxide-nitrideoxide (ONO) dielectrics. Devices incorporating these dielectrics also require a short RTA, 30 s at 900°C after the oxynitride or ONO deposition, in order to improve their performance to the same levels as in devices with the same types of dielectrics, but formed at significantly higher processing temperatures. In summary, the combination of low-temperature plasma-assisted oxidation for interface formation, coupled with 300°C plasma-assisted film depositions or 800°C RTCVD films depositions, and combined with either mid- or end-of-process RTAs has been shown to yield device-quality electrical properties at reduced thermal budge:ts with respect to the conventional furnace processing techniques for oxide, oxynitride and ONO dielectrics. This research is supported in part by Office of Naval Research, the NSF Engineering Center for Advanced Electronic Materials Processing at NC State University, the North Carolina SEMATECH Center of Excellence and the Semiconductor Research Corporation.

References [1] G.Q. Lo, W.C. Ting, D.K. Shih and D.L. Kwong, Appl. Phys. Lett. 56 (1990) 979. [2] X-L Xu, R.T. Kuehn, J.J. Wortman and M.C. Ozturk, Appl. Phys. Lett. 60 (1992) 3063.

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G. Lucoz,sky et al. /Journal of Non-Crystalline Solids 179 (1994) 354-366

[3] J. Batey and E. Tierney, J. Appl. Phys. 60 (1986) 3136. [4] T. Yasuda, Y. Ma, S. Habermehl and G. Lucovsky, Appl. Phys. Lett. 60 (1992) 434. [5] G.G. Fountain, R.A. Rudder, S.V. Hattangady, R.J. Markunas and P.S. Lindorme, J. Appl. Phys. 63 (1988) 4744. [6] G. Lucovsky, Yi Ma, T. Yasuda, C. Silvestre and J.R. Hauser, Jpn. J. Appl. Phys. 31 (1992) 4387. [7] C.H. Bjorkman, T. Yasuda, C.E. Shearon Jr., G. Lucovsky, U. Emmerichs, C. Meyer, K. Leo and H. Kurz, J. Vac Sci. Technol. Bll (1993) 1521. [8] V. Misra, S.V. Hattangady, X.-L. Xu, M.J. Watkins, B. Hornung, G. Lucovsky, J.J. Wortman, U. Emmerichs, C. Meyer, K. Leo and H. Kurz, presented at European MRS Meeting, Strasbourg, France, May 1993, and to be published in the symposium proceedings.

[9] W. Kern, J. Eiectrochem. Soc. 137 (1990) 1887. [10] E.H. Nicollian and J.R. Brews, in: MOS Physics and Technology (Wiley, New York, 1982) p. 792. [11] A.G. Milnes, in: Semiconductor Devices and Integrated Electronics (Van Nostrand Reinhold, New York, 1980) ch. 7. [12] M. Morita and T. Ohmi, in: The Physics and Chemistry of SiP 2 and the Si-SiO 2 Interface 2, ed. C.R. Helms and B.E. Deal (Plenum, New York, 1993) p. 199. [13] J.R. Hauser and J.J. Wortman, unpublished results. [14] Y. Ma, T. Yasuda, S. Habermehl and G. Lucovsky, J. Vac. Sci. Technol. Bll (1993) 1533. [15] Y. Ma and G. Lucovsky, unpublished results.