SiC hetero-junction MOSFET

Solid-State Electronics 51 (2007) 662–666 www.elsevier.com/locate/sse

Study of a novel Si/SiC hetero-junction MOSFET L. Chen *, O.J. Guy, M.R. Jennings, P. Igic, S.P. Wilks, P.A. Mawby School of Engineering, The University of Wales Swansea, Singleton Park, Swansea SA2 8PP, United Kingdom Received 24 April 2006; received in revised form 31 January 2007; accepted 3 February 2007 Available online 27 March 2007

The review of this paper was arranged by Prof. S. Cristoloveanu

Abstract A new device is proposed that utilizes a Si/SiC hetero-junction to potentially overcome one of the major issues holding back the development of SiC MOSFET technology. The proposed device makes use of a thin epitaxial layer of silicon grown on a SiC substrate, on which a high-quality MOS structure can be fabricated. Doped p-type wells in both the silicon and SiC epitaxial layers ensure that the blocking region is contained entirely within the SiC substrate, thus maximising the breakdown voltage of the device. In this study, numerical modelling methods have been applied to a Si/SiC hetero-junction MOSFET structure in order to investigate its feasibility and potential benefits over conventional SiC MOSFETs. Preliminary results on growth of thin silicon layers on SiC – which would be used in fabrication of the real device – are also reported.  2007 Elsevier Ltd. All rights reserved. Keywords: Hetero junction; MOSFET; SiC; Si

1. Introduction Traditional silicon technology has come close to its theoretical limits in high power applications. An increasing demand for high power and high voltage electronics devices gives wide band gap semiconductors an opportunity to enter this market. Among the wide band gap semiconductor materials, SiC has become extremely attractive. Its unique physical properties allow the opportunity to achieve new breakthroughs in the electrical performance of power switching devices. In particular, the 4H–SiC polytype possesses a high avalanche break-down electric field strength (P2.2 · 106 V/cm), which is almost one order of magnitude higher than that of silicon. 4H–SiC has a band gap of 3.26 eV, a high thermal conductivity (5 W/cm K), a high bulk electron mobility (800 cm2/V s), and a high intrinsic temperature (around 1000 C). The superior mate-

*

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0038-1101/$ - see front matter  2007 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2007.02.026

rial properties of 4H–SiC, compared to those of silicon, make it ideally suitable for high voltage [1–3] and high temperature applications [4]. Silicon power MOSFETs are hampered by the rapid increase in specific on-resistance (Ron) in the drift region, with increasing blocking voltage Vb ðRon / V 2:5 b Þ. SiC power MOSFETs have specific onresistances two order of magnitudes lower than their silicon counterparts [5,6], therefore their current handling capability is much higher. SiC also has the advantage of having silicon dioxide as its native oxide, facilitating the fabrication of metal-oxidesemiconductor (MOS) structures by thermally growing an oxide at the SiC surface. However, the conventional thermal oxidation process normally results in a high density of interface states (Dit) at the SiC/SiO2 interface [7,8]. The Dit value is around 2.9 eV above the valence band edge in both 4H–SiC and 6H–SiC [9], which means the interface states lie mostly within the 4H–SiC band gap. The high density of interface state results in poor inversion channel mobility with values of 1–20 cm2/V s in 4H–SiC [10,11] being typical. Vertical MOSFETs demonstrate superior

L. Chen et al. / Solid-State Electronics 51 (2007) 662–666

performance relative to lateral MOSFETs due to the higher carrier mobility in the c-plane (1190 cm2/V s) of 4H–SiC. Low on-resistance, high voltage MOSFETs with short channel lengths of 0.5 lm, combined with optimised implant dosage and activation anneals have been reported [12,13]. High frequency 10 kV vertical DMOSFETs with adequate channel mobility (22 cm2/V s) and specific onresistance (123 mX cm2) have also been demonstrated [14,15]. Although these devices produced adequate on-state performances, the channel mobility associated with these devices is still at least an order of magnitude below that of silicon MOSFETs. Improved channel mobilities would yield significant improvements in on-resistance, and much work has been undertaken on increasing the channel mobility in 4H–SiC power MOSFETs. It is been reported that post-oxidation anneal using NO or N2O improve channel mobility to around 50 cm2/V s [16]. These low channel mobility figures are at least an order of magnitude lower than the bulk mobility, and thus limit the specific on-state resistance of the MOSFET. In most 4H–SiC power MOSFETs, the major components of the total on-resistance of the device are the resistance of the drift layer and the resistance of the inversion channel. To overcome these difficulties, new design solutions to minimize the channel resistance, without compromising the other components of the device specific on-resistance, are required. It is therefore essential to develop new MOSFET structures, which combine good on-state performance, for high current handling capacity, with high off-state blocking voltages. Silicon can normally reach an inversion layer mobility of 50–70% of its bulk mobility of 1360 cm2/V s (pure silicon crystal orientation 100 at 300 C). The aim of the Si/ SiC hetero-junction MOSFET structure is to overcome the drawback of the low channel mobility in SiC MOSFETs, by taking the advantage of the much higher channel mobilities in silicon MOS structures (typically several hundred cm2/V s) [21]. This will yield a high on-state current conductivity, as well as utilizing the critical electric field strength in SiC for high reverse blocking voltage capability. This paper presents the simulation of the electrical characteristics of Si/4H–SiC hetero-junction MOSFET structures, using the finite element (FE) based device simulator TCAD Studio [17]. FE device modelling tools provide a reliable and cost effective way to evaluate the performance of semiconductor devices before committing to fabrication.

2. MOSFET structure and simulation parameters 2.1. Novel MOSFET structure The cross-section of the novel MOSFET Si/SiC power device is schematically shown in Fig. 1. The proposed hetero-junction Si/SiC MOSFET structure is comprised of an n-type 4H–SiC 10 lm thick low doped epitaxial layer on a heavily doped 4H–SiC substrate. A thin silicon epitaxial layer (0.1 lm in thickness) on top of the SiC contains

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Fig. 1. Schematic simulated structure of Si/SiC hetero-junction MOSFET.

n+ source and p-body regions. An aligned p-well is also present in the SiC epi-layer. A 50 nm thin oxide layer – which would be formed from partial oxidation of the silicon layer – is used as the gate insulator. 2.2. Simulation parameters A SiC epitaxial layer (n-drift) is needed to support high voltages in the MOSFET. The 10 lm thick 4 · 1015 cm3 doped epitaxial layer used in the simulated device (see Fig. 1), is capable of theoretically supporting a voltage rated over 1 kV. The doping concentration of the silicon n-drift region was also defined as 4 · 1015 cm3. The p-well region was assigned a box shape doping profile at a depth of 1.1 lm from the silicon surface. The lateral distance (d in Fig. 1) between adjacent p-wells has been varied from 2 to 6 lm. The total lateral cell pitch was 16 lm. The doping concentration of the p-wells in both the silicon and SiC layers was identical. It is important to optimise these doping concentrations, as these parameters determine the on-state and off-state behaviour of the MOSFET. A relatively high doping concentration in the p-well will prevent the device from suffering premature break-down under reverse bias conditions, due to p-well punch through. The drawback of a MOSFET with a highly doped p-well is the undesirably high threshold voltage. An optimised value of 1.8 · 1017 cm3 was adopted in these simulations as a compromise between these two scenarios. In this case, the p-well/n-drift metallurgical junction is located at a depth of 1 lm from SiC surface. The n+ source has a doping concentration of 1 · 1019 cm3 and penetrates the silicon layer to a depth of 200 nm from silicon surface. A gate oxide thickness of 50 nm was used. The lateral channel length was 1.3 lm. In a real Si/SiC MOSFET, the device performance will also be influenced by the SiO2/Si and Si/SiC interfaces. To represent the Si/SiO2 interface, a large positive interface

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charge of 1 · 1011 cm2 eV1 [18] was assumed in the device model. With regard to the interface state densities at the Si/SiC hetero-junction, to the best of our knowledge, there have been no reports in the literature so far. In this study, a range of positive fixed interface charges were assumed at the Si/SiC interface, with the largest value up to 1 · 1012 cm2 eV1. Under forward bias conditions, current can flow through the MOSFET, from the drain to the source, if a sufficiently large voltage is applied to the gate electrode to generate a n-channel inversion layer in the p-well. In the hetero-junction MOSFET, the inversion channel is formed in the silicon, between the n+ source and n-drift regions just beneath the gate oxide. The resistance of the device is limited by the on-state voltage drop across the resistive components between the source and the drain: Rs (the lateral resistance of the silicon in the n+ source region), Rch (the channel resistance), RJFET JFET resistance, Rd (the resistance of the SiC drift layer), and Rsub (the resistance of the SiC substrate). The largest resistances can be attributed to Rch and RJFET. The channel resistance Rch in the hetero-junction MOSFET is expected to be lower than the equivalent channel resistance encountered in a conventional SiC MOSFET. 3. Simulation results and discussion The semiconductor device simulator TCAD Studio has been employed in the study of a Si/SiC hetero-junction MOSFET structure. The simulator can be used to model the two-dimensional distribution of potential and carrier concentrations in a device, in order to predict its electrical characteristics at a given bias. The electrical and material parameters of 4H–SiC polytype used in the simulation were obtained from the published literature [19,20]. The most important operating considerations for power MOSFET performance are the break-down voltage and the specific on-resistance. An ideal power MOSFET should have the break-down voltage as high as possible, and have specific on-resistance as low as possible. The key parameter to determine break-down voltage and specific on-resistance is the doping and thickness of the drift region. Obtaining a high break-down voltage by lowering the doping or increasing the thickness of drift region will normally lead to a high specific on-resistance. In this study, the breakdown voltage and the specific on-resistance were investigated as a function of varying the p-well spacing. Fig. 2 shows the curves of break-down voltage and the corresponding specific on-resistance for the Si/SiC hetero-junction MOSFET structures for four different p-well spacings: 2 lm, 3 lm, 4 lm and 6 lm. The specific on-resistance values for all cases were extracted at gate voltage of 10 V in this study. In addition, the Si/SiC MOSFET has been simulated with four different interface parameter cases. Case 1 shows the result from an ideal MOSFET structure without any surface states between Si/SiO2 and Si/SiC interfaces. The maximum break-down voltage

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Fig. 2. Break-down voltage versus specific on resistance, the p-well spacing ranges from 2 lm, 3 lm, 4 lm and 6 lm in four different cases.

reached 1220 V, with a maximum specific on-resistance of 24.46 mX cm2 for the structure with the smallest p-well spacing of 2 lm. The break-down voltage reduces to 981 V, and specific on-resistance drops to 11.85 mX cm2 when the p-well spacing increases to 3 lm. The minimum break-down voltage of 729 V, associated with a minimum specific on-resistance of 6.9 mX cm2, was obtained using the largest p-well spacing of 6 lm. Case 2 assumes that the interface state density at the Si/SiO2 interface is 1 · 1011 cm2 eV1. These interface states do not influence the break-down voltage value, but have a significant effect on the specific on-resistance value. This is because when the n-channel MOSFET works in inversion condition, the Fermi level lies close to the conduction band edge. All the interface states below the Fermi level are occupied by electrons. As a result, these trapped electrons increase the electric field in SiO2. Therefore, the number of electrons present in the inversion layer at a given oxide field is reduced. Further more, the Coulomb scattering effect from the trapped electrons reduces the effective mobility in the inversion channel. The channel current is significantly reduced under these combined effects. As a result, the specific on-resistance in Case 2 is 34.6 mX cm2 for the 2 lm pwell spacing, which is higher compared with the ideal structure in Case 1 (24.46 mX cm2). In Case 3, the interface state density at the Si/SiO2 is assigned to be 0, and interface state value at the Si/SiC is assigned to be 1 · 1012 cm2 eV1. This interface state introduces an internal electric field in the junction between silicon and SiC, causing the breakdown-down voltage to be lower – compared to the MOSFET model without interface states (Case 1). The heterojunction MOSFET benefits from this internal electric field at Si/SiC junction during its on-state operation, where the gate is positively biased. The higher electric field in the inversion layer, induced by the internal electric field, acts to increase the number of electrons in the channel, thus increasing the electron current. This results in a lower specific on-resistance, compared to Case 1.

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Further investigation of the effect of Si/SiC interface states on the on-state device performance have been performed using SILVACO TCAD. These results confirm our original findings that a Si/SiC Dit of 1 · 1012 cm2 eV1, produces an increase in the current flow through the simple Si/SiC test structure, reducing Ron. This can be explained by a reduction of the electrical barrier at the Si/SiC interface produced by a positive Dit. This effect dominates the electrical behavior of the Si/SiC interface. In Case 4, the interface state density at the Si/SiO2 is increased to 1 · 1011 cm2 eV1, and the Si/SiC is assigned a value of 1 · 1012 cm2 eV1. Due to the small dimension between these two interfaces, the internal electric field enhanced by the Si/SiC interface causes higher inversion current at a positive gate bias. Although channel mobility is lowered by the Si/SiO2 finterface states, this effect can be negligible compared to the dominant Si/SiC interface effect. The simulation results show that the specific onresistance values are close to the values in Case 3 (Fig. 2). Simulations have also been carried out on a conventional SiC MOSFET structure with similar dimensions and parameters to the hetero-junction MOSFET. The results show that specific on-resistances of the Si/SiC hetero-junction MOSFETs are lower than the pure SiC MOSFET structures. An example of a pure SiC MOSFET with 3 lm p-well spacing, which has the same parameters as in the case 4 shown previously for Si/SiC hetero-junction MOSFET, except that the SiC/SiO2 interface state was assigned 1 · 1012 cm2 eV1. The specific on-resistance is 12.6 mX cm2 for pure SiC MOSFET, as compared to 10.2 mX cm2 for Si/SiC hetero-junction structure. Simulations have also been performed to model the hetero-junction’s forward characteristics at different gate voltages. Fig. 3a shows the forward current (Ids) versus voltage (Vds) characteristics of the 3 lm p-well spacing hetero-junction MOSFET with positive interface charges of (1 · 1011 cm2 eV1), (1 · 1012 cm2 eV1) respectively at the Si/SiO2 and Si/SiC interfaces. These results compare favorably with the conventional SiC MOSFET shown in Fig. 3b with positive interface charges (1 · 1012 cm2 eV1) at SiC/SiO2. The hetero-junction structure also gives higher currents at much lower gate voltages – due to the lower threshold voltage achieved by hetero-junction structure. One of the principal goals is to achieve a high blocking voltage in the design of Si/SiC hetero-junction MOSFETs. In this paper, a 811 V blocking voltage and a 10.2 mX cm2 specific on-resistance were obtained by optimizing the pwell gap to 3 lm for the structure with interface states at Si/SiC and Si/SiO2. Further reduction in p-well spacing leads to a higher blocking voltages, but is accompanied by a dramatic increases the on-state resistance, due to the narrow current path in the JFET region of the device. Further increases in p-well spacing lead to lower blocking voltages, because a larger p-well spacing has a lower effect on driving the electric field away from the silicon n-drift region. The interface states at Si/SiC are favourable to the on-state performance, but are not desirable in terms

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Fig. 3. Forward characteristics of MOSFETs: (a) 3 lm p-well spacing hetero-junction MOSFET, with positive interface charges in Si/SiO2 (1 · 1011 cm2 eV1), and Si/SiC (1 · 1012 cm2 eV1) interfaces, at a gate voltage of 3, 3.5, 4, and 4.5 V; (b) 3 lm p-well spacing SiC MOSFET, with positive interface charges in SiC/SiO2 (1 · 1012 cm2 eV1) interface, at a gate voltage of 4, 4.5, 5, and 5.5 V.

of the blocking voltage, which decreases with interface states due to its associated internal built-in electric field. The proposed hetero-junction MOSFET construction has been designed so that the depletion layer spreads into SiC epilayer, therefore utilising the high dielectric strength of the SiC semiconductor substrate to sustain the high blocking voltage. Furthermore, the large thermal conductivity of SiC should also yield advantages in the dissipation of heat generated by a current flow in the device. In the simulation, a perfect single crystal structure for silicon was assumed, along with associated electrical and material parameters. In reality, there must be a lattice mismatch at the interface between silicon and SiC. Deposition of silicon on SiC confirmed monolayer growth for thin films (less than 2 nm), but showed islanding for thicker

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films. The degradation on the silicon parameters due to this growth process, compared to an ideal single crystal layer, is not known. However, ellipsometric studies in our current research show a very sharp and abrupt Si/SiC interface, suggesting that a high-quality Si/SiC interface may be achieved. Further work is concentrating on improving the quality of the silicon layer and developing fabrication process that will be optimized to minimize the degradation of its electronic properties. 4. Conclusions A high blocking voltage has been simulated for a Si/SiC hetero-junction vertical MOSFET design. The device design has been optimized so that the high electric field, produced by high reverse voltages, is driven away from silicon region by controlling the spacing between the p-wells of adjacent MOS structures. Using device structures with a narrow p-well spacings the electric field build-up has been confined to the SiC layer. Smaller p-well spacings have been shown to yielding higher blocking voltages, but also yield a larger resistance in the JFET region of the device structure during on-state performance. A trade-off between the onresistance and off-state blocking voltage must be made, with the optimum p-well spacing found to be between 2 lm and 3 lm. The use of thin silicon layer (less than 0.5 lm) ensures that the contribution of this layer to the total resistance of the MOSFET is minimal. The effect of interface states at both the SiO2/Si and Si/SiC interfaces has been investigated under forward and reverse bias conditions. Interface states at SiO2/Si had little effect on the reverse blocking voltage, but SiO2/Si interface states produced an increase in the MOSFETs on-resistance. In contrast, Si/SiC interface states yielded a minor improvement in on-state resistance, suggested to be due to a reduction or narrowing of the internal electrical barrier at the Si/SiC interface. Initial growth studies show a sharp interface between the silicon and SiC layers, though the lattice mismatch (19.3%) between silicon and SiC is expected to generate defects and dislocations at the Si/SiC interface, that will offset the device performance. It is likely that the thin silicon layer grown on these lattice mismatch materials will be highly strained, which may enhance the mobility of electrons in the strained silicon layer. These simulation results show that if a silicon layer of sufficient quality can be grown on SiC, the Si/SiC MOSFET could yield significant improvements in on-state resistance over conventional SiC MOSFETs. Acknowledgement The authors gratefully acknowledge the financial support provided by the European Union ESCAPEE (GRD1-2000-25337) and the UK Department of Trade and Industry INTRINSIC (TP/3/OPT/6/I/17311) projects.

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