Analytical PSpice model for SiC MOSFET based high power modules

Microelectronics Journal 53 (2016) 167–176

Contents lists available at ScienceDirect

Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo

Analytical PSpice model for SiC MOSFET based high power modules Daniel Johannesson n, Muhammad Nawaz ABB Corporate Research, Forskargränd 7, SE-72178 Västerås, Sweden

art ic l e i nf o

a b s t r a c t

Article history: Received 2 October 2015 Received in revised form 25 February 2016 Accepted 2 May 2016

A simple analytical PSpice model has been developed and verified for a 4H–SiC based MOSFET power module with voltage and current ratings of 1200 V and 120 A. The analytical simulation model is a temperature dependent silicon carbide (SiC) MOSFET model that covers static and dynamic behavior, leakage current and breakdown voltage characteristics. The technology dependent MOSFET modeling parameters are extracted from characterization measurements, datasheets and PSpice simulations at various temperatures. The SiC MOSFET model is implemented in the PSpice circuit simulation platform using PSpice standard components and analog behavior modeling (ABM) blocks. The MOSFET switching performance is investigated under influence of different circuit elements, such as stray inductance, gate resistance and temperature, in order to study and estimate on-state and switching losses pre-requisite for design of various converter and inverter topologies. The performance of the SiC MOSFET model is fairly accurate and correlates well with the measured results over a wide temperature range. & 2016 Elsevier Ltd. All rights reserved.

Keywords: 4H–SiC 4H–SiC MOSFET Device modeling Silicon carbide PSpice SiC power modules

1. Introduction With energy efficient power transmission in mind, one of the main drivers within the power industry are to reduce the physical footprint and overall losses in transmission and distribution systems. Today, HVDC, FACTS and other high power applications request compact, highly efficient and reliable power electronic converter systems [1,2] using novel power semiconductor devices. Since Si based conventional semiconductor devices have reached to a certain maturity point and approaching theoretical limits, the research focus has partly been shifted towards wide bandgap semiconductor materials and devices. Silicon Carbide (SiC) based semiconductor devices are predicted to operate beyond the Si operating range, especially for high temperature, radiation sensitive environment, and for high power applications. This is a direct consequence of fundamental properties of the SiC material that are shown superior in many ways in comparison to Si counterparts. For example, the properties of wide bandgap of SiC material that outperform Si counterpart and promote the usage of SiC based power semiconductors in very high power system [3] are higher electric breakdown field strength, higher thermal conductivity and higher saturation velocity of charge carriers. Hence, the SiC based power semiconductor devices are predicted to allow high switch frequencies, low on-state and low switching losses n

Corresponding author. E-mail addresses: [email protected] (D. Johannesson), [email protected] (M. Nawaz). http://dx.doi.org/10.1016/j.mejo.2016.05.001 0026-2692/& 2016 Elsevier Ltd. All rights reserved.

and thereby reduce auxiliary components and cooling system requirement within the power electronic converter leading to the design of compact and efficient converters systems at lower overall system cost. The SiC semiconductor device and material manufacturing process has been rapidly evolved during the recent years resulting in larger SiC wafer's size (3″–6″) and improved epitaxial growth quality [4,5]. The manufacturing progress has already introduced a variety of interesting SiC semiconductor devices and power modules at basic research level (i.e., MOSFETs, JFETs, BJTs, Thyristors and IGBTs) [6–9]. The SiC based bipolar junction transistors and other bipolar charge carrier semiconductor devices has relatively low on-state voltage drop in comparison with other semiconductor device structures. Unfortunately there is still degradation problems of forward current gain and on-state voltage drop which is inherent drawback for the performance of for instance SiC BJT power modules [10]. Among the unipolar charge carrier semiconductor devices, the SiC based JFET has low on-state voltage drop and are predicted for operation in high temperature and high frequency applications. On the other hand, the normally-on nature of JFET power modules require complex driving circuits and has overall a rather narrow process improvement window [11]. The voltage controlled SiC MOSFET has simple gate control requirements and are predicted to reach high switch frequencies. The MOSFET has slightly higher conduction losses compared to bipolar semiconductor devices. Unfortunately, the MOSFET development has been hampered by MOS interface issues, such as interface traps between the SiC surface and gate oxide material

168

D. Johannesson, M. Nawaz / Microelectronics Journal 53 (2016) 167–176

[12]. The presence of interface traps within the MOSFET channel reduces the mobility of charge carriers resulting in low current gain of MOSFET devices [13]. Also, the poor reliability of MOS interface leads to threshold voltage degradation over time which is a clear drawback. Though, the strong advantages of simple, voltage controlled gate drivers and high switching frequency overcomes the SiC MOSFET challenges where a great research effort has led to MOS interface improvements and development of high voltage devices. Various design concepts of SiC MOSFETs has been explored recently and novel semiconductor devices with blocking voltages 4 10 kV [3,14,15] and channel mobility 4100 cm2/V s [16,17] has recently been presented. The commercial SiC semiconductor devices (i.e., JFETs, MOSFETs and BJTs) has nowadays reached 1.2 kV–1.7 kV blocking voltage and 100 A–800 A current capability [18–20]. Looking at the current pace of technology development, the current and voltage ratings of SiC power modules is increasing rapidly that may lead to introduce more high power commercial semiconductor modules in the market soon. The power semiconductor device is the main building block and key component in power electronic converters. In order to fully utilize the benefits of SiC semiconductor devices and to ensure a swift implementation of SiC semiconductor devices in power electronic converters, the performance has to be fully evaluated. Comprehensive studies are necessary to evaluate different converter topologies and design solutions with respect to stability, conduction losses and switching losses. The converter performance must be simulated, optimized and experimentally verified to ensure reliable operation, by using analytical circuit simulations based on accurate and reliable semiconductor device models [21–30]. The semiconductor device models should preferable be simple and analytical with a limited set of parameters and at the same time be robust and suitable for circuit simulators. Note that previously developed SiC MOSFET models implemented in SPICE type circuit simulators deals with low power applications, ranging from
mA up to 33 A [21–28]. Most of the models are behavior models which are rather easy to implement and suitable in circuit simulators with only a few parameters [21–27]. The parameter extraction procedure of behavior models are relatively easy, performed either by using values from datasheets or using the built-in parameter extraction tools and models within circuit simulation software [22–24,26,27]. Advanced numerical simulation models based on the physical structure of the semiconductor shows accurate simulation results but on the cost of computationally intensive longer simulation time [29]. For instance, Fu et al. has developed a circuit simulation model which accounts for the non-uniform current distribution in the JFET region of a DMOSFET which shows fairly accurate results [29]. One the other hand, the numerical simulation models could be complicated to implement, may be unsuitable for circuit simulator platform such as PSpice. Several SiC MOSFET models includes temperature dependency, either by a physic-based approach or by temperature scaling functions, applicable in ranges from room temperature up to over 150 °C [22,26,28,30]. Lu et al. [21] and Sun et al. [25] has presented simulation models for a wide temperature range, including low temperature applications. McNutt et al. has developed a physic-based SiC MOSFET model, implemented in Saber circuit simulator, which shows accurate static and dynamic characteristics [28]. The modeling parameters of the model is extracted by the IMPACT software [28,31]. As of today, few models covers full SiC MOSFET performance to the extent that power electronic converters could be thoroughly evaluated. The SiC MOSFET models must be able to replicate temperature dependent static and dynamic characteristics, including breakdown voltage characteristics and leakage currents. This paper proposes an analytical PSpice model developed and verified for high power SiC MOSFET modules with voltage and

current rating of 1200 V and 120 A (Rohm Semiconductor BSM120D12P2C005 [32]). The developed model is based on the original McNutt et al. [28] SiC MOSFET modeling approach but with extensions to include breakdown voltage characteristics and leakage current. The original McNutt model has been modified with for instance a different physic-based expression of intrinsic carrier concentration and simplifications in the implementation strategy to achieve a less complex model that is suitable for converter system design and optimization. Note also that the previously developed model was developed for a 5 A SiC MOSFET chip, and the model presented in this paper is developed for commercial available SiC MOSFET power modules, with significant higher current rating, 120 A. Contrary to previous verification in SABER platform [28], the proposed model has been implemented in PSpice circuit simulation platform using ABM blocks and verified for commercial high power SiC modules. The developed model covers temperature dependent static and dynamic characteristics of the SiC MOSFET power module and is well-suited for power electronic converter system design and optimization (i.e., main aim of our modeling effort).

2. Model development 2.1. Model description A SiC based MOSFET power module supplied by Rohm Semiconductor has been characterized to generate electrical data set for verification of the model. The SiC MOSFET power module is manufactured in a half-bridge configuration with SiC MOSFETs and SiC Schottky Barrier Diode (SBD) as free-wheeling diodes (FWD) [32]. A schematic figure of the theoretical SiC MOSFET structure and equivalent electrical modeling structure used in the presented model is illustrated in Fig. 1. The proposed SiC MOSFET modeling approach in this paper is based on a set of analytical equations representing the MOSFET characteristics and the FWD characteristics. The MOSFET drain current, ID in this model is well represented by the product of the MOSFET channel current, IMOS and the multiplication factor, M

Fig. 1. The silicon carbide MOSFET structure and a theoretical schematic of the developed modeling approach.

D. Johannesson, M. Nawaz / Microelectronics Journal 53 (2016) 167–176

region width, wB and the parameters n and B [34], according to

according to

ID = MIMOS

for

(1)

VGS > VT

VT = VT 0 + VTT (T − 300)

≤

⎡ KF KP ⎢ ( VGS − VT ) VDS − ⎣

y

⎥ ⎦

( 1 + θ ( VGS − VT ) ) VGS − VT P VF

for

VDS

(3)

2

KP ( VGS − VT )

(

2 1 + θ ( VGS − VT )

)

for

VDS >

VGS − VT P VF

(4)

where VDS is the drain-source voltage, PVF is the pinch-off voltage factor and y is the pinch-off voltage exponent represented by (7). θ is the transverse electric field parameter, KF and KP are the linear and saturation region transconductance parameters. The temperature dependency of the transconductance and transverse electric field is represented by

⎛ 300 ⎞KFT , KPT ⎟ KF , P = KF 0, P 0 ⎜ ⎝ T ⎠

(5)

⎛ T ⎞θ T ⎟ θ = θ0 ⎜ ⎝ 300 ⎠

(6)

y=

P VF 2

1 m 1 − ( VDS /VB )

(9)

(7)

(8)

where VB is the breakdown voltage of the device and the exponent m is used as a fitting parameter. Note that M ¼1 for VDS o oVB. The breakdown voltage represents the point of drain-source voltage where drain current increases significantly, caused by impact ionization. The ionization rate in this model is approximated by the Shields and Fulop power approach (10), where the effective ionization rate are expressed with the constant B and the exponent n [34]. The impact ionization rates are temperature dependent, thereby also the breakdown voltage, which is covered by the temperature dependence of parameters B and n which are expressed in (11) and (12). Therefore, the temperature dependent breakdown voltage in this model are expressed in terms of drift

(10)

n=

bEFF 1.68 × 106 + 1300 (T − 300) = E0 2.093 × 105

(11)

B=

aEFF 3.42 × 10−2 = E0n exp (n) E0n exp (n)

(12)

here, EC is the critical electric field strength and E0 is the normalized electric field and aEFF and bEFF are the two ionization rate coefficients. For gate-source voltages below threshold voltage, a small leakage current, IR is flowing. The MOSFET body leakage current consist basically of saturation current and electron holes pair current generated in the space–charge region [34]. The MOSFET leakage current is represented by

IR = MIr

for

(13)

VGS < VT

⎛ 2 n L n Ir = qA ⎜⎜ i P + i N τ τg ⎝ B P

2εR ( VBI − VDS ) ⎞⎟ ⎟ qNB ⎠

(14)  19

where, q is the elementary charge (1.602  10 C), ni is the intrinsic carrier concentration, εR ( ¼9.66ε0) represents the dielectric constant for 4H–SiC and LP is the diffusion length of hole carriers and is equal to the square-root of the product of the hole diffusion constant and the hole lifetime. NB is the drift region doping level, τP and τg represents the hole carrier lifetime and the generation lifetime and VBI is the built-in potential. The intrinsic carrier concentration is determined by the 4H–SiC bandgap properties and bandgap narrowing phenomena [34] which is represented by

KF KF −

here, KF0, KFT, KP0, KPT, θ0 and θT are temperature coefficients. When the applied voltage approaching the breakdown voltage, the impact ionization rate increases rapidly and the current rises abruptly. The high applied electric field accelerating the charge carriers to a certain point whereas the impact with other carriers generates an avalanche effect [34]. This is represented by the multiplication factor which is approximated as

M=

1/ n wB EC w ⎛ n + 1⎞ = B⎜ ⎟ 2 2 ⎝ BwB ⎠

⎛ E ⎞bEFF / E0 = B⋅E n αEFF = aEFF e−bEFF / E0 ⎜ ⎟ ⎝ E0 ⎠

2 −y ⎤

y−1 y P VF VDS ( VGS − VT )

Saturation region:

IMOS =

VB =

(2)

where VGS is the applied gate-source voltage and VT is the MOSFET threshold voltage whereas the temperature dependency is approximated as a linear function with coefficients VT0 and VTT. Here, T is the temperature. The MOSFET channel current is represented by two equations, one for the linear region and one for the saturation region [33], according to Linear region:

IMOS =

169

Eg0 = 3.263 −

ΔEg =

3q 16π ϵ r

6.5 × 10−4 ⋅T 2 T + 1300

(15)

q2n ϵ r kT

(16)

where k is the Boltzmann's constant (8.617  10  5 eV K  1). The bandgap narrowing effect depends on the electron carrier density, n, which for simplicity reasons are assumed to be equal to the doping concentration. Furthermore, the intrinsic carrier concentration are expressed, using (15) and (16) and the effective density of state for electrons and holes for 4H–SiC material is represented as

⎛ T ⎞1.58 ⎟ NC = 1.69 × 1019 ⎜ ⎝ 300 ⎠

(17)

⎛ T ⎞1.85 ⎟ NV = 2.49 × 1019 ⎜ ⎝ 300 ⎠

(18)

⎛ q ( −Eg 0 + ΔEg ) ⎞ ⎟⎟ ni2 = NC NV exp ⎜⎜ kT ⎝ ⎠

(19)

The 4H–SiC carrier mobility is described by the Arora model

170

D. Johannesson, M. Nawaz / Microelectronics Journal 53 (2016) 167–176

[35], where the mobility is dependent on the total doping concentration and temperature which is illustrated by

μE =

947 (T /300)−2.15

(

1 + N /1.94 × 1017

μH = 15.9 +

)0.61

(20)

124 (T /300)−2.15 − 15.9

(

1 + N /1.76 × 1019

)0.34

(21)

The life time of hole charge carriers are modeled according to the Scharfetter relation with a power law temperature dependence [36,37] according to

⎛ T ⎞1.72 ⎜ ⎟ 0.3 ⎝ 300 ⎠

τp0

τp = 1+

(

p 3 × 1017

)

(22)

where τpo denotes the maximum hole lifetime without impurities at 300 K. The drift region resistance [28] is determined according to

RB =

w qμE NB A

where

w = wB − wDSJ

ADS εR wDSJ

ADS = A − AGD

(24)

2εR ( VDS − VBI )

wDSJ =

VBI =

where

qNB

(25)

⎛N N ⎞ kT ln ⎜ A 2 B ⎟ q ⎝ ni ⎠

(26)

here, ADS is the drain body area and AGD is the gate–drain overlap area. NA and NB are the two doping levels. The gate–drain capacitance, CGD is split into two parts, depending on drain-source voltage, gate-source voltage and the gate–drain overlap depletion threshold voltage VTD. The gate–drain capacitance [28] is expressed by

CGD = COXD

for

VDS ≤ VGS − VTD

Table 1 PSpice modeling parameters for SiC MOSFET power module. Parameter Name

(23)

here, A is the chip area, wB is the width of the low doped drift region and wDSJ is the drain-source depletion width. The drainsource capacitance is related to the PN-junction and space–charge region which reaches into the drift region and is represented according to

CDSJ =

Fig. 2. Measured and simulated temperature dependency of MOSFET threshold voltage.

A AGD KF0 KFT KP0 KPT PVF θ0 θT RS τp0 τg wB NA NB VT0 VTT VTD0 VTDT VBIGD FXJBE FXJBM CGS COXD m

MOSFET active area Gate–drain overlap area Linear region transconductance KF temperature coefficient Saturation region transconductance KP temperature coefficient Pinch-off voltage factor Transvers electric field parameter θ temperature coefficient Series drain resistance Initial hole lifetime Generation lifetime Metallurgical drift region width Acceptor doping concentration Drift region doping concentration MOSFET threshold voltage VT temperature coefficient Gate–drain overlap depletion threshold voltage VTD temperature coefficient Built-in potential of gate–drain overlap region Fraction depletion charge at gate– drain overlap edge Fraction depletion charge at gate– drain overlap middle Gate-source capacitance Gate–drain overlap capacitance Multiplication factor

Value 0.138 0.069 1.5 2.15 4.5 0.115 0.95 0.001 1 0.001 2  10  6 1  10  6 11.33 1  1016 1.18  1016 5.06  0.0167 0 0.01 2.8

Unit 2

Ext. by

Ω s s μm cm  3 cm  3 V V/K V

E E Exp Exp Exp Exp E E E Exp E E E E E Exp Exp E

V/K V

E E

cm cm2 A/V2 A/V2

V1

0.5

E

0.75

E

14  10  9 1  10  9 6

F F

DS DS E

(27) Table 2 PSpice modeling parameters for SiC free-wheeling diode.

CGD =

COXD CGDJ

( COXD + CGDJ )

CGDJ =

wGDJ =

for

AGD εR wGDJ

VDS > VGS − VTD

(28)

(29)

Parameter

Name

Value

Unit

Ext. by

n A* VBN wSBD ASBD NDSBD

Ideality factor Schottky barrier diode Richardson's constant Metal–semiconductor potential barrier SBD drift region width Schottky barrier diode area Doping concentration SBD

1.03 400 1.27 15.75 0.0729 8  1017

A eV μm cm2 cm  3

Exp Exp Exp E E E

2εR ( VDG − VTD ) qNB

VTD = VTD0 + VTDT (T − 300)

(30)

(31)

where, VDG is the drain–gate voltage, COXD is the gate–drain overlap capacitance, CGDJ is the gate–drain depletion capacitance and wGDJ

is the depletion width. VTD is the gate–drain overlap depletion threshold voltage with temperature scaling factors VTD0 and VTDT. At sufficient large negative gate voltages, holes flows from the body region and accumulates beneath the gate–drain overlap region which then becomes inverted and affects the gate–drain capacitance [28]. This is modeled as gate–inversion layer capacitance, CGI expressed as

D. Johannesson, M. Nawaz / Microelectronics Journal 53 (2016) 167–176

171

NDSBD parameters. 2.2. Parameter extraction

Fig. 3. The extracted Schottky barrier diode characteristics, used as free-wheeling diode in the SiC MOSFET power module.

CGI = COXD

for

(32)

VGS ≤ VTDI

⎛ VGS − VVDIedge ⎞ ⎟ CGI = COXD ⎜ ⎝ VTDI − VVDIedge ⎠

VTDI = VTD − VBIGD −

for

VGS < VTDIedge & VTDIedge > VTDI

FXJBM AGD 2εR qNB ( VBIGD + VDS ) COXD

VTDIedge = VTD − VBIGD −

FXJBE AGD 2εR qNB ( VBIGD + VDS ) COXD

(33)

(34)

(35)

here, VTDI is the gate–drain overlap inversion threshold voltage, VTDIedge is the threshold voltage at body edge of gate–drain overlap. VBIGD is the built potential voltage of the gate–drain overlap region FXJBM and FXJBE is respective depletion charge fraction at the gate– drain overlap, in the middle and at the edge. The properties of the free-wheeling diode affects the dynamic characteristics of the MOSFET power module. In this model, the source current of the free-wheeling Schottky barrier diode are determined by the saturation current, IS, ideality factor n and resistance, R. The Schottky diode current [34] is represented by −qVBN ⎛ q (V − IR) ⎞ ⎞ ⎛ q (V − IR) I = IS ⎜ e nkT − 1⎟ = A*T 2e kT ⎜ e nkT − 1⎟ ⎠ ⎝ ⎠ ⎝

(36)

here, A* is the Richardson constant, V is the applied voltage and VBN is the metal–semiconductor potential barrier. The resistance of the SBD is determined according to (23), using the wSBD, ASBD and

The static performance of the SiC MOSFET power module was measured with a Tektronix 371a curve tracer with a measurement capability of 3000 V and 300 A. The dynamic characteristics were measured using a single pulse test setup under inductive load conditions. The measured characteristics were used for extraction of MOSFET modeling parameters and validation of the model. The I–V characteristics were measured at different gate voltages and for different temperatures along the MOSFET operating range. Static modeling parameters, such as linear- and saturation region transconductance (i.e., KF and KP) were obtained from the measured I–V characteristics. Further, the temperature dependency of the threshold voltage, VT, was also derived from the linear portion of I–V characteristics. Fig. 2 shows the measured and simulated threshold voltage for different temperatures. Initially guesses of the modeling parameters regarding the MOSFET gate-source capacitance, CGS and gate–drain overlap oxide capacitance, COXD, were extracted from the datasheet along with drain series resistance, RS, and MOSFET chip area, A. Finally, the modeling parameters were manually fine-tuned in order to optimize the MOSFET static and dynamic characteristics. All the modeling parameters that gives fair agreement with experimental data related to the 1.2 kV SiC MOSFET model are presented in Table 1. The last column of the Tables 1 and 2 intends the parameter extraction procedure where Exp means extracted from experiment, DS is a datasheet value, and E is a typical estimated value from device design. The free-wheeling diode (FWD) characteristics and temperature dependency were extracted from the datasheet. The Schottky diode characteristics that are used in the proposed model are shown in Fig. 3 together with the FWD diode characteristics in the datasheet. The modeling parameters related to the free-wheeling diode model are presented in Table 2. 2.3. PSpice implementation As discussed earlier, previous modeling approaches implemented in PSpice circuit simulator deals with primarily low power SiC-MOSFET devices (i.e., single die) [25,26]. This model is developed for MOSFET power modules with current capabilities of 4100 A where several dies are in parallel. The complete set of equations are implemented according to the physical structure of a MOSFET device presented in Fig. 1, requiring both standard PSpice components and analog behavioral modeling (ABM) blocks. The

Fig. 4. PSpice sub-circuit schematics of the implemented SiC MOSFET model.

172

D. Johannesson, M. Nawaz / Microelectronics Journal 53 (2016) 167–176

Fig. 5. The PSpice schematics of the dynamic evaluation circuit with the SiC MOSFET sub-circuit model represented by the U2 and U3 blocks.

VGS=20 V T=300K

VGS=15 V

VGS=10 V VGS=5 V

VGS=20 V T=373K

VGS=15 V VGS=10 V VGS=5 V

Fig. 7. Measured and simulated breakdown voltage characteristics indicating currents at different temperatures.

T=425K

VGS=20 V

Experiment VGS = 0 V Simulation VGS = 0 V (Constant = 5e21) Simulation VGS = 10 V, 15 V and 20 V

VGS=15 V VGS=5 V

VGS=10 V

Fig. 6. Current–voltage characteristics (i.e., IDS Vs VDS) at different gate voltages for SiC MOSFET power module at 300 K (a), 373 K (b) and 425 K (c).

usage of ABM blocks enables implementation and simulation of different types of linear and non-linear equations in PSpice. The equations of the MOSFET model are finally implemented as a PSpice sub-circuit represented by a set of properly connected

Fig. 8. Simulated current–voltage characteristics (i.e., ID Vs VDS) up to the breakdown voltage of the device. Also shown is the measured breakdown voltage characteristics (at VGS ¼0) for the SiC MOSFET power module.

D. Johannesson, M. Nawaz / Microelectronics Journal 53 (2016) 167–176

ID VDS

VDS

ID

173

ID

ID VDS

VDS

Fig. 9. The measured and simulated dynamic performance of SiC MOSFET power module at two drain-source voltage levels, VDS ¼ 600 V (a) and VDS ¼800 V (b) at 300 K.

VGS controlled current sources, capacitors and resistors, according to Fig. 4. The MOSFET drain current is represented by “IMOS” ABM block in Fig. 4. The MOSFET drain current is implemented as the MOSFET channel current, (1), together with leakage current characteristics, (13) which both contains the breakdown voltage characteristics due to the multiplication factor. The drift region resistance, RB in the model is represented by two components, mainly because of simplicity. First, the ABM calculation block derives the drift region resistance which then gives input to the voltage dependent resistor. The three voltage dependent capacitors are represented by voltage controlled current sources. The sub-circuit are then implemented in a static and dynamic evaluation circuit. The static evaluation circuit consist basically of one voltage source, which generate the drain-source voltage and one voltage source, which generate the gate-source voltage. The dynamic evaluation circuit represents the single pulse test setup under inductive load conditions. The gate driver is simulated by a simple driving circuit, consisting of a voltage pulse source, resistor and inductor. The PSpice schematics of the dynamic evaluation circuit is presented in Fig. 5.

3. Results and discussion The static and dynamic simulation result of the developed model are verified against measured data at different temperatures. The simulated and measured I–V characteristics for different gate voltages (i.e., 5 V, 10 V, 15 V, and 20 V) at 300 K, 373 K and 425 K are presented in Fig. 6. A fair agreement is witnessed at both temperatures. As expected, On-resistance (RON) increases and threshold voltage decreases for SiC-MOSFET power modules with the increase of temperature for a given gate-source bias similar to experimental findings [24–26]. The MOSFET breakdown voltage characteristics are presented in Fig. 7 and Fig. 8. The drain current increases significantly as the drain-source voltage approaches the

VGS

Fig. 10. The zoomed-in view of turn-on (a) and turn-off (b) transient of the SiC MOSFET power module with supply voltage VDS ¼ 600 V. The zoomed-in view of gate voltage during turn-on (c) and turn-off (d).

breakdown voltage, due to impact ionization. In Fig. 8, a simulation constant has been used in order to present the simulated breakdown voltage (at VGS ¼0) in the same figure and with the same axis as for the measured breakdown voltage. The dynamic performance is simulated according to the dynamic test setup shown in Fig. 5 for two voltage levels namely VDS ¼600 V and VDS ¼800 V and is shown in Fig. 9. The zoomed-in view of drain-source voltage VDS, drain current ID, and gate voltage VGS during turn-on and turn-off of the device are presented at two voltage levels in Fig. 10 and Fig. 11. The proposed model predicts

174

D. Johannesson, M. Nawaz / Microelectronics Journal 53 (2016) 167–176

VDS

ID

ID

VDS

IC=120 A T=300 K

VDS=600 V T=300 K

VDS=600 V T=300 K

VGS

VDS=600 V T=300 K

VGS

VDS=600 V Fig. 11. The zoomed-in view of turn-on (a) and turn-off (b) transient of the SiC MOSFET power module with supply voltage VDS ¼ 800 V. The zoomed-in view of gate voltage during turn-on (c) and turn-off (d).

an overall fair agreement with experimental data at 600 V and 800 V supply voltages. The scalability of the model is investigated as a switch loss trend analysis where the turn-on and turn-off energy losses trend indicates if the model may be applicable to a wider region than the single experimentally verified operating point. Several important circuit modeling parameters have been simulated in PSpice and studied to predict the switching loss trend over a wide range. The turn-on and turn-off losses as function of five different converter cell parameters are studied. For instance, drain-source voltage, drain current, gate resistance, stray inductance and temperature

Fig. 12. Turn-on and turn-off switching losses as function of drain-source voltage (a), drain current (b), gate resistance (c), stray inductance (d) and temperature (e). Measured values and datasheet values are represented with black symbols (i.e., triangles and circles).

D. Johannesson, M. Nawaz / Microelectronics Journal 53 (2016) 167–176

VDS=600 V T=300 K

VDS=600 V T=300 K

175

and thereby lower losses. The switching losses during turn-off, on the other hand, shows only a minor decrease for increasing transconductance, mainly because the extracted current during turn-off is basically the same. The energy loss trend seen in Fig. 13b indicates that both turnon loss and turn-off loss increases as the drift region doping concentration increases. The doping level affects not only the mobility, lifetime and thereby the MOSFET on-state resistance but also the drain-source capacitance and gate–drain capacitance. As the drift region doping level increases, the available charge carriers increases leading to a higher built in potential in the PNjunction, but most significant, the width of space–charge region will be reduced. Thereby, the drain-source capacitance and gate– drain capacitance increases and more time is needed to charge and discharge the larger capacitances. This leads to a decrease of dVDS /dt (dID/dt remains approximately unchanged) which resulting in higher switching losses for increasing drift region doping levels.

4. Conclusion

Fig. 13. Turn-on and turn-off switching losses as a function of internal modeling parameters, drift region dopant density, NB (a) and transconductance, KP (b).

which is presented in Fig. 12. For a given load current, a quasilinear increase in switching loss for increased drain-source voltage is obtained as expected. The experimental switching losses for VDS ¼600 V and VDS ¼800 V are plotted as black triangles (turn-on) and circles (turn-off) in Fig. 12a for comparison. Further, the switching losses increases for increasing drain current as expected and with the same trend as the manufacturer datasheet. The same increasing switch loss trend are observed for increasing gate resistance. Basically, the gate resistance determines the magnitude of the gate current and thereby the rate of dID/dt and dVDS/dt during turn-on and turn-off transient. An increase of gate resistance will reduce the rate of change which will lead to longer switching times and thereby increased switching loss. The datasheet switching losses for different gate resistances are plotted for comparison with simulation results. The datasheet values are plotted as black triangles for turn-on and black circles for turn-off in Fig. 12c. The influence of stray inductance of the total losses is overall small in comparison to the drain-source voltage. For instance, the reduction in turn-on switching losses and increase of turn-off losses varies about 10%–15% for a stray inductance variation from 50 nH to 500 nH. The influence of temperature dependence is even smaller than the influence of stray inductance. A slight increase in the turn-off loss and a decrease in the turn-on loss is noticeable which is consistent to the datasheet trends in the same temperature range. Again, this PSpice model accurately reflects the static and dynamic assessment of the MOSFET power module. The switching performance has been studied further by variation of two internal SiC MOSFET modeling parameters. The influence on energy loss as a function of saturation region transconductance, KP and drift region doping level, NB are investigated, and both are presented in Fig. 13. The turn-on and turn-off energy loss shows a decreasing trend for increasing transconductance, KP. The decrease in turn-on energy loss could be explained by the increase of transconductance, in other words, an increase of current amplification which leads to faster turn-on current risetime (dID/dt)

An analytical model for a 1.2 kV and 120 A SiC based MOSFET power module has been developed, implemented and verified in the PSpice simulation platform. The developed model shows a fair agreement between measured and simulated performance, both for static and dynamic characteristics. Further, the model also takes into account the breakdown voltage characteristics and leakage current. The model scalability has been investigated by switch loss trend analysis, where the energy loss trends has been observed as function of a number of important modeling parameters (e.g., stray inductances, temperatures, gate resistances). The developed model has been shown valid for all regions of device operation at the whole MOSFET temperature operating range. The developed model is used to facilitate converter design at cell level and thereby predict and optimize converter cell performance regarding for instance energy loss.

References [1] A. Nami, L. Jiaqi, F. Dijkhuizen, G.D. Demetriades, Modular multilevel converters for HVDC applications: review on converter cells and functionalities, IEEE Trans. Power Electron. 30 (1) (2015) 18–36. [2] J. Liang, A. Nami, F. Dijkhuizen, P. Tenca, J. Sastry, Current source modular multilevel converter for HVDC and FACTS, in: Proceedings of the IEEE Power Electronics Application (EPE), 2013, pp. 1–10. [3] V. Pala, E.V. Brunt, L. Cheng, M. O'Loughlin, J. Richmond, A. Burk, S.T. Allen, D. Grider, J.W. Palmour, C.J. Scozzie, 10 kV and 15 kV silicon carbide power MOSFETs for next-generation energy conversion and transmission systems, in: Proceedings of the IEEE Energy Conversion Congress and Exposition, 2014, pp. 449–454. [4] J. Quast, D. Hansen, M. Loboda, I. Manning, K. Moeggenborg, S. Mueller, C. Parfeniuk, E. Sanchez, C. Whiteley, High quality 150 mm 4H SiC wafers for power device production, Mater. Sci. Forum 821–823 (2015) 56–59. [5] Y. Sun, G. Feng, L. Lv, W. Qian, Y. Li, J. Luo, J. Zhang, 150 mm 4H–SiC epitaxial layer growth in a warm-wall planetary reactor, Mater. Sci. Forum 821–823 (2015) 153–156. [6] J.L. Hostetler, P. Alexandrov, X. Li, L. Fursin, A. Bhalla, 6.5 kV SiC normally-off JFETs – technology status, IEEE Workshop on Wide Bandgap Power Devices and Applications (WiPDA), 2014, pp. 143–146. [7] H. Miyake, H.N.T. Okuda, T. Kimoto, J. Suda, 21-kV SiC BJTs with spacemodulated junction termination extension, IEEE Electron Device Lett. 33 (2012) 1598–1600. [8] L. Cheng, A.K. Agarwal, C. Capell, M. O'Loughlin, K. Lam, J. Richmond, E. Van Brunt, A. Burk, J.W. Palmour, H. O'Brien, A. Ogunniyi, C. Scozzie, 20 kV, 2 cm2, 4H–SiC gate turn-off thyristors for advanced pulsed power applications, in: Proceedings of the 19th IEEE Pulsed Power Conference, 2013, pp. 1–4. [9] E. Van Brunt, L. Cheng, M. O'Loughlin, J. Richmond, V. Pala, J.W. Palmour, C. W. Tipton, C. Scozzie, 27 kV, 20 A 4H–SiC n-IGBTs, Mater. Sci. Forum 821–823 (2015) 847–850. [10] Q.J. Zhang, A. Agarwal, Design and technology considerations for SiC bipolar devices: BJTs, IGBTs, and GTOs, Phys. Status Solidi (A) 206 (10) (2009) 2431–2456.

176

D. Johannesson, M. Nawaz / Microelectronics Journal 53 (2016) 167–176

[11] J. Millan, P. Godignon, X. Perpina, A. Perez-Tomas, J. Rebollo, A survey of wide bandgap power semiconductor devices, IEEE Trans. Power Electron. 29 (5) (2014) 2155–2163. [12] M. Nawaz, On the evaluation of gate dielectrics for 4H–SiC based power MOSFETs, Act. Passiv. Electron. Compon. 2015 (2015) 12, Article ID 651527. [13] A.C. Ahyi, A. Modic, C. Jiao, Y. Zheng, G. Liu, L.C. Feldman, S. Dhar, Channel mobility improvement in 4H–SiC MOSFETs using a combination of surface counter-doping and NO annealing, Mater. Sci. Forum 821–823 (2015) 693–696. [14] S.-H. Ryu, S. Krishnaswami, B. Hull, J. Richmond, A. Agarwal, A. Hefner, 10 kV, 5 A 4H–SiC power DMOSFET, in: Proceedings of the International Symposium on Power Semiconductor Devices and ICs, 2006, pp. 265–268. [15] H. Robert, S. Buchoff, S. Van Campen, T. McNutt, A.E.B. Bettina, C. Kirby, M. Sherwin, R. Clarke, R. Singh, A 10-kV large-area 4H–SiC power DMOSFET with stable subthreshold behavior independent of temperature, IEEE Trans. Electron Devices 55 (2008) 1807–1815. [16] S. Dhar, A. Modic, G. Liu, A.C. Ahyi, L.C. Feldman, Channel mobility improvement in 4H–SiC MOSFETs using a combination of surface counter-doping with antimony and NO annealing, Mater. Sci. Forum 821–823 (2015) (2015) 693–696. [17] D. Okamoto, M. Sometani, S. Harada, R. Kosugi, Y. Yonezawa, H. Yano, Improved channel mobility in 4H–SiC MOSFETs by Boron passivation, IEEE Electron Device Lett. 35 (12) (2014) 1176–1178. [18] CREE 1.7 kV 225 A SiC MOSFET datasheet, CAS300M17BM2. [19] Infineon Silicon Carbide – Junction Field Effect Transistor, 1.2 kV CoolSiCTM datasheet, IJW120R070T1, Rev. 2.0. [20] GeneSiC 1.2 kV Silicon Carbide Junction Transistor/Schottky Diode Co-pack datasheet, GA100SICP12-227, Mar 2015. [21] J. Lu, K. Sun, H. Wu, Y. Xing, L. Huang, Modeling of SiC MOSFET with temperature dependent parameters and Its applications, in: Proceedings of the IEEE Applied Power Electronics Conference and Exposition, March, 2012, pp. 540–544. [22] M. Mudholkar, S. Ahmed, M.N. Ericson, S.S. Frank, C.L. Britton, H.A. Mantooth, Datasheet driven silicon carbide power MOSFET model, IEEE Trans. Power Electron. 29 (5) (2014) 2220–2228. [23] R. Pratap, R.K. Singh, V. Agarwal, SPICE model development for SiC power MOSFET, in: Proceedings of the IEEE International Conference on Power Electronics, Drives and Energy Systems, 1–5, 2012, pp. 16–19. [24] Zheng Chen, D. Boroyevich, R. Burgos, F. Wang, Characterization and modeling

[25]

[26]

[27]

[28]

[29]

[30]

[31]

[32] [33] [34] [35]

[36]

[37]

of 1.2 kv, 20 A SiC MOSFETs, in: Proceedings of the IEEE Energy Conversion Congress and Exposition, 20–24 Sept., 2009, pp. 1480–1487. K. Sun, H. Wu, J. Lu, Y. Xing, L. Huang, Improved modeling of medium voltage SiC MOSFET within wide temperature range, IEEE Trans. Power Electron. 29 (5) (2014) 2229–2237. Y. Cui, M. Chinthavali, L.M. Tolbert, Temperature dependent PSpice model of SiC power MOSFET, in: Proceedings of the IEEE Applied Power Electronics Conference and Exposition, Feb. 2012, pp. 1698–1704. N. Phankong, T. Funaki, T. Hikihara, A static and dynamic model for a silicon carbide power MOSFET, in: Proceedings European Conference on Power Electronics and Applications (EPE), 2009, pp. 1–10. T.R. McNutt, A.R. Hefner Jr., H.A. Mantooth, D. Berning, S.H. Ryu, Silicon carbide power MOSFET model and parameter extraction sequence, IEEE Trans. Power Electron. 22 (2) (2007) 353–363. R. Fu, A. Grekov, J. Hudgins, A. Mantooth, E. Santi, Power SiC DMOSFET model accounting for nonuniform current distribution in JFET region, IEEE Trans. Ind. Appl. 48 (1) (2012) 181–190. S. Potbhare, N. Goldsman, A. Lelis, J.M. McGarrity, F.B. McLean, D. Habersat, A physical model of high temperature 4H–SiC MOSFETs, IEEE Trans. Electron Devices 55 (8) (2008) 2029–2040. A. Hefner, S. Bouche, Automated parameter extraction software for advanced IGBT modeling, in: Proceedings of the 7th Workshop on Computers in Power Electronics (COMPEL',00), 2000, pp. 10–18. Rohm Semiconductor 1.2 kV 120 A SiC MOSFET datasheet, BSM120D12P2C005, Rev. A. T. McNutt, A. Hefner, A. Mantooth, D. Berning, R. Singh, Compact models for silicon carbide power devices, Solid-State Electron. 48 (2004) 1757–1762. J. Lutz, H. Schlangenotto, U. Scheuermann, R.D. Doncker, Semiconductor Power Devices: Physics, Characteristics, Reliability, Springer-Verlag, 2011. W.J. Schaffer, G.H. Negley, K.G. Irvine, J.W. Palmour, Conductivity anisotropy in epitaxial 6H and 4H SiC, in: Proceedings of the Materials Research Society Symposium, vol. 339, 1994, pp. 595–600. X. Li, Y. Luo, L. Fursin, J.H. Zhao, M. Pan, P. Alexandrov, M. Weiner, On the temperature coefficient of 4H–SiC BJT current gain, Solid State Electron. 47 (2003) 233–239. Y.-R. Zhang, B. Zhang, Z.-J. Li, X.-C. Deng, X.-L. Liu, A novel structure of a high current gain 4H–SiC BJT with a buried layer in the base, Chin. Phys. B 18 (9) (2009) 3995.