Analytical model of 6H-SiC MOSFET

Microelectronic Engineering 65 (2003) 416–427 www.elsevier.com / locate / mee

Analytical model of 6H-SiC MOSFET Anil Kumar a , Navneet Kaushik a , Subhasis Haldar b , Mridula Gupta a ,1 , R.S. Gupta a , * ,2 a

Semiconductor Devices Research Laboratory, Department of Electronic Science, University of Delhi South Campus, New Delhi 110 021, India b Department of Physics, Motilal Nehru College, Benito Juarez Road, New Delhi 110 021 India Received 5 September 2002; received in revised form 26 December 2002; accepted 14 January 2003

Abstract An analytical model of 6H-SiC inversion channel MOSFET is developed incorporating the influence of incomplete dopant ionization. The charge sheet approach is used to evaluate the drain current, transconductance and drain conductance. Maximun transconductance of 46 mS is obtained for Vds 550 mV at a gate voltage of 2.3 V. An explicit analytical expression is also developed which relate the transconductance with interface trap density. It is observed that interface state density has an effect of lowering the transconductance. Some of the results obtained are verified with the experimental data. The interface trap density effects on other device characteristics has also been discussed.  2003 Elsevier Science B.V. All rights reserved. Keywords: 6H-SiC; MOSFET; Ionization; I–V characteristics

1. Introduction Silicon carbide (SiC) possesses many favorable properties making it interesting for high temperature and high power applications. In addition to its remarkable thermal and electronic properties, such as, saturated electron drift velocity of 2310 7 cm / s, thermal conductivity of 3.5 W/ cm 8C and critical breakdown field of 3310 6 V/ cm [1–8], SiC has the added advantage of a thermally grown native oxide, which opens the opportunity for its use in metal-oxide-semiconductor devices. Several workers have studied the thermal oxidation of SiC using MOS capacitors to evaluate * Corresponding author. Tel.: 191-11-2410-5580; fax: 191-11-2688-6606. E-mail address: [email protected] (R.S. Gupta). 1 Member IEEE, Fellow IETE. 2 Sr. Member IEEE, Fellow IETE. 0167-9317 / 03 / $ – see front matter  2003 Elsevier Science B.V. All rights reserved. doi:10.1016 / S0167-9317(03)00053-4

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oxide thickness and quality [9–14]. The native oxide of the SiC is in the form of SiO 2 and produces quite large interface traps densities in p-type samples, which require further studies and research to be improved. The charge sheet model of the metal oxide semiconductor system is widely used for calculating the dependence of the inversion layer charge density on surface potential and gate voltage and thus serves as a starting point for the description of current transport in the MOS transistor [16]. Past descriptions of the charge sheet model have assumed complete ionization of donor and acceptor impurities [16,17]. This approach is appropriate for silicon, which is fully ionized at room temperature. But in the case of SiC the impurity levels are deeper and are not fully ionized at room temperature, hence, require the extension of the charge-sheet model taking into account the effect of incomplete ionization of the dopant impurities. A model [18] exists in the literature, which describe the formulation of the Poisson’s equation including the degenerate surface-free-carrier distribution. In another paper [20], the work is restricted to the surface space charge of a MOS capacitor only, while the present model provides an analytical expression for the drain current, transconductance and drain conductance of the 6H-SiC MOSFET. The interface traps are undesirable both in minority and majority carrier devices, they can be fatal in some majority carrier devices by pinning the Fermi level and disabling the field effect. Even when the interface trap densities are not large enough to pin the Fermi level, they can deteriorate the ability of an external electric field to modulate the channel conductance. The deterioration of the electric field effect is directly reflected in the transconductance, which is a measure of the strength of the field effect. Low transconductance in these devices may be due to the factors such as large contact resistances and interface traps. In the present model, an analytical expression is also developed which relate the transconductance with interface trap densities. The relationship derived can provide insight into the interface state traps impact on the transconductance. Proximity of some of the predicted results with the experimental data confirms the validity of the present model. The effect of interface traps on electrical characteristics has also been incorporated.

2. Model formulation

2.1. Electric field and surface potential The structure analyzed to develop analytical model of 6H-SiC MOSFET for integrated circuits is shown in Fig. 1. The electric field Es at the semiconductor surface is obtained by solving the Poisson’s equation using the incomplete dopant ionization, as described by Arnold [20], is given as qc B LD ] Es 5 ]] Œ2 Fs ´s

(1)

]] kT´s LD 5 ]] q 2c B

(2)

with

œ

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Fig. 1. The schematic diagram of a 6H-SiC MOSFET.

Fs 5 ]]]]]]]]]]]]]]]]]]]]]]]]]]] 4F3 / 2 [w(v, i) 2 u s ] 4F3 / 2 [w(i, c) 1 u s ] Na ln(A 1 ) Nd ln(A 2 ) ]]]]]]] ]]]]]]]]]] ]]] 1 1 1 ]]] 2 1 ] ] cB cB 3Œp exp[w(v, i) 1 uu B u] 3Œp exp[w(i, c) 1 uu B u 1 fc ( y)]

œS

D (3)

1 1 1 ] exp[u s 2 w(a, i)] 2 A 1 5 ]]]]]]]] 1 1 1 ] exp[u B 2 w(a, i)] 2

(4)

1 1 1 ] exp[w(d, i) 2 u s ] 2 A 2 5 ]]]]]]]] 1 1 1 ] exp[w(a, i) 2 u B ] 2

(5)

and where the following notation has been used EP 2 EQ w(P, Q) 5 ]]] kT qf u5] kT

Ef 2 Ei and f 5 ]]] kT

qVc ( y) fc ( y) 5 ]] kT In which EV , EC , Ei and EF represent the valance band edge, the conduction band edge, the intrinsic

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energy level and the Fermi level respectively. u is the dimensionless Fermi potential whose corresponding values at the surface and in the bulk are denoted by u s and u B respectively. fs and fb are the Fermi potentials at the surface and in the bulk respectively, c B is the bulk majority-carrier concentration, and F1 / 2 (h ) is the Fermi–Dirac integral [19]. Vc ( y) is the channel potential, which varies from Vc ( y 5 0) 5 0V at the source end to Vc ( y 5 L) 5VDS at the drain end. The total space charge Q s is related to the gate voltage by Qs Vgs 5Vfb 1 cs 2 ]] Cox

(6)

where Cox 5 ´ox /t ox , is the oxide capacitance per unit area. cs ( 5 fs 2 fb ), is the surface potential, Vfb is the flat band voltage, ´ox is the dielectric permittivity of oxide and t ox is the oxide thickness. Now from Gauss’ law, the total charge density Q s in silicon carbide is given by ] Q s 5 2 qc B LDŒ2 Fs (7) Combining Eqs. (6) and (7) yields ] qc B LDŒ2 Fs Vgs 5Vfb 1 cs 1 ]]]] Cox

(8)

Eq. (8) is an implicit equation in cs and can be solved using iterative procedures. In doing so, surface potential (cs ) has been obtained. The work in [20] was restricted to the surface space change of a MOS capacitor only. In the present work, analytical expressions for the drain current, transconductance, drain conductance of the 6H-SiC MOSFET have been developed. A relationship between transconductance and interface trap density has been developed which indicates how the interface traps effect the transconductance.

2.2. Drain current In the charge sheet model, the inversion layer is assumed to be of zero thickness (i.e., simply a sheet of charges) so that no potential is dropped across it. Also the total space charge Q s is the sum of the inversion or channel charge Q i and the bulk charge Q b , which is given as Q i ( y) 5 2 Cox [Vgs 2Vfb 2 cs ( y)] 2 Q b ( y) where Q b ( y) is the bulk charge density given as ] Q b ( y) 5 2 qc B LDŒ2 Fb Fb includes the depletion terms in (3) ]]]]]]]]]] Na ln (A 1 ) Nd ln (A 2 ) Fb 5 ]]] 1 ]]] 2 1 cB cB

œS

D

(9)

(10)

(11)

Drift component of the drain current is given by [16] dcs Ids 5 2 meffWQ i ( y) ]] dy

(12)

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The mobility reduction due to gate voltage in the strong inversion regime is given by

m0 meff 5 ]]]]] 1 1 u (Vgs 2Vth )

(13)

where m0 is the maximum electron mobility given as

S

S

Nd m0 5 510 3 1 2 0.075 log ]]]5 3 3 10

DDS D T ]] 300

21.5

(14)

Integrating (12), under the boundary conditions

cs ( y) 5 cs0

at

y50

cs ( y) 5 csL

at

y5L

and

and making use of Eq. (9) for Q i yields Ids 5 Ids1 1 Ids2

(15)

where

F

G

W 1 2 Ids1 5 meff ] Cox (Vgs 2Vfb )(csL 2 cs0 ) 2 ] (c sL 2 c 2s0 ) L 2 ] 2 3/2 q(Na 2 Nd )csL q(Na 2 Nd )cs0 W 2Œ2 c B Ld kT Ids2 5 2 meff ] ]]]] ]]]]] 2 M 2 ]]]]] 2 M L 3(Na 2 Nd ) c B kT c B kT

SS

D S

(16)

D D 3/2

(17)

and M 5 M1 1 M2

(18)

qf 2 E 1 E E 2 E 2 qf S DS]Nc lnS1 1 ]12 expS]]]]] DD 1 ]Nc lnS1 1 ]12 expS]]]]] DD 1 1D kT kT

1 M1 5 ln ] 2

a

b

B

a

i

d

d

i

b

B

(19)

S

D SD

Na Nd qfb (Na 2 Nd ) 2 Na (Ea 2 Ei ) 1 Nd (Ed 2 Ei ) 1 M2 5 2 ] 1 ] ln ] 2 ]]]]]]]]]]]]] cB cB 2 c B kT

(20)

The native oxide of the SiC produces quite large interface trap densities p-type samples of 6H-SiC. If the energy dependence of interface state density is known, the charge trapped in interface states and the mobile inversion layer charge and hence the drain current can be accurately calculated for any value of the gate voltage. In the present model, the effect of interface states is incorporated by using a constant interface state density Dit , (7310 11 eV 21 cm 22 as extracted in [15] for the structure used in the present analysis), which is assumed to be located at the plane of the interface but outside of the space charge region. Therefore, the electric field across the oxide must support the charge in interface states, so the gate voltage (V 9gs ) at any given surface potential will depend on the interface state occupancy as V 9gs 5Vgs 1Vit

(21)

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where Vit is the interface trap voltage, which is further related to the interface states trap charges (Q it ) by Q it Vit 5 ]] Cox

(22)

where Q it is determined by the integral of the interface state trap density (Dit ) as E f1cs

Q it (cs ) 5 q

E

Dit (E) dE

(23)

Ev

Therefore, to incorporate the effect of interface states in the analysis the Vgs , is changed as given in Eq. (21).

2.3. Transconductance and drain conductance The transconductance including the effect of interface states can be derived by differentiating drain current [Ids , Eq. (15)] with respect to gate voltage [V 9gs ] taking drain voltage [Vds ] as a constant parameter and is obtained as gm 5 gm1 1 gm2

(24)

where

S

D

S

Dit Dit u W gm1 5 meff ] Cox 1 2 c 9s0 2 c 9s0 ]] Vds 2 ] meff Ids1 1 2 c 9s0 ]] L Cox m0 Cox W ] gm2 5 2 meff ] Œ2 qc B Ld L

SS

q(Na 2 Nd )csL ]]]]] 2M c B kT

D

(25)

D S 1/2

D D9

q(Na 2 Nd )cs0 2 ]]]]] 2 M c B kT

1/2

c s0

(26)

and

S

S

q 2c L N 2 Cox kTFs1 B ]]]]]]]]]]]]]]]]]]] Na ln(A 1 ) Nd ln(A 2 ) Fs1 5 exp[2u s 2 uu B u 1 exp[u s 2 uu B u] 1 ]]] 1 ]]] 2 1 cB cB

N

B d d d c 9s0 5 1 1 ]]]] 2 exp[2u s 2 uu B u 1 exp[u s 2 uu B u] 1 ]] B1 2 ]]B2 Œ] 2c 2c

œ

B

DD

21

(27)

(28)

exp[u s 2 w(a, i)] B1 5 ]]]]]]] 1 1 1 ] exp[u s 2 w(a, i)] 2

(29)

exp[w(d, i) 2 u s ] B2 5 ]]]]]]] 1 1 1 ] exp[w(d, i) 2 u s ] 2

(30)

Similarly, drain conductance is calculated by differentiating drain current [Ids , Eq. (15)] with respect 9 ] as a constant parameter and is given as to drain voltage [Vds ] taking gate voltage [V gs

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S

S

q(Na 2 Nd )csL W 9 2Vit 2Vfb 2 csL ) 2Œ]2 qc B Ld ]]]]] gd 5 m ] Cox (V gs 2M L c B kT

D D 1/2

(31)

2.4. Relationship between transconductance and interface trap density Rewriting Eq. (21) as: V 9gs 5Vgs 1Vit 1 R sg Ids

(32)

where R sg is source to gate resistance. Since Vit , is a function of cs , differentiation of (32) with respect to Ids yields ≠V 9gs ≠Vgs ≠V ≠c ≠Vgs ]] 5 ]] 1 ]]it ]]s ]] 1 R sg ≠Ids ≠Ids ≠cs ≠Vgs ≠Ids

(33)

Eq. (32) can also be written as ≠Vit ≠cs ( g 9m )21 5 g m21 1 ]] ]] g m21 1 R sg ≠cs ≠Vgs

(34)

Evaluating this expression with Eqs. (7), (29) and (31) gives qDit ( g 9m )21 5 g m21 1 ]] c 9s0 g m21 1 R sg Cox

(35)

An ideality factor (h ) can be defined by setting R sg equal to zero and is given by

S

g 9m qDit h 5 ] 5 1 1 ]] c 9s0 gm Cox

D

21

(36)

This relationship applies to cases where the drain voltage is nonzero. From this equation, we can identify some device parameters relating to transconductance. The various assumed values of Dit , along with the corresponding value of ideality factor h at c 9s0 50.98 eV are given in Table 1. The results in the table indicate that the ideality factor h decreases with increase in Dit . Reducing the oxide layer thickness, the oxide capacitance increases, which increases the ideality factor h and hence limits the effect of interface trap density on the transconductance. Table 1 Ideality factor for 6H-SiC MOSFETs with different assumed interface trap densities Dit 5(eV 21 cm 22 )

1310 9

1310 10

1310 11

1310 12

1310 13

h5

0.999

0.986

0.874

0.410

0.065

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Fig. 2. Variation of surface potential with gate voltages for different doping concentration. [L55 mm, W5800 mm, t ox 532 nm, Ea 2 Ev 5200 meV and Ec 2 Ev 53.0 eV].

3. Results and discussion The variation of surface potential, Cs , with the gate voltage for different values of doping concentration is shown in Fig. 2. At low gate voltage Cs , increases rapidly with gate bias and so does the depletion width under the gate. This regime corresponds to the depletion and weak inversion regions of the device operation. At large gate biases, Cs hardly changes. This regime corresponds to the strong inversion of the device, at which fs 5 2 fB . The condition when this happens is often called the condition for threshold and the corresponding gate voltage is called threshold voltage. Fig. 3

Fig. 3. Variation of dcs / dVgs with gate voltage for different doping concentration. [L55 mm, W5800 mm, t ox 532 nm, Ea 2 Ev 5200 meV and Ec 2 Ev 53.0 eV].

424

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Fig. 4. Output characteristics of the 6H-SiC MOSFET. [Dit 57310 11 eV 21 cm 22 , L55 mm, W5800 mm, t ox 532 nm, Ea 2 Ev 5200 meV, Ec 2 Ev 53.0 eV].

shows the variation of dcs / dVgs with gate voltage for different values of doping concentration. In Fig. 3, the points where curves intersect the x-axis give the threshold voltage of the device. As indicated from the curves the threshold voltage increases with increase in the doping concentration level. The Id 2Vd characteristics of 6H-SiC MOSFET for various values of gate voltage incorporating the effect of Dit present in the device analyzed are shown in Fig. 4. It is shown that for a fixed gate voltage, the drain current initially increases linearly with increasing drain voltage and then saturates. The modeled results shown the close proximity with the experimental data [15]. Fig. 5 shows the dependence of drain current on gate voltage for different values of drain voltages. Fig. 6 depicts the variation of transconductance with gate voltage at different values of drain voltages. The inset shows that the transconductance reaches a peak value of 46 mS at a gate voltage of 2.3 V when drain bias is 50 mV, which show the close proximity with the experimental data [15]. The variation of transconductance with drain voltage is shown in Fig. 7. Fig. 8 shows the drain voltage dependence of drain conductance for 6H-SiC MOSFET. The drain conductance having a finite value at higher drain voltages shows that the model is valid in the saturation regime of device operation.

4. Conclusion In the present analysis an analytical model for the various physical characteristics of 6H-SiC MOSFET has been developed. The model includes the effect of partial ionization of deep lying impurity levels and also incorporated the effect of interface states present in the device analyzed. A simple relation to study the effect of the interface trap density on transconductance is developed. It is observed that an interface state density that increases near the band edges has the effect of lowering

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Fig. 5. Transfer characteristics of the 6H-SiC MOSFET. [Dit 57310 11 eV 21 cm 22 , L55 mm, W5800 mm, t ox 532 nm, Ea 2 Ev 5200 meV, Ec 2 Ev 53.0 eV].

Fig. 6. Variation of transconductance with gate voltage for different values of drain bias. [Dit 57310 11 eV 21 cm 22 , L55 mm, W5800 mm, t ox 532 nm, Ea 2 Ev 5200 meV and Ec 2 Ev 53.0 eV].

426

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Fig. 7. Variation of transconductance with drain voltage for different values of gate bias. [Dit 57310 11 eV 21 cm 22 , L55 mm, W5800 mm, t ox 532 nm, Ea 2 Ev 5200 meV and Ec 2 Ev 53.0 eV].

Fig. 8. Drain conductance with drain voltage for different values of gate bias. [Dit 57310 11 eV 21 cm 22 , L55 mm, W5800 mm, t ox 532 nm, Ea 2 Ev 5200 meV and Ec 2 Ev 53.0 eV].

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the 6H-SiC MOSFET transconductance. Due to the non-availability of the experimental results we could not compare some of our predicted results.

Acknowledgements The authors are grateful to Defense Research and Development Organization, Ministry of Defence, Government of India for providing financial support to carry out this work.

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