- Email: [email protected]
20th Design automation conference
190
ConferenceReports
The Proceedings of this conference have been edited by B.J. Davies and have been co-published by IFS (Publications) Ltd. and North-Holland, under
Uomputers in Industry' the title Design Engineering. 1983. 388 pages. ISBN 0-444-86817-8. Price. US$82.75 (USA/Canada), Dfl. 215.00 (rest of the world).
20th Design Automation Conference The ACM-IEEE 20th Design Automation Conference was held in Miami Beach, Florida, U.S.A. from June 24-29, 1983. At this 20th Design Automation Conference, as at the first workshop held in 1964, the goal has remained to provide a forum for an effective technical interchange. Through the reviewed, professional technical presentations, the conference has well served the computer-aided design field. The Chairman of the conference, Charles E. Radke (IBM Corporation, N.Y., U.S.A.), noted in his Message, that over the past 20 years, the often referenced conference proceedings have served as a base for the expanding number of computer-aided design and test publications. These proceedings, together with the ever-increasing numbers of international attendees, have indeed given the Design Automation Conference a recognized international standing. For the second year, the conference has provided, through a fully subscribed s o f t w a r e / hardware vendor exhibit, the increasingly important bridge between the available hardware and software design tools and the technical program. The contents of the technical program and the exhibits have remained separate. T h e Program Chairman of the 1983 Design Automation Conference was Hi//el Ofek (IBM Corporation, N.Y.). The conference Keynote Speaker was John S. Mayo, Executive Vice-President, Network Systems at Bell Laboratories. The title of his talk was "Design Automation - Lessons of the Past, Challenges for the Future". We feature below a summary of the Keynote Speech and a list of all other presentations of the conference.
Keynote Address J.S. Mayo (Bell Labs., Murray Hill, N.J., U.S.A.) began his speech by remarking that during the past two decades, we have learned that design automation is increasingly the only viable way to deal with the complexity of electronic circuits. And DA, he said, will continue to thrive in the future because of ever-increasing complexity. Despite good progress in design automation, experience has taught us that some tough problems still remain. We need to have more powerful aids to enable designers to crystallize their ideas into initial designs. Furthermore, said Mayo, even wellworked areas, such as layout and testing, could be further improved. We also need more powerful tools to manage change, especially to deal with multiple design changes that occur at different stages of the design process. In addition, we must better integrate C A D so that designers can move more gracefully from one phase of design to another. Just as we have learned in the past that design automation must be a comprehensive system, part of a complete design philosophy, we are also recognizing that in the future we will need a comprehensive design and manufacturing system. According to Mayo, to make that happen, we must achieve a dynamic integration of CAE, CAD, CAT and CAM, including factory automation. The integration must be dynamic because each of the tools and factory automation are constantly and independently evolving. Such an integration, asserted Mayo, would smooth and speed up the entire flow from design to manufacture. The optimum level of design automation, Mayo continued in his Address, is an especially important challenge because the cost/benefit tradeoff associated with DA is difficult to manage. Determining the optimum DA level involves quantifying the impact of D A on such factors as quality, productivity, turnaround time, and cost - and
Computers in Industry
the interplay of all these factors. There is a continuing challenge to keep design automation in step with technology. Design automation must not only keep up with electronic circuitry advances, but it must increasingly spur further advances as well, according to Mayo. Finally, Mayo concluded, we are making good progress in merging the two hardware cultures those concerned with chip design aids and those concerned with equipment design aids. But, he said, we must now merge with the culture concerned with software design aids. This merging should help us devise sufficiently powerful design aids for both hardware and software so that the two can be developed in parallel. Such progress will enable us to design better systems - and to do it more effectively. Session 2: Panel Discussion "Central DA and Its Role: An Executive View" (R.J. Camoin, Moderator) Session 3: Hardware Description Languages "Computer Design Language - Version Munich (CDLM): A Modern Multi-Level Language" (W. Hahn) "Programming Languages for Hardware Description" (P. Robinson and J. Dion ) "Zeus: A Hardware Description Language for VLSI" (K.J. Lieberherr and S.E. Knudsen ) "Microprocessor Systems Modeling with MODLAN" (A. Pawlak ) Session 4: I C Design Environment and Tools Chip Assemblers: Concepts and Capabilities (R.H. Katz and S. Weiss) A Vertically Integrated VLSI Design Environment (J. Rosenberg, D. Boyer, J. Dallen, S. Daniel, C. Poirer, J. Poulton, D. Rogers, and N. Weste) IBM FSD Chip Design Methodology (K. Adhoot, R. AIvarodiaz, and L. Crawley ) The IC Module Compiler, A VLSI System Design Aid (N.J. Elias and A.W. Wetzel) Session 5: Testing for L S I - M O S On Fault Detection in CMOS Logic Networks ( K . - W Chiang and Z.G. Vranesic) A New Integrated System for PLA Testing and Verification (F. Somenzi, S. GaL M. Mezzalama, and P. Prinetto) Test Generation for MOS Circuits using D-Algorithm (S.K. Jain and V.D. Agrawal) Test Generation for Scan Design Circuits with Tri-State Modules and Bidirectional Terminals (T. Ogihara, S. Mural Y. Takamatsu, K. Kinoshita, and 1t. Fujiwara ) Session 6: Workshop: Engineering Work Stations Engineering Workstations: Tools or Toys? (S. Sapiro) Session 7." Workshop: Design/Synthesis Design/Synthesis: Workshop Session (J.R. Logan) Session 8: Functional Simulation An Interactive Simulation Facility for the Evaluation of Shared-Resource Architectures ( J.A. Board, Jr., and P.N. Marinos )
Conference Reports
191
Aquarius: Logic Simulation on an Engineering Workstation ( A. Sangster and J. Monahan) BIMOS, an MOS Oriented Multi-Level Logic Simulator (P. Stevens and G. Arnout ) Session 9: Layout Compaction An Algorithm to Compact a VLSI Symbolic Layout with Mixed Constraints ( Y.Z. Liao and C.K. Wong) Graph-Optimization Techniques for IC Layout and Compaction ( G. Kedern and H. Watanabe ) Improved Compaction by Minimized Length of Wires (WL. Schiele ) Session 10: Tutorial Tutorial-Group Technology ( H.R. Prasad ) Session 11: CAD Systems and Software Engineering Computer Aided Software Engineering (CASE) ( F W. Day) Software Architecture for the Implementation of a ComputerAided Engineering System ( C.L. Leath and S.J. Ollanik ) Program Visualization: Graphics Support for Software Development (D. Kramlich, G.P. Brown, R.T. Carling" and C. F Herot) Session 12: Special Hardware Simulators and Their Application HAL: A Block Level Hardware Logic Simulator (T. Sasaki, N. Koike, K. Ohmori, and K. Tomita ) Simulating Pass Transistor Circuits using Logic Simulation Machines ( Z BarzilaL L. Huisman, G. Silberman, D. Tang, and L. Woo) Session 13: V L S I Placement Placement Algorithms for Custom VLSI (K.J. Supowitz and E.A. Slutz ) A Module Interchange Placement Machine (A. losupovici, C. King, and M.A. Breuer) Automatic Placement Algorithms for High Packing Density VLSI (T. Kozawa, H. Terai, T. lshii, M. Hayase, C. Miura, Y. Ogawa, K. Kishida, N. Yamada, and Y. Ohno ) A Placement Algorithm for Array Processors ( D. -J. Chyan and M.A. Breuer ) Session 14: Incorporating the Human Factor in Color CAD Systems Incorporating the Human Factor in Color CAD Systems ( F S . Frome ) Session 15: Testing and Failure Evaluation Diagnosis of TCM Failures in the IBM 3081 Processor Complex ( N.N. Tendolkar) Quality Level and Fault Tolerance for Multichip Modules (K.E. Torku and C.E. Radke) Functional Testing of Digital Systems (K.-W. Lai and D.P. Siewiorek) Critical Path Tracing - An Alternative to Fault Simulation (M. Abramovici, P.R. Menon, and D.T. Miller) Session 16: Formal Design Verification Techniques Formal Verification of a Real-Time Hardware Design (Z.D. Umrtgar and V. Pitchumani) Formal Design Verification of Digital Systems (A.S. Wojcik) Session 17." Panel: Mask Design and Manufacturing Automating Mask Layout and Specification - Panel Session ( R.B. Cutler) Session 18." IBM's Engineering Design System Support for V L S I Design and Verification An Overview of the Design and Verification Subsystem of the Engineering Design System (L.N. Dunn) A Logic System Front-End for Improved Engineering Produc-
192
Conference Reports
tivity ( F. Rubin and P. W. Horstmann ) Structured Design Verification: Function and Timing (C.J. Rimkus, M.R. Wayne, D.D. Cheng~ and F.J. Magistro ) Design through Transformation (J.B. Bendas) Session 19: V L S I Routing Methods Routing Method for VLSI Design using Irregular Cells (H.-J. Rothermel and D.A. Mlynski ) Reducing Channel Density in Standard Cell Layout ( K J . Supowit ) Pictures with Parentheses: Combining Graphics and Procedures in a VLSI Layout Tool (R.N. Mayo and J.K. Ousterhout ) Session 20: Tutorial Importance of Device Independence to the CAD/CAM Industry ( J.R. Warner ) Session 21: M O S Simulation A Multiple Media Delay Simulator for MOS LSI Circuits (K. Okazaki, T. Moriya, and T. Yahara ) Design Aids for the Simulation of Bipolar Gate Arrays (P. Kozak, A.K. Bose, and A. Gupta ) An Improved Switch-Level Simulator for MOS Circuits (V. Ramachandran ) Session 22: Theory of Test and Diagnosis Design for Test Calculus: An Algorithm for DFT Rules Checking ( D.K. Bhaosar) Measured Performance of a Programmed Implementation of the Subscripted D-Algorithm (C. Benmehrez and J . F McDonaM ) Classes of Diagnostic Tests (C. Paulson) Petri Net Based Search Directing Heuristics for Test Generation (K.E. Torku and B.M. Huey) Session 23: Circuit Extracting HEX: An Instruction-Driven Approach to Feature Extraction ( M. Hofmann and U. Lauther) Hierarchical Circuit Extraction with Detailed Parasitic Capacitance ( G.M. Tarolli and W.J. Herman) Symbolic Parasitic Extractor for Circuit Simulation (SPECS) (,I.D. Bastian, C.E. Huan~ M. Ellement, L.P. McNamee, and P.J. Fowler) A Layout Verification System for Analog Bipolar Integrated Circuits ( E. Barke ) Session 24: Solid ModeUing for C A D / C A M Solid Model in Geometric Modelling System: HCAD (S. Tokumasu, Y. Kunitomo, Y. Ohta, S. Yamamoto, and N. Nakafima ) Integration of Solid Modeling and Data Base Management for C A D / C A M (Y.C. Lee and K.S. Fu) UNIGRAFIX (C.H. Sbquin and P.S. Strauss) VERDI: A Computer Aided Design System for Development and City Planning ( M. Bouyat, H. Botta, and J.C. Vignat) Session 25: Workshop: Engineering Work Stations Session 26: Workshop: Technology Design Rules for Design Automation Workshop - Technology Design Rules for Design Automation ( R. Waxman ) Technology Rules - The Other Side of Technology Dependent Code ( M.F. Heilweil) Technology-Dependent Circuit Layout ( R.J. Smith H ) Technology Design Rules - A User's Perspective (T.R. Reinke) Role of Technology Design Rules in Design Automation (G.J. Von Ehr)
Computers in Industry Session 27: Timing Verification Statistical Techniques of Timing Verification (J.H. Shelly and D.R. Tryon ) Path Delay Analysis for Hierarchical Building Block Layout System (E. Tamura, K. Ogawa, and 7". Nakano) Timing Analysis for nMOS VLSI (N.P. Jouppi) Session 28: VLSI Design Aids" The Effect of Register-Transfer Design Tradeoffs on Chip Area and Performance ( J.J. Granacki and A.C. Parker) VGAUA: The Variable Geometry Automated Universal Array Layout System (D.C. Smith, R. Noto, F. Borgini, S.S. Sharma, and J. C. Werbickas ) APSS: An Automatic PLA Synthesis System (M. W Stebinsky, M . F McGinnis, J.C. Werbickas, R.N, Putatunda, and A: Feller) Session 29: Integrating P W B CAD and C A M Integrated Computer Aided Design, Documentation, and Manufacturing System for PCB Electronics (M. Teroonen, 1t. Lehikoinen, and T. Mukari) Minimizing PWB NC Drilling (.I.D. Litke) Simplification of CNC Programming for PWB Routing (J. Drier) Session 30: Placement Algorithms Partitioning and Placement Technique for Bus-Structured PWB ( G. Odawara, K. lijima, and T Kiyomatsu ) Linear Ordering and Application to Placement (S. Kang) Placement of Circuit Modules using a Graph Space Approach ( K. Fukunanga, S. Yamada, H.H. Stone, and T. Kasai) Session 31: Synthesis 1 Computer-Aided Partitioning of Behavioral Hardware Descriptions ( M. C. McFarland, Jr.) The VLSI Design Automation Assistant: Prototype System (T.J. Kowalski and D.E. Thomas) A Method of Automatic Data Path Synthesis (C. Y. Hitchcock I I I and D.E. Thomas) Facet: A Procedure for the Automated Synthesis of Digital Systems ( C. -J. Tseng and D.P. Siewiorek ) Session 32: A Set of Functional Design Tools for VLSI Systems N.mPc: A Perspective ( C. W. Rose, G.M. Ordy, and E L Parke ) Functional Models for VLSI Design (R.L. Druian) Functional Simulation Shortens the Development Cycle of a New Computer ( R. Cheng, B. Griffin, K. Katsumata, and J. Welsh ) The N.2 System (G.M. Ordy and C. V~ Rose) Session 33: Computer Aided Programming Computer Aided Programming (P. Bassett) Session 34: PLA Minimization Techniques PLEASURE: A Computer Program for Simple/Multiple Constrained/Unconstrained Folding of Programmable Logic Arrays ( G. De Michelli and A. Sangiooanni-Vincentelli) Bounds on the Saved Area Ratio Due to PLA Folding ( W. Liu and D.E. Atkins) PRONTO: Quick PLA Product Reduction (J.F. MartinezCarballido and V.M. Powers) Optimum Reduction of Programmable Logic Array (T. C. Hu and Y.S. Kuo) Session 35: Panel: Robotics Panel Discussion: Robots in Design (E.L. Hall) Session 36: Synthesis II Heuristics for the Circuit Realization Problem (J. Cohoon and S. Sahni)
Computers in Industry Binary Decision Diagrams: From Abstract Representations to Physical Implementations ( J.S. Matos and J. I~ OldfieM) Some Computer Aided Engineering System Design Principles ( H.L. Nattrass and G.K. Okita) Session 37: Gate Array Routing General River Routing Algorithm (C.-P. Hsu) A New Channel Routing Problem (H. W Leong and C.L. Liu) Hierarchical Channel Router ( M. Burstein and R. Pelavin ) Session 38: Panel." The Future of the Relational Data Model for CA D." Close Encounters of the Third Normal Form Tutorial/Panel Workshop ( S. Wong) Tutorial: The Relational Data Model for Design Automation ( M.N. Haynie) Session 39: Simulation Aids Edisim and Edicap: Graphical Simulator Interfaces (D.D. Hill) An Algebra for Logic Strength Simulation (P.L. Flake, P.R. Moorby, and G. Musgrave) A Data Structure for MOS Circuits (C.-Y. Lo, H.N. Nham, and A.K. Bose) Session 40." Multi-Company Collaboration in Solving Design Problems VHSIC Hardware Description (VHDL) Development Program ( A. Dewey) The UK5000 - Successful Collaborative Development of an Integrated Design System for a 5000 Gate CMOS Array with Built-ln Test ( J.R. Gierson, B. Cosgrove, R. Daniel, R.E. Halliwell, LH. Kirk, J.C. Knight, J.C. McLean, J.M. McGrail, and C.O. Newton) Placement of Irregular Circuit Elements on Non-Uniform Gate Arrays (1.H. Kirk, P.D. Crowhurst, J.A. Skingley, J.D. Bowman, and G.L. Taylor) Automatic Routing of Double Layer Gate Arrays using a Moving Cursor ( B.D. Prazic and M.A. Bozier) Optimisation of Global Routing for the UK5000 Gate Array by Iteration (C.O. Newton and P.A. Young) Automatic Layout for Gate Arrays with One Layer of Metal ( P. Robinson) Session 41: Gate Array Design An Over-Cell Gate Array Channel Router (H.E. Krohn) A New Statistical Model for Gate Array Routing (A. El Gamal and Z.A. Syed) A Topology for Semicustom Array-Structured LSI Devices and Their Automatic Customisation (P. Jennings) Session 42: Computer Integrated Manufacturing Automatic Batch Processing in Multilayer Ceramic Metallization ( N. DalCero ) C A D / C A M = The Foundation for Computer Integrated Manufacturing ( R.L. Simon) Session 43: Workshop: Technology Design Rules for Design Automation
Conference Reports
193
Session 44: Workshop: Design / Synthesis Session 45: Short Papers-I Test Strategy for Microprocessors ( S.K. Jain and A.K. Susskind ) A Design Verification Methodology Based on Concurrent Simulation and Clock Suppression (E. Ulrich) Total Stuck-at-Fault Testing by Circuit Transformation (A.S. LaPaugh and R.J. Lipton) Testing for Bridging Faults (Shorts) in CMOS Circuits (J.M. A cken ) ILS - Interactive Logic Simulator ( G.D. Jordan, B.B. Popli, and R.M. Apte) ACE: A Circuit Extractor (A. Gupta) Session 46: Short Papers-11 MACH: A High-Hitting Pattern Checker for VLSI Mask Data ( A. Tsukizoe, J. Sakemi, T. Kozawa, and H. Fukuda ) Consistency Checking for MOS/VLSI Circuits (N.-S. Chang and R.M. Apte) Space Efficient Algorithms for VLSI Artwork Analysis (T.S. Szymanski and C.J. Van Wyk ) Experiments with the SLIM Circuit Compactor (R.C. McGarity and D.P. Siewiorek ) CAF: A Computer-Assisted Floorplanning Tool (A. Leblond) Laying the Power and Ground Wires on a VLSI Chip (A.S. Mouhon ) Session 47: Short P a p e r s - l l l The Transfer of University Software for lndustrj Use (R. Wyleczuk, L. Meyer, and G. Babcock ) A Graphical Tool for Conceptual Design of Data Base Applications ( C. Batini and C. Costa) UCAD: Building Design Automation with General Purpose Software Tools on UNIX (J.H. Tomkinson) Behavioral Level Transformation in the CMU-DA System (R.A. Walker and D.E. Thomas) HOPLA-PLA Optimization and Synthesis ( S. Wimer and N. Sharfman ) International Connection Problem in Large Optimized PLAs ( S. Chuquillanqui )
The Proceedings of the ACM IEEE 20th Design Automation Conference may be ordered prepaid from: ACM, Order Department, P.O. Box 64145, Baltimore, Md. 21264, U.S.A. ACM Order Number 477830, or IEEE Computer Society, Order Department, 10662 Los Vaqueros Circle, Los Alamitos, Calif. 90720, U.S.A. IEEE Order No. 447. 814 pages. Price: US $33.00 (members), US $66.00 (non-members).
ConferenceReports
The Proceedings of this conference have been edited by B.J. Davies and have been co-published by IFS (Publications) Ltd. and North-Holland, under
Uomputers in Industry' the title Design Engineering. 1983. 388 pages. ISBN 0-444-86817-8. Price. US$82.75 (USA/Canada), Dfl. 215.00 (rest of the world).
20th Design Automation Conference The ACM-IEEE 20th Design Automation Conference was held in Miami Beach, Florida, U.S.A. from June 24-29, 1983. At this 20th Design Automation Conference, as at the first workshop held in 1964, the goal has remained to provide a forum for an effective technical interchange. Through the reviewed, professional technical presentations, the conference has well served the computer-aided design field. The Chairman of the conference, Charles E. Radke (IBM Corporation, N.Y., U.S.A.), noted in his Message, that over the past 20 years, the often referenced conference proceedings have served as a base for the expanding number of computer-aided design and test publications. These proceedings, together with the ever-increasing numbers of international attendees, have indeed given the Design Automation Conference a recognized international standing. For the second year, the conference has provided, through a fully subscribed s o f t w a r e / hardware vendor exhibit, the increasingly important bridge between the available hardware and software design tools and the technical program. The contents of the technical program and the exhibits have remained separate. T h e Program Chairman of the 1983 Design Automation Conference was Hi//el Ofek (IBM Corporation, N.Y.). The conference Keynote Speaker was John S. Mayo, Executive Vice-President, Network Systems at Bell Laboratories. The title of his talk was "Design Automation - Lessons of the Past, Challenges for the Future". We feature below a summary of the Keynote Speech and a list of all other presentations of the conference.
Keynote Address J.S. Mayo (Bell Labs., Murray Hill, N.J., U.S.A.) began his speech by remarking that during the past two decades, we have learned that design automation is increasingly the only viable way to deal with the complexity of electronic circuits. And DA, he said, will continue to thrive in the future because of ever-increasing complexity. Despite good progress in design automation, experience has taught us that some tough problems still remain. We need to have more powerful aids to enable designers to crystallize their ideas into initial designs. Furthermore, said Mayo, even wellworked areas, such as layout and testing, could be further improved. We also need more powerful tools to manage change, especially to deal with multiple design changes that occur at different stages of the design process. In addition, we must better integrate C A D so that designers can move more gracefully from one phase of design to another. Just as we have learned in the past that design automation must be a comprehensive system, part of a complete design philosophy, we are also recognizing that in the future we will need a comprehensive design and manufacturing system. According to Mayo, to make that happen, we must achieve a dynamic integration of CAE, CAD, CAT and CAM, including factory automation. The integration must be dynamic because each of the tools and factory automation are constantly and independently evolving. Such an integration, asserted Mayo, would smooth and speed up the entire flow from design to manufacture. The optimum level of design automation, Mayo continued in his Address, is an especially important challenge because the cost/benefit tradeoff associated with DA is difficult to manage. Determining the optimum DA level involves quantifying the impact of D A on such factors as quality, productivity, turnaround time, and cost - and
Computers in Industry
the interplay of all these factors. There is a continuing challenge to keep design automation in step with technology. Design automation must not only keep up with electronic circuitry advances, but it must increasingly spur further advances as well, according to Mayo. Finally, Mayo concluded, we are making good progress in merging the two hardware cultures those concerned with chip design aids and those concerned with equipment design aids. But, he said, we must now merge with the culture concerned with software design aids. This merging should help us devise sufficiently powerful design aids for both hardware and software so that the two can be developed in parallel. Such progress will enable us to design better systems - and to do it more effectively. Session 2: Panel Discussion "Central DA and Its Role: An Executive View" (R.J. Camoin, Moderator) Session 3: Hardware Description Languages "Computer Design Language - Version Munich (CDLM): A Modern Multi-Level Language" (W. Hahn) "Programming Languages for Hardware Description" (P. Robinson and J. Dion ) "Zeus: A Hardware Description Language for VLSI" (K.J. Lieberherr and S.E. Knudsen ) "Microprocessor Systems Modeling with MODLAN" (A. Pawlak ) Session 4: I C Design Environment and Tools Chip Assemblers: Concepts and Capabilities (R.H. Katz and S. Weiss) A Vertically Integrated VLSI Design Environment (J. Rosenberg, D. Boyer, J. Dallen, S. Daniel, C. Poirer, J. Poulton, D. Rogers, and N. Weste) IBM FSD Chip Design Methodology (K. Adhoot, R. AIvarodiaz, and L. Crawley ) The IC Module Compiler, A VLSI System Design Aid (N.J. Elias and A.W. Wetzel) Session 5: Testing for L S I - M O S On Fault Detection in CMOS Logic Networks ( K . - W Chiang and Z.G. Vranesic) A New Integrated System for PLA Testing and Verification (F. Somenzi, S. GaL M. Mezzalama, and P. Prinetto) Test Generation for MOS Circuits using D-Algorithm (S.K. Jain and V.D. Agrawal) Test Generation for Scan Design Circuits with Tri-State Modules and Bidirectional Terminals (T. Ogihara, S. Mural Y. Takamatsu, K. Kinoshita, and 1t. Fujiwara ) Session 6: Workshop: Engineering Work Stations Engineering Workstations: Tools or Toys? (S. Sapiro) Session 7." Workshop: Design/Synthesis Design/Synthesis: Workshop Session (J.R. Logan) Session 8: Functional Simulation An Interactive Simulation Facility for the Evaluation of Shared-Resource Architectures ( J.A. Board, Jr., and P.N. Marinos )
Conference Reports
191
Aquarius: Logic Simulation on an Engineering Workstation ( A. Sangster and J. Monahan) BIMOS, an MOS Oriented Multi-Level Logic Simulator (P. Stevens and G. Arnout ) Session 9: Layout Compaction An Algorithm to Compact a VLSI Symbolic Layout with Mixed Constraints ( Y.Z. Liao and C.K. Wong) Graph-Optimization Techniques for IC Layout and Compaction ( G. Kedern and H. Watanabe ) Improved Compaction by Minimized Length of Wires (WL. Schiele ) Session 10: Tutorial Tutorial-Group Technology ( H.R. Prasad ) Session 11: CAD Systems and Software Engineering Computer Aided Software Engineering (CASE) ( F W. Day) Software Architecture for the Implementation of a ComputerAided Engineering System ( C.L. Leath and S.J. Ollanik ) Program Visualization: Graphics Support for Software Development (D. Kramlich, G.P. Brown, R.T. Carling" and C. F Herot) Session 12: Special Hardware Simulators and Their Application HAL: A Block Level Hardware Logic Simulator (T. Sasaki, N. Koike, K. Ohmori, and K. Tomita ) Simulating Pass Transistor Circuits using Logic Simulation Machines ( Z BarzilaL L. Huisman, G. Silberman, D. Tang, and L. Woo) Session 13: V L S I Placement Placement Algorithms for Custom VLSI (K.J. Supowitz and E.A. Slutz ) A Module Interchange Placement Machine (A. losupovici, C. King, and M.A. Breuer) Automatic Placement Algorithms for High Packing Density VLSI (T. Kozawa, H. Terai, T. lshii, M. Hayase, C. Miura, Y. Ogawa, K. Kishida, N. Yamada, and Y. Ohno ) A Placement Algorithm for Array Processors ( D. -J. Chyan and M.A. Breuer ) Session 14: Incorporating the Human Factor in Color CAD Systems Incorporating the Human Factor in Color CAD Systems ( F S . Frome ) Session 15: Testing and Failure Evaluation Diagnosis of TCM Failures in the IBM 3081 Processor Complex ( N.N. Tendolkar) Quality Level and Fault Tolerance for Multichip Modules (K.E. Torku and C.E. Radke) Functional Testing of Digital Systems (K.-W. Lai and D.P. Siewiorek) Critical Path Tracing - An Alternative to Fault Simulation (M. Abramovici, P.R. Menon, and D.T. Miller) Session 16: Formal Design Verification Techniques Formal Verification of a Real-Time Hardware Design (Z.D. Umrtgar and V. Pitchumani) Formal Design Verification of Digital Systems (A.S. Wojcik) Session 17." Panel: Mask Design and Manufacturing Automating Mask Layout and Specification - Panel Session ( R.B. Cutler) Session 18." IBM's Engineering Design System Support for V L S I Design and Verification An Overview of the Design and Verification Subsystem of the Engineering Design System (L.N. Dunn) A Logic System Front-End for Improved Engineering Produc-
192
Conference Reports
tivity ( F. Rubin and P. W. Horstmann ) Structured Design Verification: Function and Timing (C.J. Rimkus, M.R. Wayne, D.D. Cheng~ and F.J. Magistro ) Design through Transformation (J.B. Bendas) Session 19: V L S I Routing Methods Routing Method for VLSI Design using Irregular Cells (H.-J. Rothermel and D.A. Mlynski ) Reducing Channel Density in Standard Cell Layout ( K J . Supowit ) Pictures with Parentheses: Combining Graphics and Procedures in a VLSI Layout Tool (R.N. Mayo and J.K. Ousterhout ) Session 20: Tutorial Importance of Device Independence to the CAD/CAM Industry ( J.R. Warner ) Session 21: M O S Simulation A Multiple Media Delay Simulator for MOS LSI Circuits (K. Okazaki, T. Moriya, and T. Yahara ) Design Aids for the Simulation of Bipolar Gate Arrays (P. Kozak, A.K. Bose, and A. Gupta ) An Improved Switch-Level Simulator for MOS Circuits (V. Ramachandran ) Session 22: Theory of Test and Diagnosis Design for Test Calculus: An Algorithm for DFT Rules Checking ( D.K. Bhaosar) Measured Performance of a Programmed Implementation of the Subscripted D-Algorithm (C. Benmehrez and J . F McDonaM ) Classes of Diagnostic Tests (C. Paulson) Petri Net Based Search Directing Heuristics for Test Generation (K.E. Torku and B.M. Huey) Session 23: Circuit Extracting HEX: An Instruction-Driven Approach to Feature Extraction ( M. Hofmann and U. Lauther) Hierarchical Circuit Extraction with Detailed Parasitic Capacitance ( G.M. Tarolli and W.J. Herman) Symbolic Parasitic Extractor for Circuit Simulation (SPECS) (,I.D. Bastian, C.E. Huan~ M. Ellement, L.P. McNamee, and P.J. Fowler) A Layout Verification System for Analog Bipolar Integrated Circuits ( E. Barke ) Session 24: Solid ModeUing for C A D / C A M Solid Model in Geometric Modelling System: HCAD (S. Tokumasu, Y. Kunitomo, Y. Ohta, S. Yamamoto, and N. Nakafima ) Integration of Solid Modeling and Data Base Management for C A D / C A M (Y.C. Lee and K.S. Fu) UNIGRAFIX (C.H. Sbquin and P.S. Strauss) VERDI: A Computer Aided Design System for Development and City Planning ( M. Bouyat, H. Botta, and J.C. Vignat) Session 25: Workshop: Engineering Work Stations Session 26: Workshop: Technology Design Rules for Design Automation Workshop - Technology Design Rules for Design Automation ( R. Waxman ) Technology Rules - The Other Side of Technology Dependent Code ( M.F. Heilweil) Technology-Dependent Circuit Layout ( R.J. Smith H ) Technology Design Rules - A User's Perspective (T.R. Reinke) Role of Technology Design Rules in Design Automation (G.J. Von Ehr)
Computers in Industry Session 27: Timing Verification Statistical Techniques of Timing Verification (J.H. Shelly and D.R. Tryon ) Path Delay Analysis for Hierarchical Building Block Layout System (E. Tamura, K. Ogawa, and 7". Nakano) Timing Analysis for nMOS VLSI (N.P. Jouppi) Session 28: VLSI Design Aids" The Effect of Register-Transfer Design Tradeoffs on Chip Area and Performance ( J.J. Granacki and A.C. Parker) VGAUA: The Variable Geometry Automated Universal Array Layout System (D.C. Smith, R. Noto, F. Borgini, S.S. Sharma, and J. C. Werbickas ) APSS: An Automatic PLA Synthesis System (M. W Stebinsky, M . F McGinnis, J.C. Werbickas, R.N, Putatunda, and A: Feller) Session 29: Integrating P W B CAD and C A M Integrated Computer Aided Design, Documentation, and Manufacturing System for PCB Electronics (M. Teroonen, 1t. Lehikoinen, and T. Mukari) Minimizing PWB NC Drilling (.I.D. Litke) Simplification of CNC Programming for PWB Routing (J. Drier) Session 30: Placement Algorithms Partitioning and Placement Technique for Bus-Structured PWB ( G. Odawara, K. lijima, and T Kiyomatsu ) Linear Ordering and Application to Placement (S. Kang) Placement of Circuit Modules using a Graph Space Approach ( K. Fukunanga, S. Yamada, H.H. Stone, and T. Kasai) Session 31: Synthesis 1 Computer-Aided Partitioning of Behavioral Hardware Descriptions ( M. C. McFarland, Jr.) The VLSI Design Automation Assistant: Prototype System (T.J. Kowalski and D.E. Thomas) A Method of Automatic Data Path Synthesis (C. Y. Hitchcock I I I and D.E. Thomas) Facet: A Procedure for the Automated Synthesis of Digital Systems ( C. -J. Tseng and D.P. Siewiorek ) Session 32: A Set of Functional Design Tools for VLSI Systems N.mPc: A Perspective ( C. W. Rose, G.M. Ordy, and E L Parke ) Functional Models for VLSI Design (R.L. Druian) Functional Simulation Shortens the Development Cycle of a New Computer ( R. Cheng, B. Griffin, K. Katsumata, and J. Welsh ) The N.2 System (G.M. Ordy and C. V~ Rose) Session 33: Computer Aided Programming Computer Aided Programming (P. Bassett) Session 34: PLA Minimization Techniques PLEASURE: A Computer Program for Simple/Multiple Constrained/Unconstrained Folding of Programmable Logic Arrays ( G. De Michelli and A. Sangiooanni-Vincentelli) Bounds on the Saved Area Ratio Due to PLA Folding ( W. Liu and D.E. Atkins) PRONTO: Quick PLA Product Reduction (J.F. MartinezCarballido and V.M. Powers) Optimum Reduction of Programmable Logic Array (T. C. Hu and Y.S. Kuo) Session 35: Panel: Robotics Panel Discussion: Robots in Design (E.L. Hall) Session 36: Synthesis II Heuristics for the Circuit Realization Problem (J. Cohoon and S. Sahni)
Computers in Industry Binary Decision Diagrams: From Abstract Representations to Physical Implementations ( J.S. Matos and J. I~ OldfieM) Some Computer Aided Engineering System Design Principles ( H.L. Nattrass and G.K. Okita) Session 37: Gate Array Routing General River Routing Algorithm (C.-P. Hsu) A New Channel Routing Problem (H. W Leong and C.L. Liu) Hierarchical Channel Router ( M. Burstein and R. Pelavin ) Session 38: Panel." The Future of the Relational Data Model for CA D." Close Encounters of the Third Normal Form Tutorial/Panel Workshop ( S. Wong) Tutorial: The Relational Data Model for Design Automation ( M.N. Haynie) Session 39: Simulation Aids Edisim and Edicap: Graphical Simulator Interfaces (D.D. Hill) An Algebra for Logic Strength Simulation (P.L. Flake, P.R. Moorby, and G. Musgrave) A Data Structure for MOS Circuits (C.-Y. Lo, H.N. Nham, and A.K. Bose) Session 40." Multi-Company Collaboration in Solving Design Problems VHSIC Hardware Description (VHDL) Development Program ( A. Dewey) The UK5000 - Successful Collaborative Development of an Integrated Design System for a 5000 Gate CMOS Array with Built-ln Test ( J.R. Gierson, B. Cosgrove, R. Daniel, R.E. Halliwell, LH. Kirk, J.C. Knight, J.C. McLean, J.M. McGrail, and C.O. Newton) Placement of Irregular Circuit Elements on Non-Uniform Gate Arrays (1.H. Kirk, P.D. Crowhurst, J.A. Skingley, J.D. Bowman, and G.L. Taylor) Automatic Routing of Double Layer Gate Arrays using a Moving Cursor ( B.D. Prazic and M.A. Bozier) Optimisation of Global Routing for the UK5000 Gate Array by Iteration (C.O. Newton and P.A. Young) Automatic Layout for Gate Arrays with One Layer of Metal ( P. Robinson) Session 41: Gate Array Design An Over-Cell Gate Array Channel Router (H.E. Krohn) A New Statistical Model for Gate Array Routing (A. El Gamal and Z.A. Syed) A Topology for Semicustom Array-Structured LSI Devices and Their Automatic Customisation (P. Jennings) Session 42: Computer Integrated Manufacturing Automatic Batch Processing in Multilayer Ceramic Metallization ( N. DalCero ) C A D / C A M = The Foundation for Computer Integrated Manufacturing ( R.L. Simon) Session 43: Workshop: Technology Design Rules for Design Automation
Conference Reports
193
Session 44: Workshop: Design / Synthesis Session 45: Short Papers-I Test Strategy for Microprocessors ( S.K. Jain and A.K. Susskind ) A Design Verification Methodology Based on Concurrent Simulation and Clock Suppression (E. Ulrich) Total Stuck-at-Fault Testing by Circuit Transformation (A.S. LaPaugh and R.J. Lipton) Testing for Bridging Faults (Shorts) in CMOS Circuits (J.M. A cken ) ILS - Interactive Logic Simulator ( G.D. Jordan, B.B. Popli, and R.M. Apte) ACE: A Circuit Extractor (A. Gupta) Session 46: Short Papers-11 MACH: A High-Hitting Pattern Checker for VLSI Mask Data ( A. Tsukizoe, J. Sakemi, T. Kozawa, and H. Fukuda ) Consistency Checking for MOS/VLSI Circuits (N.-S. Chang and R.M. Apte) Space Efficient Algorithms for VLSI Artwork Analysis (T.S. Szymanski and C.J. Van Wyk ) Experiments with the SLIM Circuit Compactor (R.C. McGarity and D.P. Siewiorek ) CAF: A Computer-Assisted Floorplanning Tool (A. Leblond) Laying the Power and Ground Wires on a VLSI Chip (A.S. Mouhon ) Session 47: Short P a p e r s - l l l The Transfer of University Software for lndustrj Use (R. Wyleczuk, L. Meyer, and G. Babcock ) A Graphical Tool for Conceptual Design of Data Base Applications ( C. Batini and C. Costa) UCAD: Building Design Automation with General Purpose Software Tools on UNIX (J.H. Tomkinson) Behavioral Level Transformation in the CMU-DA System (R.A. Walker and D.E. Thomas) HOPLA-PLA Optimization and Synthesis ( S. Wimer and N. Sharfman ) International Connection Problem in Large Optimized PLAs ( S. Chuquillanqui )
The Proceedings of the ACM IEEE 20th Design Automation Conference may be ordered prepaid from: ACM, Order Department, P.O. Box 64145, Baltimore, Md. 21264, U.S.A. ACM Order Number 477830, or IEEE Computer Society, Order Department, 10662 Los Vaqueros Circle, Los Alamitos, Calif. 90720, U.S.A. IEEE Order No. 447. 814 pages. Price: US $33.00 (members), US $66.00 (non-members).