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4401904 Delay circuit used in semiconductor memory device
194
New Patents
4403396 S E M I C O N D U C T O R DEVICE DESIGN AND PROCESS Richard J Stein assigned to G T E Laboratories Incorporated 58 58 5~ 54
54
54
4O
A method for fabricating a gate-source structure for a recessed-gate static induction transistor. Source impurities are implanted prior to forming the recessed gates. The recessed gates are formed by a first isotropic etching step and a second anisotropic etching step which results in a unique overhanging protective layer used to protect the walls of the grooves during implantation of gate impurities in the bottom of the grooves. Implantations are driven and activated to form gate and source regions, the protective layer is removed and metal deposited to form electrodes. The procedure minimizes the required number of masking steps and associated mask registration problems.
4403307 SEMICONDUCTOR MEMORY DEVICE Koh-ichi Maeda, Yokohama, Japan assigned to Fujitsu Limited 16
0 p4
15
16
control gates are connected to a first signal lines, the drains are connected respectively to the different second and third signal lines and the sources are grounded.
4403306 SEMICONDUCTOR MEMORY O P E R A B L E AS STATIC R A M OR EAROM Kaoru Tokushige, Masayoshi Nakane, Yokohama, Japan assigned to Tokyo Shibaura Denki Kabushiki Kaisha A semiconductor memory comprises a CMOS flip-flop circuit and a pair of N-channel MNOS (Metal Nitride Oxide Semiconductor) transistors. A first MNOS transistor is connected between a first pair of CMOS transistors and a second MNOS transistor is connected between a second pair of CMOS transistors. The gates of the first and second MNOS transistors are connected to a control signal line. The control signal line is normally maintained at a reference voltage. When an erase pulse of first polarity is supplied to the control signal line, the first and second MNOS transistors are turned ON, so that the memory operates in the static RAM mode. When a write pulse of second polarity is supplied to the control signal line, the data stored in the static RAM mode becomes nonvolatile.
4403241 M E T H O D FOR E T C H I N G III-V SEMICONDUCTORS AND DEVICES M A D E BY THIS METHOD Alexander D Butherus, Lucian D'Asaro assigned to Bell Telephone Laboratories Incorporated
The present invention discloses a semiconductor memory device composed of double gate type field effect transistors which have control gate and floating gate for accumulating charges. The conditions for optimum charge injection writing and for optimum reading of this semiconductor memory device are mutually inconsistent. In order to satisfy said two conditions, the present invention provides a charge injection transistor and a read transistor, wherein the floating gate of both transistors are electrically connected, the
2,~,~1. ~
2,,
~,
The use of an anisotropic etchant containing BC13 and a source of atomic chlorine for III-V semiconductor materials has yielded improved results for semiconductor devices. For example, via gallium arsenide field effect transistors produced using this anisotropic etchant to fabricate via holes exhibit excellent electrical characteristics.
New Patents
4403396 S E M I C O N D U C T O R DEVICE DESIGN AND PROCESS Richard J Stein assigned to G T E Laboratories Incorporated 58 58 5~ 54
54
54
4O
A method for fabricating a gate-source structure for a recessed-gate static induction transistor. Source impurities are implanted prior to forming the recessed gates. The recessed gates are formed by a first isotropic etching step and a second anisotropic etching step which results in a unique overhanging protective layer used to protect the walls of the grooves during implantation of gate impurities in the bottom of the grooves. Implantations are driven and activated to form gate and source regions, the protective layer is removed and metal deposited to form electrodes. The procedure minimizes the required number of masking steps and associated mask registration problems.
4403307 SEMICONDUCTOR MEMORY DEVICE Koh-ichi Maeda, Yokohama, Japan assigned to Fujitsu Limited 16
0 p4
15
16
control gates are connected to a first signal lines, the drains are connected respectively to the different second and third signal lines and the sources are grounded.
4403306 SEMICONDUCTOR MEMORY O P E R A B L E AS STATIC R A M OR EAROM Kaoru Tokushige, Masayoshi Nakane, Yokohama, Japan assigned to Tokyo Shibaura Denki Kabushiki Kaisha A semiconductor memory comprises a CMOS flip-flop circuit and a pair of N-channel MNOS (Metal Nitride Oxide Semiconductor) transistors. A first MNOS transistor is connected between a first pair of CMOS transistors and a second MNOS transistor is connected between a second pair of CMOS transistors. The gates of the first and second MNOS transistors are connected to a control signal line. The control signal line is normally maintained at a reference voltage. When an erase pulse of first polarity is supplied to the control signal line, the first and second MNOS transistors are turned ON, so that the memory operates in the static RAM mode. When a write pulse of second polarity is supplied to the control signal line, the data stored in the static RAM mode becomes nonvolatile.
4403241 M E T H O D FOR E T C H I N G III-V SEMICONDUCTORS AND DEVICES M A D E BY THIS METHOD Alexander D Butherus, Lucian D'Asaro assigned to Bell Telephone Laboratories Incorporated
The present invention discloses a semiconductor memory device composed of double gate type field effect transistors which have control gate and floating gate for accumulating charges. The conditions for optimum charge injection writing and for optimum reading of this semiconductor memory device are mutually inconsistent. In order to satisfy said two conditions, the present invention provides a charge injection transistor and a read transistor, wherein the floating gate of both transistors are electrically connected, the
2,~,~1. ~
2,,
~,
The use of an anisotropic etchant containing BC13 and a source of atomic chlorine for III-V semiconductor materials has yielded improved results for semiconductor devices. For example, via gallium arsenide field effect transistors produced using this anisotropic etchant to fabricate via holes exhibit excellent electrical characteristics.