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4409672 Dynamic semiconductor memory device
New Patents
191
4409674 SEMICONDUCTOR MEMORY 3
Yukio Takahashi, Sakata, Japan assigned to Fujitsu Limited In a semiconductor memory which is provided with a memory cell array, word lines and bit lines for selecting a desired one of memory cells of the memory cell array and a detector circuit for detecting a read current of the selected memory cell, the detector circuit is composed of a pair of transistors having their bases cross-connected so that a hysteresis characteristic is provided by flowing a current in the transistors, and the current is controlled by a hysteresis control circuit to flow only when all word line potentials monitored by the hysteresis control circuit have become lower than a predetermined value, whereby to remove the influence of a noise in the detection of read information of the selected memory cell.
4409672 DYNAMIC SEMICONDUCTOR MEMORY DEVICE Yoshihir Takemae, Yokohama, Japan assigned to Fujitsu Limited A dynamic semiconductor memory device incorporating memory cells of a one-transistor and one-capacitor type is provided with increased charge storage and thus improved read operation. In this device, each of the memory cells is connected to one word line, to one bit line and to one power supply line. The potential of the power supply line is toggled low then high so as to store more charges in the capacitor of a memory cell.
4409606 HIGH BREAKDOWN VOLTAGE SEMICONDUCTOR DEVICE Kornelis Wagenaar, Hendrik De Graaff, Johannes A Appels, Eindhoven, Netherlands assigned to U S Philips Corporation A semiconductor device having a semiconductor layer 3 of a first conductivity type which is situated on a substrate region 4 of the second opposite type. Present within an island-shaped
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region 3A of the layer 3 are a surface-adjoining active zone 8 of the second conductivity type, for example the base zone of a bipolar transistor or the channel region of a field effect transistor, and a juxtaposed highly doped contact zone of the first conductivity type. The thickness and the doping concentration of the layer 3 are so small that the layer is depleted up to the surface 2 at a reverse voltage across the p-n junction 5 of the layer 3 and the substrate region 4 which is lower than the breakdown voltage. According to the invention, a highly doped buried layer 8 is present between the layer 3 and the substrate region 4 and extends at least below at least a portion of the active zone 8, the shortest distance between the edge of the buried layer 11 and the edge of the contact zones 9 being at least equal to See Patent for Tabular Presentation PS where VB is the breakdown voltage of the p-n junction 5, and Ec is the critical field strength above which avalanche multiplication occurs. As a result of this the effect of lateral current concentrations (Kirk effect) is avoided, while a high breakdown voltage is maintained.
4408387 METHOD FOR PRODUCING A BIPOLAR TRANSISTOR UTILIZING AN OXIDIZED SEMICONDUCTOR MASKING LAYER IN CONJUNCTION WITH AN ANTI-OXIDATION MASK Tadashi Kiriseko, Kanagawa, Japan assigned to Fujitsu Limited A method for producing a bipolar transistor which has no emitter-base short and which attains a high density of integration. The method comprises the steps of forming a polycrystalline silicon layer on an anti-oxidation masking layer formed on a base region, selectively etching the polycrystalline silicon layer to form an opening, introducing impurities into the base region to form an emitter region, converting the polycrystalline silicon layer into an oxide layer whereby the size of the opening is reduced, selectively etching the anti-oxidation masking layer to form an emitter electrode opening, and forming electrodes.
191
4409674 SEMICONDUCTOR MEMORY 3
Yukio Takahashi, Sakata, Japan assigned to Fujitsu Limited In a semiconductor memory which is provided with a memory cell array, word lines and bit lines for selecting a desired one of memory cells of the memory cell array and a detector circuit for detecting a read current of the selected memory cell, the detector circuit is composed of a pair of transistors having their bases cross-connected so that a hysteresis characteristic is provided by flowing a current in the transistors, and the current is controlled by a hysteresis control circuit to flow only when all word line potentials monitored by the hysteresis control circuit have become lower than a predetermined value, whereby to remove the influence of a noise in the detection of read information of the selected memory cell.
4409672 DYNAMIC SEMICONDUCTOR MEMORY DEVICE Yoshihir Takemae, Yokohama, Japan assigned to Fujitsu Limited A dynamic semiconductor memory device incorporating memory cells of a one-transistor and one-capacitor type is provided with increased charge storage and thus improved read operation. In this device, each of the memory cells is connected to one word line, to one bit line and to one power supply line. The potential of the power supply line is toggled low then high so as to store more charges in the capacitor of a memory cell.
4409606 HIGH BREAKDOWN VOLTAGE SEMICONDUCTOR DEVICE Kornelis Wagenaar, Hendrik De Graaff, Johannes A Appels, Eindhoven, Netherlands assigned to U S Philips Corporation A semiconductor device having a semiconductor layer 3 of a first conductivity type which is situated on a substrate region 4 of the second opposite type. Present within an island-shaped
7
li
---L~.,
4'
region 3A of the layer 3 are a surface-adjoining active zone 8 of the second conductivity type, for example the base zone of a bipolar transistor or the channel region of a field effect transistor, and a juxtaposed highly doped contact zone of the first conductivity type. The thickness and the doping concentration of the layer 3 are so small that the layer is depleted up to the surface 2 at a reverse voltage across the p-n junction 5 of the layer 3 and the substrate region 4 which is lower than the breakdown voltage. According to the invention, a highly doped buried layer 8 is present between the layer 3 and the substrate region 4 and extends at least below at least a portion of the active zone 8, the shortest distance between the edge of the buried layer 11 and the edge of the contact zones 9 being at least equal to See Patent for Tabular Presentation PS where VB is the breakdown voltage of the p-n junction 5, and Ec is the critical field strength above which avalanche multiplication occurs. As a result of this the effect of lateral current concentrations (Kirk effect) is avoided, while a high breakdown voltage is maintained.
4408387 METHOD FOR PRODUCING A BIPOLAR TRANSISTOR UTILIZING AN OXIDIZED SEMICONDUCTOR MASKING LAYER IN CONJUNCTION WITH AN ANTI-OXIDATION MASK Tadashi Kiriseko, Kanagawa, Japan assigned to Fujitsu Limited A method for producing a bipolar transistor which has no emitter-base short and which attains a high density of integration. The method comprises the steps of forming a polycrystalline silicon layer on an anti-oxidation masking layer formed on a base region, selectively etching the polycrystalline silicon layer to form an opening, introducing impurities into the base region to form an emitter region, converting the polycrystalline silicon layer into an oxide layer whereby the size of the opening is reduced, selectively etching the anti-oxidation masking layer to form an emitter electrode opening, and forming electrodes.