Semiconductor device simulation

Semiconductor device simulation

Electrical and electronic engineering Agnew, D. Ha/j, I. N., Roulston, D. J. and 79.5 Bryant, P. R. 79.0 Efficient use of the Hessian matrix for c...

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Electrical and electronic engineering Agnew, D.

Ha/j, I. N., Roulston, D. J. and

79.5

Bryant, P. R. 79.0

Efficient use of the Hessian matrix for circuit optimization'. Proc. IEEE ISCAS (1975), pp 3 2 4 - 3 2 7 Recent work on circuit optimization has shown that, in some cases, explicit calculation of the Hessian matrix is not difficult, and the advantages are worthwhile. It is now shown that the minimum work for the Hessian is about three times the work required for the gradient. To save computation, techniques are proposed which increase the benefit obtained from each Hessian eval uation. An example is included.

Blattner, D.J.

79,1 'Choosing the right programs for computeraided design'. Electron. (29 April 1976), pp 102-105 This paper reports the results of a recent study of 16 major CAD programs in the field of circuit design with a view towards comparing their capabilities, machine suitability, speed, accuracy and flexibility.

Cutteridge, O. P. D. and

79.2 Krzeczkowski, A. J. 'Improved methods of synthesizing linear networks by coefficient matching'. IEEE Trans. CAS-22, No 6, (June 1975), pp 486 489 Attention is drawn to a large number of possible variants in the detailed application of the coefficient matching technique to the computer synthesis of lumped linear networks. Tables of run-times obtained with a numerical example provide some indication of the relative computational efficiency of the methods instanced. Simple closed-form expressions for the optimum value of the muttiplicative constant are derived for three variants. An illustrative table demonstrates that their use greatly improves the rate and range of the convergence of the method.

'A three-terminal piece-wise linear modelling approach to DC analysis of transistor circuits'. Int. ]. Circ. TheorAppl., Vol 2, No 2 , ( l u n e 1974),pp 133 147 One of the goats in computer simulation of integrated circuits is to have a program 'package' for which the input consists of chip fabrication data and the output displays the complete circuit response. In this paper, a simulation method is described which generates DC responses of transistor circuits directly from physical parameter data. / h e method is based on two-dimensional piecewise linear approach to the DC modelling o f bipolar transistors.

Hosseini, N. M., Shurmer, V. H. and Soares, R. A.

79.6

'OPTIMAL - a program for optimizing microstrip networks'. Electron. Left., Vol 12, No 8, (April 1976), pp 1 9 0 - 1 9 2 An optimization program OPTIMAL is described which includes algorithms for dispersion and loss in microstrip. The optimization routine combines pseudo-random and conjugate gradient pattern-search techniques to improve the chances of finding a global-minimum solution to multimodal problems. llmonen, M. 79.7 'Computing symbolic network functions by the derivative method'. Proc. IEEE ISCAS 1976, pp 328-331 This paper describes a numerical nontopological method to compute symbolic network functions of linear, active, timeinvariant networks, in terms of the frequency and/or network parameters. The method, in principle is related to the Padeapproximation. However, required network functions can be directly presented in the rational form, when the derivatives are known. Lee, C. M., Lomax, R. J. and

79.8

Haddad, Ca I. Essl, D. V., Mitterer, R. W. and

79.3

Rehn, B. F. 'An optimization program for switching circuits'. 1974 European Conference on Circuit Theory and Design, lEE Pub No l16, pp 68 73 This paper describes a computer program OPTISEM. This program optimizes the switching time or a voltage level of integrated bipolar and MOS switching circuits taking into account such criteria as power corn sumption, transistor area, interdependencies of circuit elements and monitored node voltage levels.

Hachtel, G. D., Lightner, M. R. and

79.4 Kelly, H. J. 'Application of the optimization program AOP to the design of memory circuits'. IEEE Trans. CAS-22, No 6, (June 1975), pp 496 -503 The memory cycle time of an IGEET readonly memory cell is designed using AOP, a program for automated and interactive optimization of electrical networks. It is shown how AOP allows user to specify multiple performance objectives and to request analysis, and/or adjoint sensitivity computation, and/or optimization for networks described in the ASTAP input language. A procedure is given for applying optimization to switching circuit design.

70

'Semiconductor device simulation'. IEEE Trans. MTT-22, No 3, (March 1974), pp 160 -177 ] w o of the numerical methods most widely used in solving the set of partial differential transport equations for holes, electrons and electric field in semiconductor devices and the various numerical instability phenomena which can be encountered are described in detail. Also presented a r e a p proaches using these methods to calculate DC static solutions and small-signal solutions, and to simulate devices in voltagedriven, current-driven, and circuit-loaded operations. Sample results are given for each mode of operation for the case of Si avalanche-diode oscillators. The numerical methods and approaches are those developed at the laboratories and sufficient details are given to permit the development of similar FORTRAN codes for others.

Massara, R. E. and Fidler, J.K.

79.9 'Computer optimization of frequency selective networks'. 1974 European Conference on Circuit Theory and Design, lEE Pub No 116, pp 133 140 This paper describes a novel approach to the CAD of electrical networks based on the method of matching coefficients of network polynomial. Its relative advantages and disadvantages are discussed. A

two-stage algorithm is described which provides rapid optimization of active and passive networks. Rabbat, N.B. 80.0 'Efficient computation of the transient response of lumped-distributed linear active networks'. IEEE Trans. CAS-22, No 8, (Aug 1975), pp 666--670 An efficient approach to the computeraided transient analysis of lumped-distributed linear networks is presented. The method is based on obtaining the transfer function of the network by symbolic techniques and the transient response is computed using fast Fourier transform, the shifting parameter a, and the new twodimensional weighting factor- w n and cr. This algorithm saves a large amount of computing time and memory when compared with existing techniques.

Rowlands, M.O. 80.1 'Improved method for evaluating the static parameters of the Ebers-Moll transistor model'. Electron. Lett., Vol 12, No 1, (Jan 1976),pp 34-~36 Existing programs for evaluating the static parameters of the Ebers-Moll transistor model provide either high accuracy or economical operation. The method presented in this paper as a computer program combines both high accuracy and economy. Examples of the improved agreement between experimental data and theoretical estimates are given. Silvester, P. and Csendes, Z . J . 80.2 'Numerical modelling of passive microwave devices'. IEEETrans. MTT-22, No 3, (March 1974), pp 190-201 Passive linear bilateral microwave devices principally include guided wave transmission structures, their junctions, and interconnections, as well as such complex devices as resonant cavities and planar networks. The computational methods for analyzing the behaviour of this class of structures and for characterizing them for purposes of network design are briefly reviewed.

Spence, R. and Apperley, M.

80,3 'The interactive-graphic man-computer dialogue in computer-aided circuit design'. Proc IEEE ISCAS 1976, pp 134-137 The crucial role played by the man-computer dialogue in computer-aided circuit design, and particularly within an interactive graphic medium, is demonstrated by reference to a working circuit design facility implemented on a minicomputer. The detailed nature of this facility and the tech niques illustrated are related to the c.ircuit design process and the behavioural characteristics of the human designer. Zibert, K. 80.4 'Computer-aided planar circuit layout'. 1974 European Conference on Circuit Theory and Design, lEE Pub. No 116, pp 4 9 - 5 5 A contribution to the design of the physical layout of circuits in a single layer. It is assumed that the topological layout on the plane represented by a planar bipartite graph has already been determined. The solution of the placement problem requires to preserve the local relations between the components in order to wire the components in their local environments. By this way the area required for the wiring is minimized.

computer-aided design