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4556840 Method for testing electronic assemblies
New Patents
4553225 M E T H O D OF TESTING IC MEMORIES Yoshikazu Ohe, Kawasaki, Japan assigned to Fujitsu Limited In a method of testing IC memories, at first, predetermined data such as all 0 or all 1 is written into an IC memory at a normal-operation power-supply voltage, and the written data is read out and confirmed. Next, the power-supply voltage is lowered and is then returned to the normal-operation power-supply voltage after a predetermined period of time has passed in order to determine whether the stored data is in agreement with the data as initially written. When the stored data is in agreement with the initially written data, the power-supply voltage is further lowered to repeat the above-mentioned procedure. The above-mentioned procedure is further repeated when the stored data is in agreement with the initially written data and a minimum data-holding limit voltage which is capable of holding the written data is thereby determined.
4553435 ELEVATED TRANSIENT T E M P E R A T U R E LEAK TEST FOR UNSTABLE MICROELECTRONIC PACKAGES Harold Goldfarb, Kenneth L Perkins, Bernard L Weigand assigned to The United States of America as represented by the Secretary of the Air Force A novel method and apparatus for detecting leaks in glass-to-metal seals of microelectronic devices and the like are described which comprise a double-gasketed vacuum station including a base plate having a central hole and a first gasket for exposing one side of the seals to a leak detector; a vacuum fixture surrounding the device provides a marginal region therearound which can be evacuated to prevent helium from permeating the first gasket; the vacuum fixture includes a central opening to expose the other side of the seals to a helium-containing atmosphere within a shroud enclosing the device and vacuum fixture; a second gasket provides a seal between the vacuum fixture and device periphery at the central opening in the fixture. For leak tests under controlled time/temperature conditions, an adjacent infrared lamp is used to radiantly heat the package containing the glass-
801
to-metal seals, and a mask is included to avoid direct radiant heating of the gaskets and glassto-metal seals.
4554506 M O D U L A R TEST PROBE Louis H Faure, Dana R Townsend, Thomas J Walsh assigned to International Business Machines Corporation A test probe employing a buckling beam array for testing integrated circuits. A pair of identicai sets of guides are positioned on either side of a centerpost to align the buckling beams. In one embodiment the holes in one set of guides is offset by a key to induce prebow in the beams. In another embodiment prebow is induced by a floating asymmetric separator positioned on the centerpost between the guide sets. When a force is applied to the probe, the beams deflect in the direction but to different extents so that a uniform force is applied to the surface of the IC irrespective of variations in height.
4556840 M E T H O D FOR TESTING ELECTRONIC A S S E M B L I E S Robert J Russell assigned to Honeywell Information Systems Inc A method for achieving printed circuit (PC) board-level testability through electronic component-level design using available technological methods to effect a state of transparency during test, allowing precise verification and diagnosis on a component-by-component basis. Applicable to a greater variety of electronic products than other test methods, and not appreciably constraining functional design, this approach inherently avoids obstacles which prevent other techniques from fulfilling their objectives. This method is applicable to analog or digital electronic components and circuits and results in the ability to largely combine component level and board level test development efforts, a reduction in the need for exhaustive component testing prior to board assembly, the applicability of a single tester configuration to a number of product types, the ability to substitute a verified component for a suspect one without removal, and the ability to detect marginally operative components which have not yet affected board functionality. This method allows the production and stocking of a single set of
802
New Patents
compatible electronic components to be used in place of existing electronic components as well as allowing existing electronic designs to be converted to this test method by substituting compatible electronic components for all existing electronic components.
4556975 PROGRAMMABLE REDUNDANCY CIRCUII Teresa B Smith, Philip C Smith assigned to Westinghouse Electric Corp
A memory redundancy circuit is described incorporating a sequential row or column counter associated with a plurality of programmable row or column decoders. The sequential row counter includes a sequence circuit for each programmable row decoder. The sequence circuit and programmable row decoder incorporate fixed and variable threshold transistors such as metal nitride oxide semiconductor (MNOS) transistors. The threshold of the variable threshold transistors are switched in response to address signals and control signals to permit redundancy. A disable circuit is also described to permit removal of the redundancy circuits to permit retest of the other circuits.
For information about P A T S E A R C H ~
Pergamon InfoLine Inc. 1340 Old Chain Bridge Road McLean, Virginia 22101 USA Telephone (703) 442-0900 Telex: 90-1811
Pergamon InfoLine Limited 12 Vandy Street London EC2A 2DE England Telephone (01) 377-4650 Telex: 8814614
Pergamon Press Canada Ltd 150 Consumers Road, Suite 104 Willowdale, Ontario Canada M2J 1P9 Telephone (416) 497-8
4553225 M E T H O D OF TESTING IC MEMORIES Yoshikazu Ohe, Kawasaki, Japan assigned to Fujitsu Limited In a method of testing IC memories, at first, predetermined data such as all 0 or all 1 is written into an IC memory at a normal-operation power-supply voltage, and the written data is read out and confirmed. Next, the power-supply voltage is lowered and is then returned to the normal-operation power-supply voltage after a predetermined period of time has passed in order to determine whether the stored data is in agreement with the data as initially written. When the stored data is in agreement with the initially written data, the power-supply voltage is further lowered to repeat the above-mentioned procedure. The above-mentioned procedure is further repeated when the stored data is in agreement with the initially written data and a minimum data-holding limit voltage which is capable of holding the written data is thereby determined.
4553435 ELEVATED TRANSIENT T E M P E R A T U R E LEAK TEST FOR UNSTABLE MICROELECTRONIC PACKAGES Harold Goldfarb, Kenneth L Perkins, Bernard L Weigand assigned to The United States of America as represented by the Secretary of the Air Force A novel method and apparatus for detecting leaks in glass-to-metal seals of microelectronic devices and the like are described which comprise a double-gasketed vacuum station including a base plate having a central hole and a first gasket for exposing one side of the seals to a leak detector; a vacuum fixture surrounding the device provides a marginal region therearound which can be evacuated to prevent helium from permeating the first gasket; the vacuum fixture includes a central opening to expose the other side of the seals to a helium-containing atmosphere within a shroud enclosing the device and vacuum fixture; a second gasket provides a seal between the vacuum fixture and device periphery at the central opening in the fixture. For leak tests under controlled time/temperature conditions, an adjacent infrared lamp is used to radiantly heat the package containing the glass-
801
to-metal seals, and a mask is included to avoid direct radiant heating of the gaskets and glassto-metal seals.
4554506 M O D U L A R TEST PROBE Louis H Faure, Dana R Townsend, Thomas J Walsh assigned to International Business Machines Corporation A test probe employing a buckling beam array for testing integrated circuits. A pair of identicai sets of guides are positioned on either side of a centerpost to align the buckling beams. In one embodiment the holes in one set of guides is offset by a key to induce prebow in the beams. In another embodiment prebow is induced by a floating asymmetric separator positioned on the centerpost between the guide sets. When a force is applied to the probe, the beams deflect in the direction but to different extents so that a uniform force is applied to the surface of the IC irrespective of variations in height.
4556840 M E T H O D FOR TESTING ELECTRONIC A S S E M B L I E S Robert J Russell assigned to Honeywell Information Systems Inc A method for achieving printed circuit (PC) board-level testability through electronic component-level design using available technological methods to effect a state of transparency during test, allowing precise verification and diagnosis on a component-by-component basis. Applicable to a greater variety of electronic products than other test methods, and not appreciably constraining functional design, this approach inherently avoids obstacles which prevent other techniques from fulfilling their objectives. This method is applicable to analog or digital electronic components and circuits and results in the ability to largely combine component level and board level test development efforts, a reduction in the need for exhaustive component testing prior to board assembly, the applicability of a single tester configuration to a number of product types, the ability to substitute a verified component for a suspect one without removal, and the ability to detect marginally operative components which have not yet affected board functionality. This method allows the production and stocking of a single set of
802
New Patents
compatible electronic components to be used in place of existing electronic components as well as allowing existing electronic designs to be converted to this test method by substituting compatible electronic components for all existing electronic components.
4556975 PROGRAMMABLE REDUNDANCY CIRCUII Teresa B Smith, Philip C Smith assigned to Westinghouse Electric Corp
A memory redundancy circuit is described incorporating a sequential row or column counter associated with a plurality of programmable row or column decoders. The sequential row counter includes a sequence circuit for each programmable row decoder. The sequence circuit and programmable row decoder incorporate fixed and variable threshold transistors such as metal nitride oxide semiconductor (MNOS) transistors. The threshold of the variable threshold transistors are switched in response to address signals and control signals to permit redundancy. A disable circuit is also described to permit removal of the redundancy circuits to permit retest of the other circuits.
For information about P A T S E A R C H ~
Pergamon InfoLine Inc. 1340 Old Chain Bridge Road McLean, Virginia 22101 USA Telephone (703) 442-0900 Telex: 90-1811
Pergamon InfoLine Limited 12 Vandy Street London EC2A 2DE England Telephone (01) 377-4650 Telex: 8814614
Pergamon Press Canada Ltd 150 Consumers Road, Suite 104 Willowdale, Ontario Canada M2J 1P9 Telephone (416) 497-8