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Testing of properties for soldered leadless chip carrier assemblies
particles that cause PIND test failures; the main source being the gold-tin solder preform used in the sealing process. We have investigated the effect of sealing materials, furnace temperature, furnace ambient, and package orientation on the number of gold-tin solder sphe'res. The best results were obtained with a nonoxidising furnace ambient with the packages placed lid down and angled at 45 degrees during sealing. These improved assembly processes have led to PIND test yeields of better than 90 percent. High speed SOS and GaAs IC testing in the 1980s D. O. WILSON, D. M. TAYLOR and D. H. PHILLIPS Solid-State Technology 95 (June 1981) High speed ( ~ 4 GHz) LSIC Automatic Test Systems (ATE) are required to economically characterise the high speed GaAs and SOS ICs that are currently being developed. Since commercial ATE systems are not available for GHz digital testing at the wafer probe level, 9a unique high speed IC test system to meet their internal G H z LSIC test requirements have been developed. This system consists of a modified Tektronix WF2200 controller based digitiser, de to 18 GHz input signal generation hardware and a 2-4 GHz IC probe station. A general purpose IEEE-488 interface buss is used to form a closed loop consisting of the controller, digitiser, I[O hardware and postulates are proposed describing the propagation of waves of logic states, which serve as a basis for a simulator written in FORTRAN. Temperature accelerated estimation of MNOS memory reliability T. AJIKI, M. SUGIMOTO, H. HIGUCHI and S. K U M A D A IEEE/Proc. IRPS 17 (1981) A MNOS non-volatile memory has many special features and a good marketability 9 In spite of that it is not widely used due to its undeveloped reliability. Life test experiments were done under various application conditions to obtain an exact reliability estimation for a MNOS memory. Results of these tests imply the application of erase/write cycles prior to retention life test experiments, which is preferable for a proper estimation of life time at field operation conditions. A screening procedure at high temperature for a short time becomes possible by applying a proper acceleration factor.
Testing of properties for soldered leadless chip carrier assemblies T H O M A S M. SHELTON
IEEE Trans. Components Hybrids Mfg Technol CHMT.4 (2), 200 (June 1981) The use of leadless chip carders in soldered assemblies represents a relatively new device packaging/interconnection technology. There is little published material treating any of the physical properties of the solder attachment in a quantitative fashion. The application of leadless hermetic chip carriers to high reliability microelectronics prompted a joint perliminary investigation by RCA and Sandia Laboratories to quantitatively characterise the solder assembly interface. It was determined that the mechanical and electrical integrity of the soldered connections could best be assured by
measuring the yield strength and electrical resistance versus different fabrication conditions and environmental stresses. Sandia devised a program for parallel sample preparation and testing by both RCA and Sandia Laboratories. This program also included tests to evaluate the thick film material system which will not be reported here. The preparation of samples and the design of methods and fixtures for testing the yield strength of the soldered connections under lap shear is described. The measurements reported include values corresponding to controlled variation in fabrication and processing parameters and the different environmental stress conditions. While the sample sizes are quite modest, the methods and fixturing are believed to be of general interest, and the various values found for the yield strength and resistance provide a good indication of the magnitude of the influences of the various processing and environmental stress conditions on the integrity of soldered chip carrier assemblies. The measurement values reported were performed by RCA under contract to Sandia Laboratories and the values appear to correlate with those obtained at Sandia for the same sets of conditions. Electric measurement and modelling of the emitter base junction behavinur of VLSI silicon transistor D. SEBILLE, O. BONNAUD andJ. P. CHANTE Solid-State Electronics 24, 11, 1053 (1981) A knowledge of the gain of the emitter base junction centre is of great interest to evaluate several phenomena which occur in VLSI technology. These effects are mainly: the edge effects of the emitter base junction; the heavily doped emitter effects (bandgap narrowing). We develop in this paper a method to measure the internal gain of the VLSI bipolar transistors using a weak avalanche multiplication in the collector. To verify our results we proposed a model which is convenient to use with our devices and consistent by comparison with some previous works. For the tested devices the ratio of the overall gain with the internal gain is about 0.5. Furthermore, the model allows a knowledge of the average intrinsic concentration of the degenerate emitter.
Failure modes in GaAs power FETs: Ohmic contact electromigration and formation of refractory oxides A. CHRISTOU, E. COHEN and A. C. MACPHERSON IEEE/Proc. IRPS 82 (1981) Failure modes have been identified for two commercially available microwave power GaAs bETs constructed with aluminium gates. MTTF data for AI gate power FETs and AI gate in combination with refractory link power FETs indicates the presence of a fadure mode w~th a well defined activation energy. The first set of power FETs (Set A) use AuGe/Au source and drain contacts and A! gates. The second set use an AI-TiPt gate with AuGeTiPt-Au source, drain contacts. The devices from set A were tested at 200~ under rf drive. An NYI'FF of 2200 hr was achieved and source-drain electromigration was identified as the primary failure mode. This newly identified failure mode for ohmic contacts has been confirmed by Auger electron spectroscopy, a n d the SEM. Gallium has been shown to outdiffuse in the contact system with subsequent Ga whisker growth and gate void formation caused by the AuA! couple at the gate. Sputter AES profiles indicated that interdiffusion in the source and drain contacts extends into the active channel region under the bias-stress tests. 9
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Testing of properties for soldered leadless chip carrier assemblies T H O M A S M. SHELTON
IEEE Trans. Components Hybrids Mfg Technol CHMT.4 (2), 200 (June 1981) The use of leadless chip carders in soldered assemblies represents a relatively new device packaging/interconnection technology. There is little published material treating any of the physical properties of the solder attachment in a quantitative fashion. The application of leadless hermetic chip carriers to high reliability microelectronics prompted a joint perliminary investigation by RCA and Sandia Laboratories to quantitatively characterise the solder assembly interface. It was determined that the mechanical and electrical integrity of the soldered connections could best be assured by
measuring the yield strength and electrical resistance versus different fabrication conditions and environmental stresses. Sandia devised a program for parallel sample preparation and testing by both RCA and Sandia Laboratories. This program also included tests to evaluate the thick film material system which will not be reported here. The preparation of samples and the design of methods and fixtures for testing the yield strength of the soldered connections under lap shear is described. The measurements reported include values corresponding to controlled variation in fabrication and processing parameters and the different environmental stress conditions. While the sample sizes are quite modest, the methods and fixturing are believed to be of general interest, and the various values found for the yield strength and resistance provide a good indication of the magnitude of the influences of the various processing and environmental stress conditions on the integrity of soldered chip carrier assemblies. The measurement values reported were performed by RCA under contract to Sandia Laboratories and the values appear to correlate with those obtained at Sandia for the same sets of conditions. Electric measurement and modelling of the emitter base junction behavinur of VLSI silicon transistor D. SEBILLE, O. BONNAUD andJ. P. CHANTE Solid-State Electronics 24, 11, 1053 (1981) A knowledge of the gain of the emitter base junction centre is of great interest to evaluate several phenomena which occur in VLSI technology. These effects are mainly: the edge effects of the emitter base junction; the heavily doped emitter effects (bandgap narrowing). We develop in this paper a method to measure the internal gain of the VLSI bipolar transistors using a weak avalanche multiplication in the collector. To verify our results we proposed a model which is convenient to use with our devices and consistent by comparison with some previous works. For the tested devices the ratio of the overall gain with the internal gain is about 0.5. Furthermore, the model allows a knowledge of the average intrinsic concentration of the degenerate emitter.
Failure modes in GaAs power FETs: Ohmic contact electromigration and formation of refractory oxides A. CHRISTOU, E. COHEN and A. C. MACPHERSON IEEE/Proc. IRPS 82 (1981) Failure modes have been identified for two commercially available microwave power GaAs bETs constructed with aluminium gates. MTTF data for AI gate power FETs and AI gate in combination with refractory link power FETs indicates the presence of a fadure mode w~th a well defined activation energy. The first set of power FETs (Set A) use AuGe/Au source and drain contacts and A! gates. The second set use an AI-TiPt gate with AuGeTiPt-Au source, drain contacts. The devices from set A were tested at 200~ under rf drive. An NYI'FF of 2200 hr was achieved and source-drain electromigration was identified as the primary failure mode. This newly identified failure mode for ohmic contacts has been confirmed by Auger electron spectroscopy, a n d the SEM. Gallium has been shown to outdiffuse in the contact system with subsequent Ga whisker growth and gate void formation caused by the AuA! couple at the gate. Sputter AES profiles indicated that interdiffusion in the source and drain contacts extends into the active channel region under the bias-stress tests. 9
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