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4961812 Etch-back apparatus for integrated circuit failure analysis
New Patents
4961050 TEST FIXTURE FOR MICROSTRIP ASSEMBLIES Warren K Harwood, Keith E Jones, Daniel DeLessert assigned to Cascade Microtech Inc A test fixture for testing microstrip assemblies and similar electronic circuit components and assemblies under application of high-frequency signals introduced through launchers whose positions are adjustable in the test fixture to accommodate circuit assemblies of different sizes and different geometry. An easily operated rapid connector positioning mechanism moves connectors which complete electrical connection between outer conductors of the launchers and a ground plane conductor of a microstrip assembly. The connectors also lift the microstrip assembly and support it while electrical connection is completed, without the need for a carrier beneath the test assembly. A lid is moved in coordination with operation of the connector positioning mechanism to provide electrical contact to a third point on the upper face of a circuit assembly to be tested.
4961052 PROBING PLATE FOR WAFER TESTING Tetsuo Tada, Ryoich Takagi, Masanobu Kohara, Hyogo, Japan assigned to Mitsubishi Denki Kabushiki Kaisha A probing plate for wafer testing is provided with a plurality of probes arranged so as to correspond to a plurality of bonding pads of semiconductor devices fabricated on a semiconductor wafer. The probing plate has a base plate formed ofan insulating material, such as a photosensitive glass, and has contact fingers each having a raised portion in the free end thereof, contact conductors respectively formed on the surfaces of the raised portions of the contact fingers so as to be brought into contact with the corresponding bonding pads, and wiring conductors formed in a predetermined pattern on the surface of the base plate so as to extend respectively from the contact conductors. The contact conductors and the wiring conductors are formed simultaneously by a photolithographic process. The contact fingers and the raised portions thereof are also formed by sub-
1059
jecting the base plate to a photolithographic process. Forming the contact conductors over the surfaces of the raised portions of the contact fingers prevents accidental contact of the contact conductors with the bonding pads of semiconductor devices other than the objective semiconductor devices.
4961053 CIRCUIT ARRANGEMENT FOR TESTING INTEGRATED CIRCUIT COMPONENTS Heinz Krug, NL 6063 Vlodrop, Netherlands A circuit arrangement is provided for testing circuit components which are formed as integrated circuits on a common base plate and operable at the base plate by way of common feed lines and input lines. In the circuit arrangement, a testing circuit and switching stages are formed on the same base plate as integrated circuits, the switching stages are controllable by the testing circuit and inserted in connecting lines for connecting the testing circuit to the circuit components, and the testing circuit is equipped with an output circuit for delivering test results. The testing circuit is arranged for testing of the components without any other connections as the power supply connections. This self-testing is achieved by means of a central unit of the testing circuit by comparing of actual and desired values, distinguishing between faulty and faultless components and deciding of the respective functionality of the components in time sequence.
4961812 ETCH-BACK APPARATUS FOR INTEGRATED CIRCUIT FAILURE ANALYSIS William Baerg, Valluri R Rao assigned to Intel Corporation An apparatus and a method to inhibit sputtering of undesirable material onto a dielectric layer of an integrated circuit being etched. After exposing the integrated circuit within its package,
1060
New Patents
the leads of the integrated circuit are electrically coupled together by a metallic foil. The metallic foil is wrapped about the package to also provide thermal coupling, however, the integrated circuit is left exposed. Then, the integrated circuit is placed onto an etch-resilient plate disposed atop a cathode electrode. An opening in the plate allows direct placement of the integrated circuit onto the cathode. An etch-resilient cover is placed above the plate opening and the integrated circuit, but the cover has an opening to expose the integrated circuit. During etching, the cover inhibits sputtering from the leads, preform and bond wires.
4962461 METHOD FOR THE REPRODUCABLE FORMATION OF MATERIAL LAYERS AND]OR THE TREATMENT OF SEMICONDUCTOR MATERIALS LAYERS Meinhard Meyer, Oswald Stormer, Munich, Federal Republic Of Germany assigned to Messerschmitt-Bolkow-Blohm GmbH A method and apparatus for process control in both the production of uniform material layers using vapor deposition, sputtering, chemical deposition, etc. and the treating of material layers. In particular, the process and apparatus are particularly useful in semiconductor fabrication where ion implantation or diffusion is used. A brief test signal of preset shape, frequency spectrum, or frequency sequence is applied at given time intervals to the material layer whose production characteristics need to be monitored. The measuring signal is applied to a digital evaluation circuit in a process control computer. The signal has various components whose time constants and/or conductivities are different from one another and which together are characteristics of the current flowing through the layer being monitored. In particular, the current flowing over the surface layer i l, the current flowing through particle houndary areas i3, and the current through homogeneous material ranges i2 can be distinguished from one another. The results from the measuring signal can be compared to stored reference values for the layer. Discrepancies between the actual and desired values are measured and used to adjust the process in a known fashion.
4963824 DIAGNOSTICS OF A BOARD CONTAINING A PLURALITY OF HYBRID ELECTRONIC COMPONENTS Edward P Hsieh, Maurice T McMahon, Henri D Schnurmann assigned to International Business Machines Corporation A method and circuitry for testing in situ the components mounted on a circuit board. First, a component is removed from the board. A testing circuit is then installed in place of the removed component. The testing circuit allows test patterns to be applied to a selected component on the board from the board I/O pins. The selected component responses are collected by the testing circuit and applied to the board output pins. In this manner, individual components on the board can be tested in situ from pins on the board.
4963825 METHOD OF SCREENING EPROM-RELATED DEVICES FOR ENDURANCE FAILURE Neal R Mielke assigned to Intel Corporation A method for screening EPROM-related integrated circuits for endurance failure is described. The screening method is based on a measurement of the number and distribution of cells within the EPROM-related device which program and/or erase significantly further and faster than normal cells. The erase speed of the floating gate cells are first measured to obtain an erase distribution for the IC in which the percentage of bits erased is plotted as a function of the applied gate threshold voltage. The number of bits which are located in the erase tail region of the distribution is then identified. If this number exceeds a certain percentage of the total bits in the array the IC is classified as one which is likely to suffer early endurance failure. Compared to traditional cycling screens, the method of the present invention identifies unreliable material non-destructively and does not require extra floating-gate cells or error-correction logic overhead.
4961050 TEST FIXTURE FOR MICROSTRIP ASSEMBLIES Warren K Harwood, Keith E Jones, Daniel DeLessert assigned to Cascade Microtech Inc A test fixture for testing microstrip assemblies and similar electronic circuit components and assemblies under application of high-frequency signals introduced through launchers whose positions are adjustable in the test fixture to accommodate circuit assemblies of different sizes and different geometry. An easily operated rapid connector positioning mechanism moves connectors which complete electrical connection between outer conductors of the launchers and a ground plane conductor of a microstrip assembly. The connectors also lift the microstrip assembly and support it while electrical connection is completed, without the need for a carrier beneath the test assembly. A lid is moved in coordination with operation of the connector positioning mechanism to provide electrical contact to a third point on the upper face of a circuit assembly to be tested.
4961052 PROBING PLATE FOR WAFER TESTING Tetsuo Tada, Ryoich Takagi, Masanobu Kohara, Hyogo, Japan assigned to Mitsubishi Denki Kabushiki Kaisha A probing plate for wafer testing is provided with a plurality of probes arranged so as to correspond to a plurality of bonding pads of semiconductor devices fabricated on a semiconductor wafer. The probing plate has a base plate formed ofan insulating material, such as a photosensitive glass, and has contact fingers each having a raised portion in the free end thereof, contact conductors respectively formed on the surfaces of the raised portions of the contact fingers so as to be brought into contact with the corresponding bonding pads, and wiring conductors formed in a predetermined pattern on the surface of the base plate so as to extend respectively from the contact conductors. The contact conductors and the wiring conductors are formed simultaneously by a photolithographic process. The contact fingers and the raised portions thereof are also formed by sub-
1059
jecting the base plate to a photolithographic process. Forming the contact conductors over the surfaces of the raised portions of the contact fingers prevents accidental contact of the contact conductors with the bonding pads of semiconductor devices other than the objective semiconductor devices.
4961053 CIRCUIT ARRANGEMENT FOR TESTING INTEGRATED CIRCUIT COMPONENTS Heinz Krug, NL 6063 Vlodrop, Netherlands A circuit arrangement is provided for testing circuit components which are formed as integrated circuits on a common base plate and operable at the base plate by way of common feed lines and input lines. In the circuit arrangement, a testing circuit and switching stages are formed on the same base plate as integrated circuits, the switching stages are controllable by the testing circuit and inserted in connecting lines for connecting the testing circuit to the circuit components, and the testing circuit is equipped with an output circuit for delivering test results. The testing circuit is arranged for testing of the components without any other connections as the power supply connections. This self-testing is achieved by means of a central unit of the testing circuit by comparing of actual and desired values, distinguishing between faulty and faultless components and deciding of the respective functionality of the components in time sequence.
4961812 ETCH-BACK APPARATUS FOR INTEGRATED CIRCUIT FAILURE ANALYSIS William Baerg, Valluri R Rao assigned to Intel Corporation An apparatus and a method to inhibit sputtering of undesirable material onto a dielectric layer of an integrated circuit being etched. After exposing the integrated circuit within its package,
1060
New Patents
the leads of the integrated circuit are electrically coupled together by a metallic foil. The metallic foil is wrapped about the package to also provide thermal coupling, however, the integrated circuit is left exposed. Then, the integrated circuit is placed onto an etch-resilient plate disposed atop a cathode electrode. An opening in the plate allows direct placement of the integrated circuit onto the cathode. An etch-resilient cover is placed above the plate opening and the integrated circuit, but the cover has an opening to expose the integrated circuit. During etching, the cover inhibits sputtering from the leads, preform and bond wires.
4962461 METHOD FOR THE REPRODUCABLE FORMATION OF MATERIAL LAYERS AND]OR THE TREATMENT OF SEMICONDUCTOR MATERIALS LAYERS Meinhard Meyer, Oswald Stormer, Munich, Federal Republic Of Germany assigned to Messerschmitt-Bolkow-Blohm GmbH A method and apparatus for process control in both the production of uniform material layers using vapor deposition, sputtering, chemical deposition, etc. and the treating of material layers. In particular, the process and apparatus are particularly useful in semiconductor fabrication where ion implantation or diffusion is used. A brief test signal of preset shape, frequency spectrum, or frequency sequence is applied at given time intervals to the material layer whose production characteristics need to be monitored. The measuring signal is applied to a digital evaluation circuit in a process control computer. The signal has various components whose time constants and/or conductivities are different from one another and which together are characteristics of the current flowing through the layer being monitored. In particular, the current flowing over the surface layer i l, the current flowing through particle houndary areas i3, and the current through homogeneous material ranges i2 can be distinguished from one another. The results from the measuring signal can be compared to stored reference values for the layer. Discrepancies between the actual and desired values are measured and used to adjust the process in a known fashion.
4963824 DIAGNOSTICS OF A BOARD CONTAINING A PLURALITY OF HYBRID ELECTRONIC COMPONENTS Edward P Hsieh, Maurice T McMahon, Henri D Schnurmann assigned to International Business Machines Corporation A method and circuitry for testing in situ the components mounted on a circuit board. First, a component is removed from the board. A testing circuit is then installed in place of the removed component. The testing circuit allows test patterns to be applied to a selected component on the board from the board I/O pins. The selected component responses are collected by the testing circuit and applied to the board output pins. In this manner, individual components on the board can be tested in situ from pins on the board.
4963825 METHOD OF SCREENING EPROM-RELATED DEVICES FOR ENDURANCE FAILURE Neal R Mielke assigned to Intel Corporation A method for screening EPROM-related integrated circuits for endurance failure is described. The screening method is based on a measurement of the number and distribution of cells within the EPROM-related device which program and/or erase significantly further and faster than normal cells. The erase speed of the floating gate cells are first measured to obtain an erase distribution for the IC in which the percentage of bits erased is plotted as a function of the applied gate threshold voltage. The number of bits which are located in the erase tail region of the distribution is then identified. If this number exceeds a certain percentage of the total bits in the array the IC is classified as one which is likely to suffer early endurance failure. Compared to traditional cycling screens, the method of the present invention identifies unreliable material non-destructively and does not require extra floating-gate cells or error-correction logic overhead.