- Email: [email protected]
7th European workshop on design for testability
Events
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June 17-21, 1990 IJCNN'90. San Diego, CA, USA. Contact: Nomi Feldman, IJCNN'90 Conference Coordinator, 5665 Oberlin Drive, San Diego, CA 92121, USA, Tel. 619-453 6222, Fax. 619-453 7930. June 18-21, 1990 7th European Workshop on Design for Testability. Segovia, Spain. Contact: 7th European DFT Workshop, c / o Chelo Rodriguez, Telefonica I + D, Emilio Vargas 6-1a Plta., 28043 Madrid, Spain, Tel. + 34-1-337 4311, Fax. + 34-1-337 4212. June 24-30, 1990 IFIP WG10.5 Summer School on Formal Methods for VLSI Design. Lyngby, Denmark. Contact: Jorgen Staunstrup, Dept. of Computer Science, Building 344, Technical University of Denmark, DK-2800 Lyngby, Denmark, Tel. 45-4288 1566. June 24-28, 1990 27th ACM/IEEE Design Automation Conference. Orlando, FL, USA. Contact: MP Associates Inc., Alfred E. Dunlop, 7490 Clubhouse Road, Suite 102, Boulder, CO 80301, USA, Tel. 303-530 4333. June 25-26, 1990 ITG/IEEE Workshop on Microelectronics for Neural Networks. Dortmund, West Germany. Contact: Dr. Ulrich Ramacher, Siemens AG, ZFE ME FKS 32, Otto-Hahn-Ring 6, D-8000 Munich-83, West Germany. June 26-28, 1990 20th Annual International Symposium on Fault-Tolerant Computing. Newcastleupon-Tyne, UK. Contact: Prof. Bev. Littlewood, CSR, City University, Northampton Square, London EC1V 0HB, UK, Tel. +44-1-253 4399 ext. 4160, Fax. + 44-1-253 3861.
Calls for Papers 7th European Workshop on Design for Testability June 18-21, 1990 Segovia, Spain The European Workshop on Design for Testability aims to provide a biennual forum on the latest problems and solutions in the area of Design for Testability. Attendance is by invitation only and restricted to 70 persons. There will be four
220
Events
paper sessions, two panel sessions and four poster sessions. Possible topic areas to be addressed in papers and posters are: Emerging test technology Test of mixed analog/digital cirSilicon compilation and D F T cuitry Failure analysis Partitioning Self-test implementations High speed testing and interconTest generation & fault-tolerant circuity nect Testing of high reliable and faultBoundary-Scan tolerant circuitry Delay testing Further information can be obtained from: 7th European D F T Workshop c / o Chelo Rodriguez, Telefonica I + D Emilio Vargas 6-1 a Plta. 28043 Madrid, Spain Tel. + 34-1-337 4311 Fax. + 34-1-337 4212
ITG/IEEE Workshop on Microelectronics for Neural Networks June 25-26, 1990 Dortmund, West Germany This workshop is dedicated to hardware for neural networks and discussion of implementation constraints introduced by application, technology and sytem environment. The workshop will include an interdisciplinary panel session and various poster sessions as well as presentations of ongoing work in the ESPRIT projects NERVES, G A L A T H E and ANNIE. Papers are solicited in the following areas: Potential technologies Hardware oriented modelling and simulation CMOS adequate design of neural algorithms System and chip architectures CAD for neural chip design Neural interfaces and sensors Further information can be requested from: Dr. Ulrich Ramacher Siemens AG Z F E ME FKS 32 Otto-Hahn-Ring 6 D-8000 Munich-83, West Germany
1990 Bipolar Circuits and Technology Meeting September 17-19, 1990 Minneapolis, MN, USA The Bipolar Circuits and Technology Meeting provides a forum for technical communication focused on the needs and interests of the bipolar community.
219
June 17-21, 1990 IJCNN'90. San Diego, CA, USA. Contact: Nomi Feldman, IJCNN'90 Conference Coordinator, 5665 Oberlin Drive, San Diego, CA 92121, USA, Tel. 619-453 6222, Fax. 619-453 7930. June 18-21, 1990 7th European Workshop on Design for Testability. Segovia, Spain. Contact: 7th European DFT Workshop, c / o Chelo Rodriguez, Telefonica I + D, Emilio Vargas 6-1a Plta., 28043 Madrid, Spain, Tel. + 34-1-337 4311, Fax. + 34-1-337 4212. June 24-30, 1990 IFIP WG10.5 Summer School on Formal Methods for VLSI Design. Lyngby, Denmark. Contact: Jorgen Staunstrup, Dept. of Computer Science, Building 344, Technical University of Denmark, DK-2800 Lyngby, Denmark, Tel. 45-4288 1566. June 24-28, 1990 27th ACM/IEEE Design Automation Conference. Orlando, FL, USA. Contact: MP Associates Inc., Alfred E. Dunlop, 7490 Clubhouse Road, Suite 102, Boulder, CO 80301, USA, Tel. 303-530 4333. June 25-26, 1990 ITG/IEEE Workshop on Microelectronics for Neural Networks. Dortmund, West Germany. Contact: Dr. Ulrich Ramacher, Siemens AG, ZFE ME FKS 32, Otto-Hahn-Ring 6, D-8000 Munich-83, West Germany. June 26-28, 1990 20th Annual International Symposium on Fault-Tolerant Computing. Newcastleupon-Tyne, UK. Contact: Prof. Bev. Littlewood, CSR, City University, Northampton Square, London EC1V 0HB, UK, Tel. +44-1-253 4399 ext. 4160, Fax. + 44-1-253 3861.
Calls for Papers 7th European Workshop on Design for Testability June 18-21, 1990 Segovia, Spain The European Workshop on Design for Testability aims to provide a biennual forum on the latest problems and solutions in the area of Design for Testability. Attendance is by invitation only and restricted to 70 persons. There will be four
220
Events
paper sessions, two panel sessions and four poster sessions. Possible topic areas to be addressed in papers and posters are: Emerging test technology Test of mixed analog/digital cirSilicon compilation and D F T cuitry Failure analysis Partitioning Self-test implementations High speed testing and interconTest generation & fault-tolerant circuity nect Testing of high reliable and faultBoundary-Scan tolerant circuitry Delay testing Further information can be obtained from: 7th European D F T Workshop c / o Chelo Rodriguez, Telefonica I + D Emilio Vargas 6-1 a Plta. 28043 Madrid, Spain Tel. + 34-1-337 4311 Fax. + 34-1-337 4212
ITG/IEEE Workshop on Microelectronics for Neural Networks June 25-26, 1990 Dortmund, West Germany This workshop is dedicated to hardware for neural networks and discussion of implementation constraints introduced by application, technology and sytem environment. The workshop will include an interdisciplinary panel session and various poster sessions as well as presentations of ongoing work in the ESPRIT projects NERVES, G A L A T H E and ANNIE. Papers are solicited in the following areas: Potential technologies Hardware oriented modelling and simulation CMOS adequate design of neural algorithms System and chip architectures CAD for neural chip design Neural interfaces and sensors Further information can be requested from: Dr. Ulrich Ramacher Siemens AG Z F E ME FKS 32 Otto-Hahn-Ring 6 D-8000 Munich-83, West Germany
1990 Bipolar Circuits and Technology Meeting September 17-19, 1990 Minneapolis, MN, USA The Bipolar Circuits and Technology Meeting provides a forum for technical communication focused on the needs and interests of the bipolar community.