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A 100 MHz VME data acquisition system
Nuclear Instruments and Methods in Physics Research A 337 (1993) 182-187 North-Holland
NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH Section A
A 100 MHz VME data acquisition system Associagâo EURATOM/IST Paulo César S. Simôes a, José Basilio S. Simôes a, Carlos M.B.A. Correia °, J. Sousa ', H. Fernandes b, B.B. Carvalho b and C.A.F. Varandas b Departamento de Fisica, Uniuersidade de Coimbra, 3000 Coimbra, Portugal n Centro de Fusdo Nuclear, Instituto Superior Técnico, 1096 Lisboa Codex, Portugal
Received 22 June 1993 A VME based 100 MSPS data acquisition system with four independent input channels and timing capability is presented. Data describing the performance of the system is also shown. Discussion is focused on the use of recently delivered devices, flash ADCs and high speed FIFO memories, configured in a data acquisition architecture, which takes advantage of the features inherent to those new devices. 1. Introduction In Nuclear Physics research, and in particular for experiments on large scale facilities, like for instance a tokamak, the need for high speed data acquisition systems frequently arises . The design of these systems is generally based on the operation of a flash ADC synchronised with a fast memory buffer . The association of memory to each acquisition channel also means that the system can operate autonomously after being programmed by the host VME computer and triggered. This feature also makes any eventual expansion of the system straightforward and linear since the software does not have to allocate any extra memory for the new boards. Generally, a trade-off between high speed, only
ADC1 IN
SC1
l
FIF01 FIF02 FIF03
JADC2 FIF04 SC2
WF1
available in ECL flash ADCs, and large memory capacities, required for large acquisition times, must be established and one of these features has to be sacrificed. New devices recently made available by several manufacturers have made it possible to design systems that take advantage of both the high speed of the new flash ADCs and the high capacity of modern CMOS FIFO memories . This paper describes one such architecture and shows results for its implementation in a VME module with the following characteristics : four independent input channels with 8 bit resolution and 32 KSamples of associated buffer memory, programmable sample rate up to 100 MSPS and, both, internal or external clock and trigger. 16 bit Data Bus
IWF2 WF3
SC1 SC2 WF1 WF2 WF3 WF4
Fig. 1. Block and timing diagrams of one input channel. 0168-9002/93/$06 .00 © 1993 - Elsevier Science Publishers B.V . All rights reserved
183
P.C.S. Simôes et al. / A 100 MHz VME data acquisition system N
aC
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C O w O .Û N N N bD
w
N Y N N
m 02
d Z
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d N
184
P.C.S . Sim5es et al. / A 100 MHz VME data acquisition system
2. Circuit description Two circuits are described which are correlated with each other: the conversion and storage circuit (figs. 1 and 2) and the clock generator circuit (fig. 3) with its associated timing diagram. The bus interface circuitry, that will not be described here, consists basically on seven 8 bit read/write registers allowing operation control and data transfer . The conversion and storage circuit is based on the AD9012 8 bit flash ADC driving the IDT7205-20 FIFOs associated in an interleaved configuration depicted in block diagram of fig. l . The AD9012 was chosen due to its high conversion rate and to its capability for directly interfacing TTL logic. These features are essential since we aimed at a single board four-channel instrument where each channel should be capable of holding a reasonable amount of data in its local memory . As shown in block diagram of fig. 1 the two ADCs are driven by two antiphase 50 MHz clocks (SCI and SC2) that combine together to produce a 10 ns sam-
pling period . Four FIFO memories, connected as shown, must be used since the fastest devices presently available, with capacities larger than 2 KWords, have a 30 ns write cycle time . Conversions are initiated by the rising edge of SC1 and SC2 and data is written into the FIFO at the rising edge of the WF 1, 2, 3, 4 signals derived from the timing circuit. Due to package restrains 8 K FIFOs were used leading to a channel capacity of 32 KWords or 320 l..s (at maximum acquisition rate). Fig. 2 shows the detailed circuit that has been implemented for each channel. Each ADC has its own adjustable reference voltage (ZN458). The input amplifier is a high speed current feedback device in an inverting amplifier geometry and two potentiometers, Tl and TZ , for gain and offset adjust respectively . The ADCs require a negative supply voltage of - 5.2 V which is supplied to the board through the spare pins in the P2 connector of the VME backplane . Since the complete circuit, with a total of 8 ADCs, sinks approximately 1.5 A from this voltage source, the use of a voltage regulator to generate -5 .2 V (from the -12 V of the VME backplane) would bring ther+sv
Fig. 3. Detailed clock circuit.
P.C.S. Sim5es et al. / A 100 MHz VME data acquisition system mal as well as space problems on the board and, thus, was avoided . The clock circuit (fig . 3) requires special precautions and a careful layout with an extensive ground plane and all critical lines terminated as close to the characteristic impedance as possible in order to minimise transmission line effects . The two antiphase start conversion signals for the ADCs (SC1 and SC2) are derived from the two XOR gates as shown in fig . 2 in order to keep the delays of both clock paths balanced . This arrangement forces one conversion every 10 ns, when the maximum sampling frequency is selected . Other sampling frequencies can be selected dividing the 50 MHz initial clock with flip-flops FF1 and FF2 for the 50 and 25 MSPS and the 74LS592 programmable counter for 6 .25 MSPS to 48 .8 KSPS . The selected frequency is gated by the 74AS151 multiplexer under the direct control of the VME host processor (ENCLKO, ENCLKI, ENCLK2 inputs) . The FIFOs write signals (WF1, WF2, WF3, WF4) are delivered by flip-flops FF4 and FF5 and are synchronised by FF3 in such a way that WF3 will always be the first active write signal in the sequence (3-1-42) .
3 . Software We have developed software, written in C language, for testing and also for operation under the OS/9 operating system . The test package emulates a digital oscilloscope allowing for the basic functions, such as sample rate and trigger mode selector for each input channel, to be performed by the host VME system and includes analysis routines that compute signal to noise ratio (SNR), effective number of bits (ENOB) and differential and integral nonlinearities (DNL and INL) . The operation software includes OS/9 drivers for interfacing with the host VME system and integration modules to the control and data acquisition system [1] of the tokamak ISTTOK [2] . The information concerning the main operating parameters resides in the ISTTOK Central Data Base [1] .
4. Results 4.1 . Tests Several tests were carried out in order to assess the performance of the board with the major concern focused on its dynamic parameters . Fig . 4 shows the SNR (signal to noise ratio) expressed both in effective number of bits (ENOB) of the
185 50
8r ADC I
__
6 ô
38
A DC2
2ADC"s _ 26 S v
14
1 2
0i 0
5
10
15
20
25
30
35
Sig-l Prequc-y (Milz)
50
38
2ADC"s
ô z
+2 10
Sir-1 Prcq-mq (MII .)
Fig. 4. SNR and ENOB for the three ADC combinations of channel 1 for different input signal frequency ranges .
converter as well as in dB as a function of the signal frequency . This data was obtained by analysing the converted signal in the frequency domain using a 512 point FFT . This method does not require too much computer time and correlates to better than 5% with the sine fitting method recommended by IEEE standard 1057 [3]. The curves shown in fig . 4 correspond to tests performed for each ADC (at 50 MSPS) and for the two ADCs in the interleaved configuration at the full 100 MSPS sampling rate. It can be noticed that ADCI systematically shows a better performance for the entire input signal frequency range (fin), This is certainly due to a layout asymmetry in the multilayer circuit board . The SNR degradation with fin is a direct consequence of jitter errors that become increasingly important for the higher values of f;r, . Jitter errors also justify the performance exhibited in the 100 MSPS interleaved circuit revealed by the third curve of fig . 4 . In fact, it should be noticed that for a 10 ns sampling period and 35 MHz fin and assuming 0 .5 ns rms for jitter (t i ) the SNR can be computed by the general expression SNR = 20 log
2 Tr ft i
186
P. C.S. Simöes et al. / A 100 MHz VME data acquisition system
to be 19 dB . As the clock circuit previously discussed operates at the very limit of TTL logic speed, jitter errors of this magnitude can be expected . Differential nonlinearity tests were also carried out and the results shown in fig. 5 where the channel width profiles and distributions are plotted for uniform spectra and 10 6 counts per channel. As expected a slight Channel 1
improvement occurs when the two ADCs are operating in the antiphase configuration . This improvement follows very closely to the expression 2 1(0-2 o-c = l + 0-2) 2 â
where Q represents the mean squared error of the respective distribution . This result has been systemati-
Differential Nonlinearity
ADC1
1 0 .8
a= 0.2 2
0 .6 0 .4 0 .2 W~~n~nl~~i~~nr~mvmun~rnc~rrlrnlirov~in~n~~nnwiR~~nivurr .0 .2
p
.0 .4 -0 .6 -0 .3
1
41
!1
121
161
201
241
0
Channel number
IS
30
ADC2
0 .8
a=0 .25
0 .6 0 .4
2
0 .2
0 .2 -0 .4 -0 .6
45
C It asaelSDNL It lalo&raas
I W__ ~rnroununri+tnmo~~n~~ln,i~~~rn!~~~n~~na~~~~~~nr~nln,~mnr I
~~~wunru~u~oln~i~uruu~~lu~uln~no!aluWn~u~runuo!~ru~~!r~~~jnln
MWMIMIWWIWWWMarr
-0 .t
41
si
121
161
201
241
0
Chassai sum ber
15
30
45
Channels DNL histogram
2 ADC's
0.8
a= 0.17
0.6 0.4 0.2 0
-0 .4 -0 .6 -0 .h
41
sl
121
161
201
T
241
Channel number
0
15
30
CIsa .aeIa DNL Is lslagraas
Fig. 5. Differential nonlinearity for the three ADC combinations of channel 1.
45
187
P.C.S. Sim5es et al. / A 100 MHz VME data acquisition system
1 V 0 0.8 t 0.6 s 0.4 0.2 0
1
201
401
601
801
1001
1201
1401
100 ns/Div
Fig. 6. Phase variation of the reflected signal from the ISTTOK microwave reflectometer. cally verified in a large number of tests and reveals the Gaussian nature of the channel widths distribution. Distributions were plotted for several input frequencies and the resulting pattern was consistent for frequencies from DC to fmax* 4.2. Operation
Some of these boards are currently being used for data acquisition in the microwave reflectometer [4] and X-ray diagnostic [5] of the tokamak ISTTOK. Fig. 6 presents the phase variations of the reflected signals of the microwave reflectometer . This data was obtained with external clock (given by a digital programmable function generator) and trigger (provided by a timing VME board [1]), using a sample rate of 10 MSPS . 5. Conclusions The board performed adequately in a variety of test and operating environments and several units are currently operating in a large experimental device providing reliable data from the above referred diagnostics . Particularly we are obtaining density profiles in less than 10 ws which is a very important procedure for transport studies in a nuclear fusion plasma .
The board design, namely the use of a four-layer printed circuit board with two power planes, has proved to be adequate for impedance matching and noise isolation. Acknowledgements This work was supported by "Instituto Superior Tecnico", "Departamento de Fisica da Universidade de Coimbra", "Junta Nacional de Investigag5o Cientifica e Tecnolôgica" and European Atomic Energy Community. References [1] C.A.F. Varandas et al ., The ISTTOK Control and Data Aquisition System, 17th Symp . on Fusion Technology, Rome, September 1992. [2] C.A .F . Varandas et al ., The Tokamak ISTTOK, 1st Brasilian Congress on Plasma Physics, vol. 1 (1991) p. 275. [3] IEEE Trial-Use Standard for Digitizing Waveform Recorders, IEEE Std 1057, July 1989. [4] P. Varela et al ., The Microwave Reflectometer for the Tokamak ISTTOK, internal report of Centro de Fusâo Nuclear (1993) . [5] P. Amorim, M.L . Carvalho, F. Nabais and C.A .F . Varandas, The X-ray Diagnostics for the Tokamak ISTTOK, internal report of Centro de Fusâo Nuclear (1993) .
NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH Section A
A 100 MHz VME data acquisition system Associagâo EURATOM/IST Paulo César S. Simôes a, José Basilio S. Simôes a, Carlos M.B.A. Correia °, J. Sousa ', H. Fernandes b, B.B. Carvalho b and C.A.F. Varandas b Departamento de Fisica, Uniuersidade de Coimbra, 3000 Coimbra, Portugal n Centro de Fusdo Nuclear, Instituto Superior Técnico, 1096 Lisboa Codex, Portugal
Received 22 June 1993 A VME based 100 MSPS data acquisition system with four independent input channels and timing capability is presented. Data describing the performance of the system is also shown. Discussion is focused on the use of recently delivered devices, flash ADCs and high speed FIFO memories, configured in a data acquisition architecture, which takes advantage of the features inherent to those new devices. 1. Introduction In Nuclear Physics research, and in particular for experiments on large scale facilities, like for instance a tokamak, the need for high speed data acquisition systems frequently arises . The design of these systems is generally based on the operation of a flash ADC synchronised with a fast memory buffer . The association of memory to each acquisition channel also means that the system can operate autonomously after being programmed by the host VME computer and triggered. This feature also makes any eventual expansion of the system straightforward and linear since the software does not have to allocate any extra memory for the new boards. Generally, a trade-off between high speed, only
ADC1 IN
SC1
l
FIF01 FIF02 FIF03
JADC2 FIF04 SC2
WF1
available in ECL flash ADCs, and large memory capacities, required for large acquisition times, must be established and one of these features has to be sacrificed. New devices recently made available by several manufacturers have made it possible to design systems that take advantage of both the high speed of the new flash ADCs and the high capacity of modern CMOS FIFO memories . This paper describes one such architecture and shows results for its implementation in a VME module with the following characteristics : four independent input channels with 8 bit resolution and 32 KSamples of associated buffer memory, programmable sample rate up to 100 MSPS and, both, internal or external clock and trigger. 16 bit Data Bus
IWF2 WF3
SC1 SC2 WF1 WF2 WF3 WF4
Fig. 1. Block and timing diagrams of one input channel. 0168-9002/93/$06 .00 © 1993 - Elsevier Science Publishers B.V . All rights reserved
183
P.C.S. Simôes et al. / A 100 MHz VME data acquisition system N
aC
U . 0 .U
C O w O .Û N N N bD
w
N Y N N
m 02
d Z
N
d N
184
P.C.S . Sim5es et al. / A 100 MHz VME data acquisition system
2. Circuit description Two circuits are described which are correlated with each other: the conversion and storage circuit (figs. 1 and 2) and the clock generator circuit (fig. 3) with its associated timing diagram. The bus interface circuitry, that will not be described here, consists basically on seven 8 bit read/write registers allowing operation control and data transfer . The conversion and storage circuit is based on the AD9012 8 bit flash ADC driving the IDT7205-20 FIFOs associated in an interleaved configuration depicted in block diagram of fig. l . The AD9012 was chosen due to its high conversion rate and to its capability for directly interfacing TTL logic. These features are essential since we aimed at a single board four-channel instrument where each channel should be capable of holding a reasonable amount of data in its local memory . As shown in block diagram of fig. 1 the two ADCs are driven by two antiphase 50 MHz clocks (SCI and SC2) that combine together to produce a 10 ns sam-
pling period . Four FIFO memories, connected as shown, must be used since the fastest devices presently available, with capacities larger than 2 KWords, have a 30 ns write cycle time . Conversions are initiated by the rising edge of SC1 and SC2 and data is written into the FIFO at the rising edge of the WF 1, 2, 3, 4 signals derived from the timing circuit. Due to package restrains 8 K FIFOs were used leading to a channel capacity of 32 KWords or 320 l..s (at maximum acquisition rate). Fig. 2 shows the detailed circuit that has been implemented for each channel. Each ADC has its own adjustable reference voltage (ZN458). The input amplifier is a high speed current feedback device in an inverting amplifier geometry and two potentiometers, Tl and TZ , for gain and offset adjust respectively . The ADCs require a negative supply voltage of - 5.2 V which is supplied to the board through the spare pins in the P2 connector of the VME backplane . Since the complete circuit, with a total of 8 ADCs, sinks approximately 1.5 A from this voltage source, the use of a voltage regulator to generate -5 .2 V (from the -12 V of the VME backplane) would bring ther+sv
Fig. 3. Detailed clock circuit.
P.C.S. Sim5es et al. / A 100 MHz VME data acquisition system mal as well as space problems on the board and, thus, was avoided . The clock circuit (fig . 3) requires special precautions and a careful layout with an extensive ground plane and all critical lines terminated as close to the characteristic impedance as possible in order to minimise transmission line effects . The two antiphase start conversion signals for the ADCs (SC1 and SC2) are derived from the two XOR gates as shown in fig . 2 in order to keep the delays of both clock paths balanced . This arrangement forces one conversion every 10 ns, when the maximum sampling frequency is selected . Other sampling frequencies can be selected dividing the 50 MHz initial clock with flip-flops FF1 and FF2 for the 50 and 25 MSPS and the 74LS592 programmable counter for 6 .25 MSPS to 48 .8 KSPS . The selected frequency is gated by the 74AS151 multiplexer under the direct control of the VME host processor (ENCLKO, ENCLKI, ENCLK2 inputs) . The FIFOs write signals (WF1, WF2, WF3, WF4) are delivered by flip-flops FF4 and FF5 and are synchronised by FF3 in such a way that WF3 will always be the first active write signal in the sequence (3-1-42) .
3 . Software We have developed software, written in C language, for testing and also for operation under the OS/9 operating system . The test package emulates a digital oscilloscope allowing for the basic functions, such as sample rate and trigger mode selector for each input channel, to be performed by the host VME system and includes analysis routines that compute signal to noise ratio (SNR), effective number of bits (ENOB) and differential and integral nonlinearities (DNL and INL) . The operation software includes OS/9 drivers for interfacing with the host VME system and integration modules to the control and data acquisition system [1] of the tokamak ISTTOK [2] . The information concerning the main operating parameters resides in the ISTTOK Central Data Base [1] .
4. Results 4.1 . Tests Several tests were carried out in order to assess the performance of the board with the major concern focused on its dynamic parameters . Fig . 4 shows the SNR (signal to noise ratio) expressed both in effective number of bits (ENOB) of the
185 50
8r ADC I
__
6 ô
38
A DC2
2ADC"s _ 26 S v
14
1 2
0i 0
5
10
15
20
25
30
35
Sig-l Prequc-y (Milz)
50
38
2ADC"s
ô z
+2 10
Sir-1 Prcq-mq (MII .)
Fig. 4. SNR and ENOB for the three ADC combinations of channel 1 for different input signal frequency ranges .
converter as well as in dB as a function of the signal frequency . This data was obtained by analysing the converted signal in the frequency domain using a 512 point FFT . This method does not require too much computer time and correlates to better than 5% with the sine fitting method recommended by IEEE standard 1057 [3]. The curves shown in fig . 4 correspond to tests performed for each ADC (at 50 MSPS) and for the two ADCs in the interleaved configuration at the full 100 MSPS sampling rate. It can be noticed that ADCI systematically shows a better performance for the entire input signal frequency range (fin), This is certainly due to a layout asymmetry in the multilayer circuit board . The SNR degradation with fin is a direct consequence of jitter errors that become increasingly important for the higher values of f;r, . Jitter errors also justify the performance exhibited in the 100 MSPS interleaved circuit revealed by the third curve of fig . 4 . In fact, it should be noticed that for a 10 ns sampling period and 35 MHz fin and assuming 0 .5 ns rms for jitter (t i ) the SNR can be computed by the general expression SNR = 20 log
2 Tr ft i
186
P. C.S. Simöes et al. / A 100 MHz VME data acquisition system
to be 19 dB . As the clock circuit previously discussed operates at the very limit of TTL logic speed, jitter errors of this magnitude can be expected . Differential nonlinearity tests were also carried out and the results shown in fig. 5 where the channel width profiles and distributions are plotted for uniform spectra and 10 6 counts per channel. As expected a slight Channel 1
improvement occurs when the two ADCs are operating in the antiphase configuration . This improvement follows very closely to the expression 2 1(0-2 o-c = l + 0-2) 2 â
where Q represents the mean squared error of the respective distribution . This result has been systemati-
Differential Nonlinearity
ADC1
1 0 .8
a= 0.2 2
0 .6 0 .4 0 .2 W~~n~nl~~i~~nr~mvmun~rnc~rrlrnlirov~in~n~~nnwiR~~nivurr .0 .2
p
.0 .4 -0 .6 -0 .3
1
41
!1
121
161
201
241
0
Channel number
IS
30
ADC2
0 .8
a=0 .25
0 .6 0 .4
2
0 .2
0 .2 -0 .4 -0 .6
45
C It asaelSDNL It lalo&raas
I W__ ~rnroununri+tnmo~~n~~ln,i~~~rn!~~~n~~na~~~~~~nr~nln,~mnr I
~~~wunru~u~oln~i~uruu~~lu~uln~no!aluWn~u~runuo!~ru~~!r~~~jnln
MWMIMIWWIWWWMarr
-0 .t
41
si
121
161
201
241
0
Chassai sum ber
15
30
45
Channels DNL histogram
2 ADC's
0.8
a= 0.17
0.6 0.4 0.2 0
-0 .4 -0 .6 -0 .h
41
sl
121
161
201
T
241
Channel number
0
15
30
CIsa .aeIa DNL Is lslagraas
Fig. 5. Differential nonlinearity for the three ADC combinations of channel 1.
45
187
P.C.S. Sim5es et al. / A 100 MHz VME data acquisition system
1 V 0 0.8 t 0.6 s 0.4 0.2 0
1
201
401
601
801
1001
1201
1401
100 ns/Div
Fig. 6. Phase variation of the reflected signal from the ISTTOK microwave reflectometer. cally verified in a large number of tests and reveals the Gaussian nature of the channel widths distribution. Distributions were plotted for several input frequencies and the resulting pattern was consistent for frequencies from DC to fmax* 4.2. Operation
Some of these boards are currently being used for data acquisition in the microwave reflectometer [4] and X-ray diagnostic [5] of the tokamak ISTTOK. Fig. 6 presents the phase variations of the reflected signals of the microwave reflectometer . This data was obtained with external clock (given by a digital programmable function generator) and trigger (provided by a timing VME board [1]), using a sample rate of 10 MSPS . 5. Conclusions The board performed adequately in a variety of test and operating environments and several units are currently operating in a large experimental device providing reliable data from the above referred diagnostics . Particularly we are obtaining density profiles in less than 10 ws which is a very important procedure for transport studies in a nuclear fusion plasma .
The board design, namely the use of a four-layer printed circuit board with two power planes, has proved to be adequate for impedance matching and noise isolation. Acknowledgements This work was supported by "Instituto Superior Tecnico", "Departamento de Fisica da Universidade de Coimbra", "Junta Nacional de Investigag5o Cientifica e Tecnolôgica" and European Atomic Energy Community. References [1] C.A.F. Varandas et al ., The ISTTOK Control and Data Aquisition System, 17th Symp . on Fusion Technology, Rome, September 1992. [2] C.A .F . Varandas et al ., The Tokamak ISTTOK, 1st Brasilian Congress on Plasma Physics, vol. 1 (1991) p. 275. [3] IEEE Trial-Use Standard for Digitizing Waveform Recorders, IEEE Std 1057, July 1989. [4] P. Varela et al ., The Microwave Reflectometer for the Tokamak ISTTOK, internal report of Centro de Fusâo Nuclear (1993) . [5] P. Amorim, M.L . Carvalho, F. Nabais and C.A .F . Varandas, The X-ray Diagnostics for the Tokamak ISTTOK, internal report of Centro de Fusâo Nuclear (1993) .