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A 2.4 GHz high output power and high efficiency power amplifier operating at inductive breakdown in CMOS technology
Microelectronics Journal 45 (2014) 449–453
Contents lists available at ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
A 2.4 GHz high output power and high efficiency power amplifier operating at inductive breakdown in CMOS technology Chie-In Lee a,b,n, Wei-Cheng Lin a, Yan-Ting Lin a a b
Department of Electrical Engineering, National Sun Yat-Sen University, No. 70 Lienhai Road, Kaohsiung 80424, Taiwan Institute of Communications Engineering, National Sun Yat-Sen University, No. 70 Lienhai Road, Kaohsiung 80424, Taiwan
art ic l e i nf o
a b s t r a c t
Article history: Received 7 June 2013 Received in revised form 13 January 2014 Accepted 6 February 2014 Available online 22 February 2014
In this paper, a novel CMOS power amplifier (PA) with high output power and power added efficiency is designed to operate in the avalanche region by increasing the supply voltage for the first time. With the X-parameter measurement based poly-harmonic distortion (PHD) behavioral model including the XS and XT terms, the simulation results can reveal accurate large signal characteristics of the whole PA at breakdown. The output power at 1-dB compression point of 30.2 dBm with 34.1% PAE at 2.4 GHz is obtained. & 2014 Elsevier Ltd. All rights reserved.
Keywords: CMOS Power amplifier Avalanche breakdown Poly-harmonic distortion
1. Introduction Due to the low-cost and high integration with the baseband circuits of the silicon, the radio-frequency (RF) power amplifier (PA) in the front-end circuit is implemented via the CMOS technology [1–6]. To prevent the transistor from burning out with large output swing, the drain supply voltage VDD of the transistors is conventionally fixed at the voltage between the knee voltage and breakdown voltage. Different from the compound technology, the VDD of the CMOS circuits is lowered due to the low breakdown voltage [7] to avoid output voltage compression. Therefore, the output power of the CMOS PA cannot be increased because the output power is proportional to the VDD [4,8]. In [9], the supply voltage of the cascode SiGe PA is increased to obtain higher output power and efficiency because the common-base (CB) heterojunction bipolar transistor (HBT) can operate in the weak avalanche breakdown region safely below BVcbo. For the MOSFET, the power cell [4,10] is commonly used to increase the maximum output power. In addition, the power-combining technique [11] can be utilized to combine the output power delivered from each power cell via a transformer if Watt-level output power is required. To predict the RF power performances under large signal excitation condition, the X-parameter based poly-harmonic distortion (PHD) nonlinear behavioral model is developed in recent years [12,13]. n Corresponding author at: Department of Electrical Engineering, National Sun Yat-Sen University, No. 70 Lienhai Road, Kaohsiung 80424, Taiwan. Tel.: þ 886 7 525 2000 4110; fax: þ886 7 525 4199. E-mail address: [email protected] (C.-I. Lee).
http://dx.doi.org/10.1016/j.mejo.2014.02.008 0026-2692 & 2014 Elsevier Ltd. All rights reserved.
The XT term in the X-parameters accounts for the nonlinear effects. This behavioral model is suitable for nonlinear operation especially for the high power PA design. Our previous research was devoted to exploring the inductive behavior of the p–n junction [14,15]. This theory is applied to the RF breakdown characterization of the MOSFETs [16]. In this paper, a CMOS PA is designed to operate in the inductive breakdown region to improve power performances for the first time. Different from the breakdown operated SiGe cascode PA consisting of two HBTs in common-emitter (CE) and CB configurations [9], the presented CMOS PA operates in the breakdown regime is in a simpler common-source (CS) configuration. The supply voltage of the power stage is increased to extend the allowable output voltage operating range without significant distortion. The X-parameter based PHD model is utilized to reveal the large signal characteristics accurately in the breakdown region.
2. Large signal analysis and circuit design Conventionally, the MOSFET is biased in the saturation region to prevent the output swing from being limited by the breakdown voltage. The presented 0.18 μm CMOS PA shown in Fig. 1 operates in the breakdown region of VDD 2.2 V with the RF avalanche breakdown considered. As the MOSFET operates in the avalanche breakdown region, the inductive reflection coefficient at the output is observed due to the breakdown inductance influenced [16]. The RF breakdown voltage where the inductive behavior occurs initially is illustrated in Fig. 2(a) for the single MOSFET with
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C.-I. Lee et al. / Microelectronics Journal 45 (2014) 449–453
Fig. 1. The presented CMOS PA. (a) Schematic. (b) Layout. (c) Design flowchart.
Fig. 2. The characterization of the PA. (a) The dynamic load line at 2.4 GHz predicted by the PHD model for the PA. The load line is superimposed to measured DC I–V. (b) The measured (circles) and simulated (lines) load-pull contour at VGS of 1.2 V and VDD of 2.2 V. Input power is 5 dBm. (c) The voltage waveform at the output of the power cell obtained from PHD model at VGS of 0.8 V and VDD of 2.2 V (solid symbols) and 1.8 V (open symbols). The input power is 0 dBm. (d) The voltage waveform at the output of the power cell obtained from the PHD model at VGS of 0.8 V and VDD of 2.2 V. The input power is from 20 to 0 dBm with 5 dBm step.
C.-I. Lee et al. / Microelectronics Journal 45 (2014) 449–453
8 15 μm gate width and 0.18 μm gate length fabricated by Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan 0.18 μm CMOS process. By using the Agilent 8563E spectrum analyzer and E4438C signal generator under the onetone excitation condition, the measured output power at 1-dB compression point (OP1 dB) of the single MOSFET at breakdown is 5.2 dBm (VGS ¼0.8 V and VDS ¼ 2.2 V) which is higher than OP1 dB of 3.6 dBm at saturation (VGS ¼0.8 V and VDS ¼ 1.8 V). The Volterra model of this single MOSFET is established through polynomial expansion [17]. Because the equivalent circuit contains reactive components, the calculated Volterra kernels can be a phasor as follows: H 3_gm ¼
H 3_Lj ¼
H2 ¼
" 3 ðY g þ s0″C gs Þ Yg K 3gm 0 0 0 ðY g þ s ″C gs ÞY d ðs ″Þ Y g þ s C gs 2 # K 2Cgs Yg Yg þ 2K 2gm Y g þ s0 C gs Y g þ s″C gs Y g þ s0 C gs
i ðY g þ s″0 C gs Þ h K H 3 þ 2K 2Lj H 1 H 2 ðY g þ s″0 C gs ÞY d ðs″0 Þ 3Lj 1
ð1Þ
ð2Þ
2 Y ðY g þ s0 C gs Þ K 2gm Y g þ sg0 C gs þ K 2gds H 21 þ K 2Lj H 21 þ K 2Rj H 21 þ g m K 2Cgs H 21 ðY g þ s″C gs ÞY d ðs″Þ
ð3Þ H1 ¼
gm Y g ðY g þ s0 C gs ÞY d ðs0 Þ
ð4Þ
Y g ¼ 1=Rsource
ð5Þ
Y d ðsÞ ¼ g ds þ 1=sLj þ 1=Rj þ 1=RL
ð6Þ
s0 ¼ jω
ð7Þ
s″ ¼ j2ω
ð8Þ
s0″ ¼ j3ω
ð9Þ
H3_gm and H3_Lj are the third-order Volterra kernels generated from transconductance and breakdown inductance, respectively. The effects of parasitics and gate-drain capacitance are neglected [18]. According to the calculation results, the phase difference between the transconductance and breakdown inductance contribution is almost π. In addition, the contribution of breakdown inductance increases with increasing drain voltage due to increased high order coefficient of breakdown inductance at high biases less than 2.4 V. Therefore, the nonlinearity from transconductance can be reduced by the increased nonlinearity from breakdown inductance in the high bias region due to the opposite phase. The X-parameter used here is to design a cascade PA and to further demonstrate the linearity improvement at breakdown. The X-parameter is able to characterize the change in response due to mismatch in a cascaded system because the XS and XT mismatch terms in the Jacobian mathematics [19] are taken into account. With these XS and XT mismatch terms considered, the validity of the X-parameter model of a single device can be extended to multi-stage circuits in cascade. Furthermore, the XT term considers the decrease of phase of the scattered wave with increasing phase of the incident wave [12,19,20]. This XT term provides improvement in predicting mismatch behavior when the input power is high. The X-parameter measurement can save time required to develop the nonlinear model [20], providing an alternative nonlinear circuit design approach. The flowchart of the design approach using PHD model is shown in Fig. 1(c). The X-parameter measurement based PHD behavioral model is able to reveal the
451
characteristics under the nonlinear operation. Especially for the breakdown regime, the PHD approach is an accurate large signal modeling methodology due to the XT term included at the high input power [12]. The measured magnitude of XT22 can be larger than the value of XS22 as VDS exceeds 2.2 V from the X-parameters for the single MOSFET used in the presented PA. This shows that the XT terms are significant at breakdown and have to be considered [12,19]. Based on the measured X-parameter model of the single MOSFET, the results of this presented three-stage cascaded PA in which the multiple MOSFETs connected in cascade are valid due to the XS and XT terms considered by this novel X-parameter technique. To further validate the accuracy of the PHD model at breakdown, the measured load-pull contour for the single MOSFET is compared with the simulated results from PHD model at VGS ¼ 1.2 V and VDS ¼2.2 V as shown in Fig. 2(b). Good agreement between measured and simulated results is obtained. It is demonstrated that the PHD model of the single MOSFET can simulate accurate large signal power performance in the breakdown region. The PHD behavioral model of the single MOSFET is implemented in the circuit to analyze the large signal characteristics and to design the presented PA. When compared with the compact model, the development time of the behavioral model is shorter [21]. In addition, the real large signal characteristics can be directly captured by the behavioral model. The dynamic load line obtained from PHD model is shown in Fig. 2(a). It is observed even when the load line exceeds the RF breakdown voltage, the compression is not significant due to the nonlinear cancellation between breakdown inductance and transconductance. Therefore, the upper edge of the waveform of the power cell can be swept from 0 to 3 V safely as shown in Fig. 2(c). For the lower edge, because the allowable operating range at breakdown is enlarged, the waveform shown in Fig. 2(c) can sweep to 2.5 V. Both the OP1 dB measurement and PHD simulation results have demonstrated the feasibility of breakdown operation. Therefore, the large allowable voltage operating range in the presented PA can be obtained. In Fig. 2(d), the simulated large signal voltage waveform of the power cell from PHD is shown as the input signal contains the harmonics from the last stage. The clipped waveform at the lower edge due to the knee voltage is characterized accurately by the PHD model. The X-parameters can predict the nonlinear behavior more accurately in the breakdown and knee voltage regions due to the XT term included [12]. In addition, when the PA is driven into large signal operation, harmonic signals are generated from the transistors. Because the X-parameters can describe the response of the multi-harmonic input [12], the power performance of the cascaded PA can be accurately obtained by using the PHD model. The PA is composed of three stages including two driver stages and one power stage operating in the breakdown region as shown in Fig. 1. Because the avalanche breakdown of the MOSFET occurs in the drain junction [16], the presented CMOS PA is designed in CS configuration to drive the power cells into the breakdown regime for increasing the output power. The balun is employed to transform the single-ended signal to the differential signal. The RF signal is amplified by two driver stages and then delivered to the power stage. The power stage consists of several power cells to increase the output power. The inter-stage matching is made with a highpass LC network as shown in Fig. 1. Inductor in the interstage matching network acts as a RF choke and as an impedance matching element at the same time. Capacitor can be used as a DC blocking and as an impedance matching element simultaneously. Therefore, this high pass LC network is selected as the inter-stage matching because it can incorporate both DC biasing and impedance matching. To combine the power delivered from the power cells, a transformer at the output is designed. The bias point of the driver stage is at VGS ¼ 1.2 V and VDS ¼ 1.8 V, and the gate width is
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Table 1 This work performance and comparison with other CMOS PAs. Technology This work [1] [2] [3] a b
CMOS CMOS CMOS CMOS
0.18 μm 0.18 μm 0.18 μm 0.13 μm
Frequency [GHz]
Power gain [dB]
OP1dB [dBm]
Power consumption [W]
PAE [%]
FOMa [104 mW GHz2]
2.4 (2.3–2.5) 1b 2.4 (2.3–2.5) 2.4 (2.3–2.5)
38.3 25 12.5 17
30.2 29 23 19
4.35 3.9 0.41 0.14
34.1 36 46 57
1391 9 1 1.3
FOM ¼ OP1dB Gain PAE frequency2. Bandwidth is not provided.
7 8 15 μm3. The higher gate voltage is designed to increase the gain. The power consumption of the drive stages is 0.13 W. The power stage is biased in class AB to increase the efficiency, and the bias point is at VGS ¼ 0.8 V and VDS ¼ 2.2 V in the breakdown region. The gate width of the power stage is 60 8 15 μm3. The power consumption of the power stage is 4.22 W. Therefore, the total power consumption of the presented PA is about 4.35 W as shown in Table 1.
3. Results and discussion Fig. 1(a) shows the schematic of the presented CMOS PA. The die area is 1 2 mm2 including RF pads as shown in Fig. 1(b). The supply voltage of the power cell shown in Fig. 1 is increased to the breakdown region to obtain higher output power and PAE. The measurement based PHD model of the single MOSFET is extracted from X-parameters through Agilent N5242A PNA-X microwave network analyzer. With the aid of PHD model which has been verified by load-pull data as shown in Fig. 2(b), the real power performances of the PA operating in the breakdown regime can be revealed accurately. The post-layout simulation results of the presented PA are shown in Fig. 3. The results of the presented CMOS PA is reliable because the validity of the X-parameter model has been verified in the circuit level design as in [13]. The linear power gain is 38.3 dB, the OP1 dB is 30.2 dBm, and the PAE is 34.1% at breakdown as shown in Fig. 3. The OP1 dB can evaluate linearity of PA. The bandwidth of the PA is about 200 MHz. The better power performances at VDD of 2.2 V are observed when compared with the results at VDD of 1.8 V. The results indicate that the power performances can be improved by operating in the breakdown regime. The presented PA has a simpler CS transistor core circuit when compared with the SiGe cascode PA using two HBTs in CE and CB configurations [9]. The results are also compared with the published CMOS PAs as shown in Table 1 and high figure-of-merit (FOM) including the DC power consumption, OP1 dB, gain, and efficiency information at the operating frequency is achieved [22,23]. The long term measurement was conducted to test the reliability of the MOSFET used in the presented PA in the breakdown region. The DC stress was set in the breakdown region of VGS ¼0.8 V, VDS ¼2.2 V and saturation region of VGS ¼1.2 V, VDS ¼1.8 V as in the PA. The DC stress was applied to the MOSFET continuously for about 1000 s which is the same as the stress time reported in [24]. According to the measured results, we found that stress does not degrade output power over 0.5 dBm after 1000 s. Because the oxide thickness of the standard 0.18 μm MOSFET used is higher than 3 nm, degradation due to reliability is insignificant in the presented work. (Performance degradation may take place if the oxide thickness is lower than 3 nm [24].) In [25], it also indicates that the reliability of the PA can be kept when device degradation is insignificant. Therefore, the used single MOSFET which can operate continuously for large time intervals in the breakdown region can be utilized to construct a reliable PA.
Fig. 3. The performances of the presented CMOS PA from the PHD model including XS and XT terms at 2.4 GHz. The results at VDD of 2.2 V (solid line) and 1.8 V (dash line) are shown. The curves marked by squares, circles, and triangles depict the power gain, output power, and PAE, respectively.
Table 2 Performances at different VDD of power stage. Other bias conditions remain the same. PHD model VDD (V)
Gain (dB)
Pout (dBm)
OP1 dB (dBm)
PAE (%)
1.8 2.2
37.4 38.3
28.8 32
27.4 30.2
21.3 34.1
Fig. 4. The voltage waveform of the presented CMOS PA from the PHD model at the output from 20 to 0 dBm with 10 dBm step.
When the power stage is driven in the saturation regime, the maximum output power and PAE are 28.8 dBm and 21.3%, respectively, which are lower than the results at breakdown as shown in
C.-I. Lee et al. / Microelectronics Journal 45 (2014) 449–453
Fig. 3 and Table 2. This is because the lower VDD results in smaller allowable output voltage swing when compared with the results at breakdown. In addition, the power gain under the breakdown operating condition is improved. The PAE is higher in the breakdown region because the PAE can increase with the supply voltage [9] although the power consumption increases. The FOM of the PA designed to operate in the breakdown regime is 1391 104. The results from the accurate PHD model shown in Figs. 3 and 4 and Table 2 have demonstrated the circuit performances can be improved by operating in the breakdown operation in CMOS technology. 4. Conclusion In this paper, a CMOS PA operating in the inductive breakdown region is designed to obtain high output power and PAE for the first time. The upper edge of the output voltage waveform is not compressed in the breakdown regime because our Volterra analysis indicates the nonlinear breakdown inductance cancels the nonlinear transconductance. The VDD of the power cell increases from 1.8 V to 2.2 V and then the output power and PAE of the whole PA are raised by 3.2 dB and 12.8%, respectively. Based on the X-parameter measurement based PHD model which has been verified by the load-pull data, the OP1 dB and PAE at breakdown are 30.2 dBm and 34.1% at 2.4 GHz, respectively. When comparing with the published CMOS PA, the high FOM of the presented PA is achieved. Therefore, the results of the PA based on the PHD model demonstrate the power performance improvement by operating in the breakdown region. Acknowledgments The authors would like to thank National Chip Implementation Center (CIC), Hsinchu, Taiwan for TSMC design kits, the National Nano Device Laboratories (NDL) for the X-parameter measurement support, and the Wireless Communication Antenna Research Center, Kaohsiung, Taiwan for the support. This work is also supported in part by the National Science Council of Taiwan under Grants NSC101-2221-E-110-077 and NSC100-2221-E-110-085. References [1] D. Tavakolifar, J. Javidan, Design of compact transformer-type power combiner for watt-level PA in CMOS technology, Int. J. Eng. Res. Appl. 2 (2) (2012) 313–321.
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[2] N. Masoumi, M. Moghaddam Tabrizi, CMOS linear high performance push amplifier for WiMAX power amplifier, Microelectron. J. 43 (8) (2012) 521–529. [3] H. Bameri, A. Hakimi, M. Movahhedi, A linear-high range output power control technique for cascode power amplifiers, Microelectron. J. 42 (9) (2011) 1025–1031. [4] T. Sowlati, D.M.W. Leenaerts, A 2.4-GHz 0.18-μm CMOS self-biased cascode power amplifier, IEEE J. Solid-State Circuits 38 (8) (2003) 1318–1324. [5] D. Gómez, C. Dufis, J. Altet, D. Mateo, J.L. González, Electro-thermal coupling analysis methodology for RF circuits, Microelectron. J. 43 (9) (2012) 633–641. [6] Q. Wan, C. Wang, A low-voltage low-power CMOS transmitter front-end using current mode approach for 2.4 GHz wireless communications, Microelectron. J. 42 (5) (2011) 766–771. [7] I. Aoki, S. Kee, R. Magoon, R. Aparicio, F. Bohn, J. Zachan, G. Hatcher, D. McClymont, A. Hajimiri, A fully-integrated quad-band GSM/GPRS CMOS power amplifier, IEEE J. Solid-State Circuits 43 (12) (2008) 2747–2758. [8] D. Sira, P. Thomsen, T. Larsen, A cascode modulated class-E power amplifier for wireless communications, Microelectron. J. 42 (1) (2011) 141–147. [9] Y. Sun, G.G. Fischer, J.C. Scheytt, A compact linear 60-GHz PA with 29.2% PAE operating at weak avalanche area in SiGe, IEEE Trans. Microw. Theory Tech. 60 (8) (2012) 2581–2589. [10] M.C. Tu, Y.C. Wang, H.Y. Ueng, Linearity optimizing on HBT power amplifier design, Microelectron. J. 40 (12) (2009) 1714–1718. [11] A. Hajimiri, Next-generation CMOS RF power amplifiers, IEEE Microw. Mag. 12 (1) (2011) 38–45. [12] J. Verspecht, D.E. Root, Polyharmonic distortion modeling, IEEE Microw. Mag. 7 (3) (2006) 44–57. [13] J. Sifri, X-parameters aid MMIC design, Microw. RF 49 (7) (2010) 55–64. [14] C.I. Lee, V.H. Ngo, D.S. Pan, Inductance probing into the semiconductor breakdown, Appl. Phys. Lett. 89 (17) (2006) (172112–172112-3). [15] C.I. Lee, D.S. Pan, Theory for high Q p-n junction avalanche inductors, Appl. Phys. Lett. 89 (1) (2006) (013501–013501-3). [16] C.I. Lee, W.C. Lin, Y.T. Lin, Modeling inductive behavior of MOSFET scattering parameter S22 in the breakdown regime, IEEE Trans. Microw. Theory Tech. 60 (3) (2012) 502–508. [17] S.A. Maas, Nonlinear Microwave and RF Circuits, 2nd ed., Artech House, Norwood, MA, 2003. [18] S. Ganesan, E. Sanchez-Sinencio, J. Silva-Martinez, A highly linear low-noise amplifier, IEEE Trans.Microw. Theory Tech. 54 (12) (2006) 4079–4085. [19] J. Verspecht, D.F. Williams, D. Schreurs, K.A. Remley, M.D. McKinley, Linearization of large-signal scattering functions, IEEE Trans. Microw. Theory Tech. 53 (4) (2005) 1369–1376. [20] C. Baylis, R.J. Marks, J. Martin, H. Miller, M. Moldovan, Going nonlinear, IEEE Microw. Mag. 12 (2) (2011) 55–64. [21] D.E. Root, J. Verspecht, D. Sharrit, J. Wood, A. Cognata, Broad-band polyharmonic distortion (PHD) behavioral models from fast automated simulations and large-signal vectorial network measurements, IEEE Trans. Microw. Theory Tech. 53 (11) (2005) 3656–3664. [22] Int. Technol. Roadmap for Semiconductors (ITRS), 2011, System Drivers [Online], Available from: 〈http://www.itrs.net/Links/2011ITRS/2011Chapters/ 2011SysDrivers.pdf〉. [23] V. Giammello, E. Ragonese, G. Palmisano, A transformer-coupling currentreuse SiGe HBT power amplifier for 77-GHz automotive radar, IEEE Trans. Microwave Theory Tech. 60 (6) (2012) 1676–1683. [24] C. Yu, J.-S. Yuan, H. Yang, MOSFET linearity performance degradation subject to drain and gate voltage stress, IEEE Trans. Device Mater. Reliab. 4 (4) (2004) 681–689. [25] M. Apostolidou, M.P. van der Heijden, D.M.W. Leenaerts, J. Sonsky, A. Heringa, I. Volokhine, A 65 nm CMOS 30 dBm class-E RF power amplifier with 60% PAE and 40% PAE at 16 dB back-off, IEEE J. Solid-State Circuits 44 (5) (2009) 1372–1379.
Contents lists available at ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
A 2.4 GHz high output power and high efficiency power amplifier operating at inductive breakdown in CMOS technology Chie-In Lee a,b,n, Wei-Cheng Lin a, Yan-Ting Lin a a b
Department of Electrical Engineering, National Sun Yat-Sen University, No. 70 Lienhai Road, Kaohsiung 80424, Taiwan Institute of Communications Engineering, National Sun Yat-Sen University, No. 70 Lienhai Road, Kaohsiung 80424, Taiwan
art ic l e i nf o
a b s t r a c t
Article history: Received 7 June 2013 Received in revised form 13 January 2014 Accepted 6 February 2014 Available online 22 February 2014
In this paper, a novel CMOS power amplifier (PA) with high output power and power added efficiency is designed to operate in the avalanche region by increasing the supply voltage for the first time. With the X-parameter measurement based poly-harmonic distortion (PHD) behavioral model including the XS and XT terms, the simulation results can reveal accurate large signal characteristics of the whole PA at breakdown. The output power at 1-dB compression point of 30.2 dBm with 34.1% PAE at 2.4 GHz is obtained. & 2014 Elsevier Ltd. All rights reserved.
Keywords: CMOS Power amplifier Avalanche breakdown Poly-harmonic distortion
1. Introduction Due to the low-cost and high integration with the baseband circuits of the silicon, the radio-frequency (RF) power amplifier (PA) in the front-end circuit is implemented via the CMOS technology [1–6]. To prevent the transistor from burning out with large output swing, the drain supply voltage VDD of the transistors is conventionally fixed at the voltage between the knee voltage and breakdown voltage. Different from the compound technology, the VDD of the CMOS circuits is lowered due to the low breakdown voltage [7] to avoid output voltage compression. Therefore, the output power of the CMOS PA cannot be increased because the output power is proportional to the VDD [4,8]. In [9], the supply voltage of the cascode SiGe PA is increased to obtain higher output power and efficiency because the common-base (CB) heterojunction bipolar transistor (HBT) can operate in the weak avalanche breakdown region safely below BVcbo. For the MOSFET, the power cell [4,10] is commonly used to increase the maximum output power. In addition, the power-combining technique [11] can be utilized to combine the output power delivered from each power cell via a transformer if Watt-level output power is required. To predict the RF power performances under large signal excitation condition, the X-parameter based poly-harmonic distortion (PHD) nonlinear behavioral model is developed in recent years [12,13]. n Corresponding author at: Department of Electrical Engineering, National Sun Yat-Sen University, No. 70 Lienhai Road, Kaohsiung 80424, Taiwan. Tel.: þ 886 7 525 2000 4110; fax: þ886 7 525 4199. E-mail address: [email protected] (C.-I. Lee).
http://dx.doi.org/10.1016/j.mejo.2014.02.008 0026-2692 & 2014 Elsevier Ltd. All rights reserved.
The XT term in the X-parameters accounts for the nonlinear effects. This behavioral model is suitable for nonlinear operation especially for the high power PA design. Our previous research was devoted to exploring the inductive behavior of the p–n junction [14,15]. This theory is applied to the RF breakdown characterization of the MOSFETs [16]. In this paper, a CMOS PA is designed to operate in the inductive breakdown region to improve power performances for the first time. Different from the breakdown operated SiGe cascode PA consisting of two HBTs in common-emitter (CE) and CB configurations [9], the presented CMOS PA operates in the breakdown regime is in a simpler common-source (CS) configuration. The supply voltage of the power stage is increased to extend the allowable output voltage operating range without significant distortion. The X-parameter based PHD model is utilized to reveal the large signal characteristics accurately in the breakdown region.
2. Large signal analysis and circuit design Conventionally, the MOSFET is biased in the saturation region to prevent the output swing from being limited by the breakdown voltage. The presented 0.18 μm CMOS PA shown in Fig. 1 operates in the breakdown region of VDD 2.2 V with the RF avalanche breakdown considered. As the MOSFET operates in the avalanche breakdown region, the inductive reflection coefficient at the output is observed due to the breakdown inductance influenced [16]. The RF breakdown voltage where the inductive behavior occurs initially is illustrated in Fig. 2(a) for the single MOSFET with
450
C.-I. Lee et al. / Microelectronics Journal 45 (2014) 449–453
Fig. 1. The presented CMOS PA. (a) Schematic. (b) Layout. (c) Design flowchart.
Fig. 2. The characterization of the PA. (a) The dynamic load line at 2.4 GHz predicted by the PHD model for the PA. The load line is superimposed to measured DC I–V. (b) The measured (circles) and simulated (lines) load-pull contour at VGS of 1.2 V and VDD of 2.2 V. Input power is 5 dBm. (c) The voltage waveform at the output of the power cell obtained from PHD model at VGS of 0.8 V and VDD of 2.2 V (solid symbols) and 1.8 V (open symbols). The input power is 0 dBm. (d) The voltage waveform at the output of the power cell obtained from the PHD model at VGS of 0.8 V and VDD of 2.2 V. The input power is from 20 to 0 dBm with 5 dBm step.
C.-I. Lee et al. / Microelectronics Journal 45 (2014) 449–453
8 15 μm gate width and 0.18 μm gate length fabricated by Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan 0.18 μm CMOS process. By using the Agilent 8563E spectrum analyzer and E4438C signal generator under the onetone excitation condition, the measured output power at 1-dB compression point (OP1 dB) of the single MOSFET at breakdown is 5.2 dBm (VGS ¼0.8 V and VDS ¼ 2.2 V) which is higher than OP1 dB of 3.6 dBm at saturation (VGS ¼0.8 V and VDS ¼ 1.8 V). The Volterra model of this single MOSFET is established through polynomial expansion [17]. Because the equivalent circuit contains reactive components, the calculated Volterra kernels can be a phasor as follows: H 3_gm ¼
H 3_Lj ¼
H2 ¼
" 3 ðY g þ s0″C gs Þ Yg K 3gm 0 0 0 ðY g þ s ″C gs ÞY d ðs ″Þ Y g þ s C gs 2 # K 2Cgs Yg Yg þ 2K 2gm Y g þ s0 C gs Y g þ s″C gs Y g þ s0 C gs
i ðY g þ s″0 C gs Þ h K H 3 þ 2K 2Lj H 1 H 2 ðY g þ s″0 C gs ÞY d ðs″0 Þ 3Lj 1
ð1Þ
ð2Þ
2 Y ðY g þ s0 C gs Þ K 2gm Y g þ sg0 C gs þ K 2gds H 21 þ K 2Lj H 21 þ K 2Rj H 21 þ g m K 2Cgs H 21 ðY g þ s″C gs ÞY d ðs″Þ
ð3Þ H1 ¼
gm Y g ðY g þ s0 C gs ÞY d ðs0 Þ
ð4Þ
Y g ¼ 1=Rsource
ð5Þ
Y d ðsÞ ¼ g ds þ 1=sLj þ 1=Rj þ 1=RL
ð6Þ
s0 ¼ jω
ð7Þ
s″ ¼ j2ω
ð8Þ
s0″ ¼ j3ω
ð9Þ
H3_gm and H3_Lj are the third-order Volterra kernels generated from transconductance and breakdown inductance, respectively. The effects of parasitics and gate-drain capacitance are neglected [18]. According to the calculation results, the phase difference between the transconductance and breakdown inductance contribution is almost π. In addition, the contribution of breakdown inductance increases with increasing drain voltage due to increased high order coefficient of breakdown inductance at high biases less than 2.4 V. Therefore, the nonlinearity from transconductance can be reduced by the increased nonlinearity from breakdown inductance in the high bias region due to the opposite phase. The X-parameter used here is to design a cascade PA and to further demonstrate the linearity improvement at breakdown. The X-parameter is able to characterize the change in response due to mismatch in a cascaded system because the XS and XT mismatch terms in the Jacobian mathematics [19] are taken into account. With these XS and XT mismatch terms considered, the validity of the X-parameter model of a single device can be extended to multi-stage circuits in cascade. Furthermore, the XT term considers the decrease of phase of the scattered wave with increasing phase of the incident wave [12,19,20]. This XT term provides improvement in predicting mismatch behavior when the input power is high. The X-parameter measurement can save time required to develop the nonlinear model [20], providing an alternative nonlinear circuit design approach. The flowchart of the design approach using PHD model is shown in Fig. 1(c). The X-parameter measurement based PHD behavioral model is able to reveal the
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characteristics under the nonlinear operation. Especially for the breakdown regime, the PHD approach is an accurate large signal modeling methodology due to the XT term included at the high input power [12]. The measured magnitude of XT22 can be larger than the value of XS22 as VDS exceeds 2.2 V from the X-parameters for the single MOSFET used in the presented PA. This shows that the XT terms are significant at breakdown and have to be considered [12,19]. Based on the measured X-parameter model of the single MOSFET, the results of this presented three-stage cascaded PA in which the multiple MOSFETs connected in cascade are valid due to the XS and XT terms considered by this novel X-parameter technique. To further validate the accuracy of the PHD model at breakdown, the measured load-pull contour for the single MOSFET is compared with the simulated results from PHD model at VGS ¼ 1.2 V and VDS ¼2.2 V as shown in Fig. 2(b). Good agreement between measured and simulated results is obtained. It is demonstrated that the PHD model of the single MOSFET can simulate accurate large signal power performance in the breakdown region. The PHD behavioral model of the single MOSFET is implemented in the circuit to analyze the large signal characteristics and to design the presented PA. When compared with the compact model, the development time of the behavioral model is shorter [21]. In addition, the real large signal characteristics can be directly captured by the behavioral model. The dynamic load line obtained from PHD model is shown in Fig. 2(a). It is observed even when the load line exceeds the RF breakdown voltage, the compression is not significant due to the nonlinear cancellation between breakdown inductance and transconductance. Therefore, the upper edge of the waveform of the power cell can be swept from 0 to 3 V safely as shown in Fig. 2(c). For the lower edge, because the allowable operating range at breakdown is enlarged, the waveform shown in Fig. 2(c) can sweep to 2.5 V. Both the OP1 dB measurement and PHD simulation results have demonstrated the feasibility of breakdown operation. Therefore, the large allowable voltage operating range in the presented PA can be obtained. In Fig. 2(d), the simulated large signal voltage waveform of the power cell from PHD is shown as the input signal contains the harmonics from the last stage. The clipped waveform at the lower edge due to the knee voltage is characterized accurately by the PHD model. The X-parameters can predict the nonlinear behavior more accurately in the breakdown and knee voltage regions due to the XT term included [12]. In addition, when the PA is driven into large signal operation, harmonic signals are generated from the transistors. Because the X-parameters can describe the response of the multi-harmonic input [12], the power performance of the cascaded PA can be accurately obtained by using the PHD model. The PA is composed of three stages including two driver stages and one power stage operating in the breakdown region as shown in Fig. 1. Because the avalanche breakdown of the MOSFET occurs in the drain junction [16], the presented CMOS PA is designed in CS configuration to drive the power cells into the breakdown regime for increasing the output power. The balun is employed to transform the single-ended signal to the differential signal. The RF signal is amplified by two driver stages and then delivered to the power stage. The power stage consists of several power cells to increase the output power. The inter-stage matching is made with a highpass LC network as shown in Fig. 1. Inductor in the interstage matching network acts as a RF choke and as an impedance matching element at the same time. Capacitor can be used as a DC blocking and as an impedance matching element simultaneously. Therefore, this high pass LC network is selected as the inter-stage matching because it can incorporate both DC biasing and impedance matching. To combine the power delivered from the power cells, a transformer at the output is designed. The bias point of the driver stage is at VGS ¼ 1.2 V and VDS ¼ 1.8 V, and the gate width is
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C.-I. Lee et al. / Microelectronics Journal 45 (2014) 449–453
Table 1 This work performance and comparison with other CMOS PAs. Technology This work [1] [2] [3] a b
CMOS CMOS CMOS CMOS
0.18 μm 0.18 μm 0.18 μm 0.13 μm
Frequency [GHz]
Power gain [dB]
OP1dB [dBm]
Power consumption [W]
PAE [%]
FOMa [104 mW GHz2]
2.4 (2.3–2.5) 1b 2.4 (2.3–2.5) 2.4 (2.3–2.5)
38.3 25 12.5 17
30.2 29 23 19
4.35 3.9 0.41 0.14
34.1 36 46 57
1391 9 1 1.3
FOM ¼ OP1dB Gain PAE frequency2. Bandwidth is not provided.
7 8 15 μm3. The higher gate voltage is designed to increase the gain. The power consumption of the drive stages is 0.13 W. The power stage is biased in class AB to increase the efficiency, and the bias point is at VGS ¼ 0.8 V and VDS ¼ 2.2 V in the breakdown region. The gate width of the power stage is 60 8 15 μm3. The power consumption of the power stage is 4.22 W. Therefore, the total power consumption of the presented PA is about 4.35 W as shown in Table 1.
3. Results and discussion Fig. 1(a) shows the schematic of the presented CMOS PA. The die area is 1 2 mm2 including RF pads as shown in Fig. 1(b). The supply voltage of the power cell shown in Fig. 1 is increased to the breakdown region to obtain higher output power and PAE. The measurement based PHD model of the single MOSFET is extracted from X-parameters through Agilent N5242A PNA-X microwave network analyzer. With the aid of PHD model which has been verified by load-pull data as shown in Fig. 2(b), the real power performances of the PA operating in the breakdown regime can be revealed accurately. The post-layout simulation results of the presented PA are shown in Fig. 3. The results of the presented CMOS PA is reliable because the validity of the X-parameter model has been verified in the circuit level design as in [13]. The linear power gain is 38.3 dB, the OP1 dB is 30.2 dBm, and the PAE is 34.1% at breakdown as shown in Fig. 3. The OP1 dB can evaluate linearity of PA. The bandwidth of the PA is about 200 MHz. The better power performances at VDD of 2.2 V are observed when compared with the results at VDD of 1.8 V. The results indicate that the power performances can be improved by operating in the breakdown regime. The presented PA has a simpler CS transistor core circuit when compared with the SiGe cascode PA using two HBTs in CE and CB configurations [9]. The results are also compared with the published CMOS PAs as shown in Table 1 and high figure-of-merit (FOM) including the DC power consumption, OP1 dB, gain, and efficiency information at the operating frequency is achieved [22,23]. The long term measurement was conducted to test the reliability of the MOSFET used in the presented PA in the breakdown region. The DC stress was set in the breakdown region of VGS ¼0.8 V, VDS ¼2.2 V and saturation region of VGS ¼1.2 V, VDS ¼1.8 V as in the PA. The DC stress was applied to the MOSFET continuously for about 1000 s which is the same as the stress time reported in [24]. According to the measured results, we found that stress does not degrade output power over 0.5 dBm after 1000 s. Because the oxide thickness of the standard 0.18 μm MOSFET used is higher than 3 nm, degradation due to reliability is insignificant in the presented work. (Performance degradation may take place if the oxide thickness is lower than 3 nm [24].) In [25], it also indicates that the reliability of the PA can be kept when device degradation is insignificant. Therefore, the used single MOSFET which can operate continuously for large time intervals in the breakdown region can be utilized to construct a reliable PA.
Fig. 3. The performances of the presented CMOS PA from the PHD model including XS and XT terms at 2.4 GHz. The results at VDD of 2.2 V (solid line) and 1.8 V (dash line) are shown. The curves marked by squares, circles, and triangles depict the power gain, output power, and PAE, respectively.
Table 2 Performances at different VDD of power stage. Other bias conditions remain the same. PHD model VDD (V)
Gain (dB)
Pout (dBm)
OP1 dB (dBm)
PAE (%)
1.8 2.2
37.4 38.3
28.8 32
27.4 30.2
21.3 34.1
Fig. 4. The voltage waveform of the presented CMOS PA from the PHD model at the output from 20 to 0 dBm with 10 dBm step.
When the power stage is driven in the saturation regime, the maximum output power and PAE are 28.8 dBm and 21.3%, respectively, which are lower than the results at breakdown as shown in
C.-I. Lee et al. / Microelectronics Journal 45 (2014) 449–453
Fig. 3 and Table 2. This is because the lower VDD results in smaller allowable output voltage swing when compared with the results at breakdown. In addition, the power gain under the breakdown operating condition is improved. The PAE is higher in the breakdown region because the PAE can increase with the supply voltage [9] although the power consumption increases. The FOM of the PA designed to operate in the breakdown regime is 1391 104. The results from the accurate PHD model shown in Figs. 3 and 4 and Table 2 have demonstrated the circuit performances can be improved by operating in the breakdown operation in CMOS technology. 4. Conclusion In this paper, a CMOS PA operating in the inductive breakdown region is designed to obtain high output power and PAE for the first time. The upper edge of the output voltage waveform is not compressed in the breakdown regime because our Volterra analysis indicates the nonlinear breakdown inductance cancels the nonlinear transconductance. The VDD of the power cell increases from 1.8 V to 2.2 V and then the output power and PAE of the whole PA are raised by 3.2 dB and 12.8%, respectively. Based on the X-parameter measurement based PHD model which has been verified by the load-pull data, the OP1 dB and PAE at breakdown are 30.2 dBm and 34.1% at 2.4 GHz, respectively. When comparing with the published CMOS PA, the high FOM of the presented PA is achieved. Therefore, the results of the PA based on the PHD model demonstrate the power performance improvement by operating in the breakdown region. Acknowledgments The authors would like to thank National Chip Implementation Center (CIC), Hsinchu, Taiwan for TSMC design kits, the National Nano Device Laboratories (NDL) for the X-parameter measurement support, and the Wireless Communication Antenna Research Center, Kaohsiung, Taiwan for the support. This work is also supported in part by the National Science Council of Taiwan under Grants NSC101-2221-E-110-077 and NSC100-2221-E-110-085. References [1] D. Tavakolifar, J. Javidan, Design of compact transformer-type power combiner for watt-level PA in CMOS technology, Int. J. Eng. Res. Appl. 2 (2) (2012) 313–321.
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