A compact model for the grounded-gate nMOS transistor behaviour under CDM ESD stress

Journal of

ELECTROSTATICS ELSEVIER

Journal of Electrostatics 42 (1998) 351-381

A compact model for the grounded-gate nMOS transistor behaviour under CDM ESD stress 1 Christian Russ a'*, Koen Verhaege a'b, Karlheinz Bock a, Philippe J. Roussel a, G u i d o G r o e s e n e k e n a, H e r m a n E. M a e s a alMEC, Kapeldreef 75, B-3001 Leuven, Belgium bSarnoff Corporation, CN5300, Princeton, NJ 08543-5300, USA

Received 21 November 1996; received in revised form 10 July 1997; accepted 15 July 1997

Abstract The parasitic bipolar transistor inherent to grounded gate nMOS transistors is modelled, accounting for the specific conditions applied by CDM ESD stress. The avalanching of both, drain and source, the triggering of snapback and the CDM-specific bipolar saturation mode are addressed. Furthermore, a fast analytical method to determine CDM ESD lumped tester parasitics from measured pulse characteristics is presented. The triggering of the grounded gate nMOS transistor under CDM is studied in detail for different gate lengths. The optimal gate length for CDM protection in advanced submicron technologies is discussed. © 1998 Elsevier Science B.V. Keywords." ESD protection; CDM; Compact model; Circuit simulation

O. Introduction For the full on-chip protection of an integrated circuit against Charged Device Model (CDM) ESD stress m a n y aspects have to be considered: operation of the single devices of a protection scheme, the overall protection concept including supply busses, the package type, pin count and die size [1-3]. The internal core circuitry also has a very strong influence [4, 5]. For product qualification in industry C D M ESD stress and its various aspects may not be neglected! However, today there is still insufficient understanding of the operation of single protection devices under C D M ESD stress [6] (Fig. 1). One of the most widely used

*Corresponding author: Tel.: + + 32 16 281 300; fax: + + 32 16 281 501; e-mail: [email protected]. 1© 1996. Reprinted with permission, after revision, from Electrical Overstress/ElectrostaticDischarge Symposium Proceedings, LOS-18, Orlando, FL, USA, September 10-12, 1996. 0304-3886/98/$19.00 © 1998 Elsevier Science B.V. All rights reserved. PII S 0 3 0 4 - 3 8 8 6 ( 9 7 ) 0 0 1 62-9

352

C. Russ et aL/Journal of Electrostatics 42 (1998) 351-381

Cback = Cdi e d- ~

Cpini i

Fig. 1. CDM ESD stress applied to a single gg-nMOSt. The discharge is determined by the charge on the total background capacitance (Cback) and the parasitics in the discharge path (R, L).

devices in on-chip ESD protection is the grounded gate nMOS transistor (ggnMOSt). Questions on trigger timing issues and on CDM specific operating conditions of the gg-nMOSts are still open. Compact gg-nMOSt models for ESD presented in [7-12] allow thermal considerations [7-9] and describe snapback behaviour of the parasitic bipolar transistor according to [11, 13-19]. The models [7, 8, 12, 17] are mainly applied to Human Body Model (HBM) ESD or Electrical Overstress (EOS). However, they do not consider the specific nature of CDM current pulses, which can easily reach amplitudes of several amps within a nanosecond and which are most often accompanied by damped but fast oscillations. Studies of CDM related device phenomena or ESD trigger issues were made in [9, 10,20-22] by both device simulations and experiments. These device simulations give precise insight into the device's internal local variables such as the electric field or the current density. However, the drawback is a long calculation time which limits the variation of different device parameters and slows down the interaction with the user. Compact models used in a circuit simulator can give fast feedback to the (ESD) circuit designer. The minimum feature size in CMOS technologies determines, by the gate length, the bipolar base width of the gg-nMOSt utilised for ESD protection (Fig. 2). It is known that the shorter the base width of a bipolar transistor, the faster it will turn on [23]. The trend in minimal feature size down scaling might therefore be beneficial for proper ESD protection design in deep sub-micron technologies [6]. However, the different aspects of the gg-nMOSt responding to fast transients, sustaining the discharge current over the entire pulse duration and ensuring uniform current flow over the entire device width need to be discussed under the circumstances of CDM ESD stress.

C. Russ et al./Journal of Electrostatics 42 (1998) 351-381

353

gg-nMOSt source / emitter

drain collector

Fig. 2. Cross-section of a grounded gate nMOS transistor with its parasitic bipolar junction transistor.

L

Vdev1

R

VGDM

cback m

Fig. 3. The compact transistor model embedded in a 2nd-order (RLC) lumped element model for CDM ESD stress.

This paper presents a compact model for the gg-nMOSt accounting for the C D M relevant turn-on and turn-off and addresses the issues of clamping behaviour and power dissipation. The gg-nMOSt behaviour under C D M stress is studied by means of circuit simulation using a 2nd-order lumped element model for the C D M testers (Fig. 3). In Section 1 the principle of the compact transistor model is described. The requirements to treat the ESD-relevant and more specifically the CDM-relevant operation states are explained. Section 2 addresses the questions which arise when the two-dimensional nature of the real gg-nMOSt device structures is considered with respect to snapback turn-on time, pulse response time and turn-off delay time. A simple analytical method is introduced in Section 3 to extract equivalent RLClumped element parameters of measured C D M discharge pulses. The transistor model

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is employed to discuss the trigger timing and self-heating issues during CDM ESD stress (Section 4).

1. Compact transistor model 1.1. Equivalent circuit o f the transistor model

A compact transistor model is employed in a mixed technology circuit simulator [24] and this allows both electrical and thermal considerations [7, 8]. The oscillating nature of CDM pulses demands a basically symmetrical model for the intrinsic transistor. The model, based on the 'zr-form' of a modified transport version EbersMoll-model [25, 26] is presented in Fig. 4. The transport current Ix is given by Iv = Ice - Iec

(1.1)

with the non-multiplied collector current Ice = Ise{exp(Vb~/Uv) --

1}

(1.2)

and the emitter current I¢c= Is,{exp(-

V,b/UT) --

1}

(1.3)

Isc and Ise are the reverse saturation currents of the base-collector and base-emitter pn-junction, UT is the thermal voltage.

collector (drain) Vdev

l ldev

CdbcT CjbcT

±

Ib~c]

Ia!c+~ Vcb

Rbi _,

IVbi

±

ICdbeTCjbe T Ibell ~hIi~-'-~ lave'[ *Vbe

?..

,v.

emitter (source) Fig. 4. The compacttransistor model accountingfor CDM ESD stress.

C. Russ et al./Journal o f Electrostatics 42 (1998) 351-381

The ideal base current components lbe = Ice~fit

and

/be

355

and Ibc are now given by

Ibc = Ice~fir

(1.4)

where flf is the forward and fir the reverse current gain. The transistor model accounts for snapback caused by the avalanching collectorbase pn-junction [13, 11]. Additionally, avalanching and (reverse) snapback at the emitter-base pn-junction is considered due to the fact that during CDM stress the voltage across and the current through the transistor change polarities. Hence, avalanche sources law and Iave are introduced at both, collector and emitter side described by lave = I T ( M e - -

1) and

I,ve = -- I T ( M e -- 1)

(1.5)

with the avalanche multiplication factors Mc and M~ 1 \ gbc0 /

1 \gbe0/

In order to keep the model at a limited level of complexity, non-ideal base currents have been neglected. Because of the symmetry of the lateral bipolar structure in the gg-nMOSt, we can assume that the junction breakdown voltages satisfy Vb~o= Vbeo and further we take/~f =/~r. For the stress polarity considered in this work 'substrate negative', the predominantly acting part of the device is the symmetrical bipolar structure under the MOS gate and next to the junction side walls. Therefore, the reverse saturation currents Is~ and lse are assumed to be equal. However, it should not be overlooked that for the stress polarity 'substrate positive', the current distribution is significantly changed [20]. Then, the lateral extensions of the collector (drain) and emitter (source)junction areas which are typically different for ESD structures have to be considered. Time delays due to the drift of the avalanche generated carriers travelling to the border of the depletion layer and also the time delay introduced by the holes injected by the avalanche current in the p-substrate and flowing to the substrate contact are in the order of 10 and 5 psec, respectively [-27]. Hence, they can be neglected compared to the by far predominating time delay of the buildup of the diffusion charge by electrons injected from the positively biased emitter to the base region. Therefore, the principal dynamic behaviour is modelled by both, the non-linear junction and diffusion capacitances. The forward and reverse transit times tf and t r can be calculated under low bias conditions as t f = t r -~ L Z / 2 D , .

(1.7)

Accounting for high current injection conditions under ESD this becomes tf = tr = L 2 / 4 D .

(1.8)

C. Russ et al./Journal of Electrostatics 42 (1998) 351-381

356

Table 1 Ideal forward transit time for different gate lengths Gate length L (= bipolar base width) (I.tm)

Ideal bipolar base transit time

0.25 0.5 1.0 2.0 4.0 8.0

16 ps 63 ps 250 ps 1.0 ns 4.0 ns 16 ns

due to the electric field in the base region enhancing the diffusion of the minority carriers to the collector by drift [11, 27-29]. The gate length L and base width WB of the parasitic bipolar transistor are identical. D, is the diffusion constant for electrons in the base region. Typical values for D, are found or can be derived from literature: 34.7 cm2/s given for instance in [30, 31] for intrinsic silicon at room temperature by solving the Einstein relationship D, = kT/epn and applied to ESD by [12]. However, the electron mobility/~, is depending on doping, minority carrier concentration, field and temperature and therefore will deviate for ESD-related high current conditions. A more pessimistic but probably better estimation was used by [27,29] with D, = 10 cm2/s. Evaluating Eq. (1.8) with D, = 10 cmZ/s for different gate lengths yields an ideal forward transit time (Table 1). The charge of the diffusion capacitances Cdb¢ and Cdbe can now be described by Qdbe = Icetf

and

Qdbc= le¢tr

(1.9)

where tf and tr are assumed to be identical as the transistor structure is lateral and hence symmetrical. These bipolar transit times are found to dominate the turn-on time of the protection device [27]. The charge storage in the pn-junctions is described by the junction capacitances Cjb c and Cjbe, respectively depending non-linearly on the voltages Fbe and Vbc [28] and accounts for dV/dt supported triggering of the gg-nMOSt [8]. The intrinsic base resistor Rbi [32, 10] is modelled non-linearly depending on the injected charge. It was reported that this is crucial for CDM events in transistors with larger gate lengths [10]. Following the symmetrical approach, both junctions (drain and source side) are considered for the injection of minority carriers into the base region and for the evaluation of Rbi by Rbi = Rsh

L W

1 1+

Qdbe q- Qdbc

(1.10)

Qbo

where Rsh is the sheet resistance of the base region and Qbo is the zero bias base charge.

C Russ et aL/Journal of Electrostatics 42 (1998) 351-381

heat ~ so,oe \

Rth Rth ~'~-[~

357

Rth - -!-[~300K

TTT T

Fig. 5. Compact thermal modelling of the gg-nMOSt considers the heat dissipation in the areas with the highest power densities. The cross-sections of the intrinsically heated volumes are represented by areaequivalent half cylinders.

The base node is connected to the substrate contact via the extrinsic base resistance Rb. The collector and emitter series resistances (R~ + Re = Rdev) of the extrinsic gg-nMOSt are extracted under high current conditions by transmission line pulse testing [33]. 1.2. Thermal model

Self-heating in the transistor is considered by the power dissipated in the basecollector and base-emitter junctions and in the series resistances Rc and Re (Fig. 5). The highest amount of power is observed in the base-collector junction, due to avalanching or snapback mode 1-34]. A thermal network is connected to each heat source. This 2D half-cylindrical thermal model consists o f concentric layers each represented by a lumped thermal capacitor and a non-linearly temperature-dependent thermal resistor [-8]. The intrinsically heated volume is modelled by the thermal capacitance of a half cylinder whose radius equals the junction depth xj (typically 0.2 txm). The thickness of the surrounding first layer is 0.05 ~tm (radius = 0.25 ~tm). This increases exponentially towards the outer layers. The obtained thermal time constants are appropriate to calculate responses in the CDM time domain as well as in much slower time domains 1-35]. This model yields effective temperatures in silicon, which provides a good estimation for comparisons, but does not account for 3D effects. Other sites of high power dissipation are the series resistances Rc and Re, where a major voltage drop occurs during the high CDM currents. The thermal model for this is similar to the one used for junction heating. The 2D cross-section of the intrinsically heated volume - here assumed to be the n ÷ layer of the drain or the source of the gg-nMOSt - is represented by an area-equivalent half cylinder. Heat

358

C. Russ et aL/Journal of Electrostatics 42 (1998) 351-381

diffusion next to the heat source is again treated by thermal resistors and capacitors in a concentric scheme. Due to the relatively large lateral dimensions of the drain and source regions of some ktm, mutual thermal diffusion between the different heat sources might not be very significant in this case. For instance, the typical thermal diffusion length in a reverse biased junction due to a H u m a n Body Model ESD pulse with a characteristic time constant of 150 ns was shown to be in the order of 3 lam [3, 36]. Hence, thermal coupling between the heat dissipation in the junctions and in the resistive components is not implemented in this first-order approach for temperature estimation. Furthermore, heat dissipation from the silicon surface to the top, heat convection and heat radiation are neglected.

2. Triggering of a gg-nMOSt structure In this section, the trigger behaviour of gg-nMOSts with a typical gate length of L = 0.5 ~tm and a width of W = 150 ~tm is being analysed by circuit simulation under the application of various transient supplies. The characteristic on-resistance of the device is Rdov ~ 4.5 ~.

2.1. Step response of the gg-nMOSt 2.1.1. Snapback effect A current pulse of Idev ~' 0.5 A with a nearly ideal rise time of 1 ps simulated by a voltage pulse of 500 V and a series resistance of 1 kf~ is applied to the gg-nMOSt to study its step response (Fig. 6). The device is almost immediately forced into avalanche conduction at the base-collector junction. The well-known snapback effect occurs: Vcb decays to Vh due to the positive feedback caused by the internal current gain of the bipolar transistor. In the same amount as the avalanche current decreases, the collector current Ic¢ without avalanche multiplication increases until the transistor has reached a steady-state condition where only a reduced avalanche current is required to sustain the full current flow in the device. In distinction to the collectorbase voltage V~b, the device terminal voltage Vdev is always higher due to the base-emitter junction which has to be forward biased and due to the voltage drop across Rdev. In the current case of a step response, we observe an almost linear shift between V~b and Vary. 2.1.2. Definition and discussion of a turn-on time for the step response Precise definitions of turn-on times for ESD protection devices are still lacking. A definition by the device internal currents Iavc and Ic~ does not seem promising as they cannot be distinguished externally (by measurement). Therefore, we will define a turn-on time ton for the step response by the 90-10% fall time of the voltage difference AV between the snapback trigger voltage Vtl and the sustaining voltage Vsustain. This is only applicable to the step response of the

C. Russ et al./Journal of Electrostatics 42 (1998) 351-381

, 0.6 - '

359

Idev lavc

.....

Ice

, , , i ~

q

0.5 0.4

~

x ,. ,'" , " "

0.3

0.2 E-

,"'

0.1 0 16 14 12

>1o ~ 8

~

R s = 1 k,Q [~RClcc v, = soov I1

"-.': '0'o01Z' H ( ' ' I '~--'~-T

- ~

~

1 .0,v=Ro+Ro

~~-~-

9°°/°'vTAV

V

K ":°~ F"--~--_._~'v ~

-_

%,,,,°

~ ~

V h

~

>

4 2 0

•• 0

on

:

~,. 0.5

i : -. .-._. .- : _ v c bVcb J= 1

1.5

2

time (nsec)

Fig. 6. Step response (pulse parameters: Vs = 500V, t,~s¢= 1 ps, R, = 1000~) of the gg-nMOSt (L = 0.5 I~m,fit = 8, tf = 200 ps, Rdev~- Rc + Re = 4.5 f~) and definition of step response snapback turn-on times to, and %.. Loading of the junction capacitance, dV/dt related triggering (see Section 2.3) and a voltage drop across the intrinsic base resistance Rbi are neglected here.

g g - n M O S t as to. occurs intrinsically at the v o l t a g e difference AV~b = V~bo - V h a n d as there is a linear shift of Vcb to Vaev. Alternatively, i n s t e a d of to,, the 1/e decay ton of AVCb (or AV) can be used when p r a c t i c a l l y required. T h e y are related as to, = %, In 9.

(2.1)

F r o m Fig. 6 we o b t a i n a step r e s p o n s e t u r n - o n time to, = 588 ps a n d %, = 268 ps for a f o r w a r d transit time used for this t r a n s i s t o r of t f - - - 2 0 0 ps. It can be a l r e a d y c o n c l u d e d here, t h a t i n d e e d the f o r w a r d transit time is d o m i n a t i n g the t u r n - o n b e h a v i o u r . A d e t a i l e d analysis of this issue follows in Sections 2.5-2.7.

2.2. CDM ESD relevant trigger response o f the gg-nMOSt 2.2,1. CDM ESD relevant operation states In Fig. 7 a c u r r e n t pulse of Idev ~ 85 m A , s i m u l a t e d by a v o l t a g e pulse of 50 V a n d a series resistance of 500 £~, is a p p l i e d to the device (a similar scheme is used as in the inset of Fig. 6, top). T h e v o l t a g e rise time of 500 ps used n o w is in the o r d e r of C D M

360

C. Russ et al./Journal o f Electrostatics 42 (1998) 351-381 o.1 o.o 0.0

*~ o.o o o.o

-0.0

1E 14

>1c 0

4

C 0

0.5

1 time (nsec)

1.5

2

Fig. 7. Analysis of the different operation states leading to turn on the gg-nMOSt (transistor parameters as before, pulse parameters with respect to the scheme depicted in the inset of Fig. 6: E, = 50 V, tri~,e= 500 ps, Rs = 500 fl). When the breakdown voltage is reached the device starts avalanching, the device voltage decreases while the current still increases. From a constant current on, the device shows a turn-on behaviour as demonstrated for the ideal step response in Fig. 6. pulse rise times. A d i s t i n c t i o n b e c o m e s evident between the following 4 o p e r a t i o n states: 1. T h e b a s e - c o l l e c t o r j u n c t i o n c a p a c i t a n c e Cjbc is charged. B o t h voltages, Vdev a n d Vcb are rising s i m u l t a n e o u s l y b e c a u s e there is only a very small voltage d r o p across Rdev. T h e fast v o l t a g e t r a n s i e n t of the pulse leads to the d i s p l a c e m e n t c u r r e n t lj~b in the j u n c t i o n . T h e injected holes c h a r g e the intrinsic base region a n d the s u b s t r a t e positive a n d can thus s u p p o r t b i p o l a r triggering. 2. A t the a v a l a n c h e b r e a k d o w n v o l t a g e Vcb0, the c o l l e c t o r - b a s e voltage V¢b starts to d r o p . T h e o c c u r r e n c e of s n a p b a c k is visible in a d r o p of the device voltage, too. T h e

C. Russ et al./Journal of Electrostatics 42 (1998) 351-381

16

'

'

' ~-I

14

....

I

'

'--~-~'

'

1

V

12

=o >

'

361

l/e &v'

6

V .....

0.4

..........

/

4

2

' ~ _ k 0

"~

-[ 100/0 Vsust/i ~ I

L

~

~ ~

0.5

0 1.5

2

time (nsec)

Fig. 8. Contrary to Fig. 7, a high current of ~0.8 A is forced here (V, = 50 V, R, = 50 f2), the rise time is again 500 ps. The device voltage is - during avalanche breakdown continuously rising due to the voltage drop across Rc and Re while the internal V~balready starts to drop. By means of the externally accessible device voltage, a definition for the complete response time of the device is proposed for switching behaviour under ESD-like conditions.

current in the device is n o w conducted by the collector-base avalanche current /ave and by the increasing contribution of the non-multiplied part of the collector current Ice. Both currents are increasing as the total current forced t h r o u g h the device is still increasing. 3. In the d o m a i n of the nearly constant current, the voltages Vd~v and V~b continue to decrease as in Fig. 6. C o m p a r e d to Fig. 6, the difference between Vdev and V~b is smaller. This is obvious because this difference contains the resistive d r o p across Rat,,. The latter is smaller as the current is smaller (85 vs. 500 mA), 4. Stable values of V,lev and Vcb are reached, the bipolar action is fully established.

2.2.2. Definition and discussion of trigger response times A distinction has to be made between the intrinsic turn-on time ton for the step response of the device and the entire response time tresp.... when subjected to an ESD-like pulse, The ton shall be mainly used for simulation studies, whereas the response time is also targeted for applications in measurements. The total response time of the device subjected to a pulse with a non-zero rise time can be a p p r o x i m a t e d as tresp . . . . ~ tdisp "4- tav a -~ "Con

where/,lisp

(2.2)

is the time duration of the displacement current IjCb until the device reaches the avalanche breakdown, tara is the time for an increasing avalanche current and ~'o, describes the 1/e decay time of the s n a p b a c k of Vdev with respect to the decreasing avalanche current (Idev ~ constant). The definition of a response time under high ESD-like current is depicted in Fig. 8. A 500 ps rise time pulse with a maximal current of ~ 0.8 A is forced t h r o u g h the

362

C. Russ et al./Journal

of Electrostatics

42 (1998) 351-381

device. As there is now the drop across R dev superposing the on-set of snapback, the maximum voltage occurring due to the increasing current is now taken for the definition of the turn-on response time. 2.3. Effective junction

capacitance

and its influence on d V/dt-triggering

The displacement current in the base-collector junction capacitance Cjbc results in the injection of holes, positively charging the intrinsic base region of the transistor and the substrate. This can lead to a triggering of the bipolar transistor and is for instance known for the silicon controlled rectifier [23]. This is called dV/dt triggering and is found also for ESD protection transistors [S, 9,37,22]. It leads to a reduced trigger voltage because the device does not have to go deep into avalanche breakdown anymore to supply sufficient carriers establishing bipolar action. However, when considering the shape of the base-collector junction in a lateral gg-nMOSt, it is likely that not the entire junction will provide carriers for the active base region of the parasitic bipolar under the MOS gate (Fig. 9). A fraction of the injected carriers will charge the substrate under the plain collector/drain area. This part will mainly contribute to a capacitive damping of the pulse applied to the device. To study and to model the dV/dt-efficiency of the device, the junction capacitance Cjbc is split up in an effectively active junction capacitance XCjbc and in an ineffective capacitance (1 - x)Cjac (where 0 < x < 1). The displacement currents are called Zj,-becand Zj,-bif, respectively. In an MOS device, XCjbc can be approximately related to the junction sidewall capacitance and (1 - x)Cjbc to the junction bottom capacitance. However, a precise analysis to determine the fraction of the effective charge would require 2D transient device simulations. For the scope of this work, we will focus on a demonstration of the influence on triggering. The effect of the dV/dt triggering is shown in Fig. 10. The displacement current in the effective junction capacitance increases with the ratio x. For x = 0.5 and 0.9, the collector-base voltage V,, does not reach the breakdown value V,,, anymore and thus the snapback trigger voltage is lowered.

Q emitter

collector 9

intriniic base

substrate

Fig. 9. Cross-section of the transistor structure distinguishing between the junction capacitance xCjbc effectively contributing to the base charge of the intrinsic transistor and the ineffective (1 - x)Cjbs where the charge is injected into the substrate.

C. Russ et al./Journal of Electrostatics 42 (1998) 351-381

363

> >

o

6 4 2

I f . . . . . . . . . x=o.5 /-~ i ..... x=o~ j_~ .

,", ,;'

0

, 0

~ I , 0.5

~ ~ i

2~

time

20~1

v

I 1

.

i

.

i

.

J 1.5

~ 2

(nsec)

," \

.~

[ "", .

O~

.

.

.

.

.

.

.

.

.

L '. ~..&......_T. :..~_- . . . .

0

0.5

X=0.5

:

t

1

1,5

time (nsec)

Fig. 10. dV/dt-trigger behaviour. A transition from avalanche triggering to dV/dt triggering is evident when the ratio x between the effective and the total junction capacitance is accounted for. The trigger voltage decreases due to carriers injected by a displacement current in the base region (transistor parameters: zero bias junction capacitance 0.8 fF/gm z, L = 0.5 lam, flf = 8, tf = 200 ps), pulse parameters: V~= 50 V, t,i~ = 500 ps, R, = 500 f~).

12

q

~ ~

~

I ~ >

8 , o

-

: -

2

0

,, 0

-

......... . . . . . . . . . .

i~:J

k , 2

, L , L, 4 6 time (nsec)

trise = 5nsec

trise = 2.Snsec trise =lnsec trise = 500psec

,,

I

8

,~_fl

10

Fig. 11, Fast rise time pulses cause a lowering of the snapback trigger voltage due to the effect (transistor and pulse parameters as in Fig. 10).

dV/dt triggering

T h e rise t i m e of the p u l s e c a n also s t i m u l a t e dV/dt triggering. R e f e r r i n g to Fig. 11, the rise t i m e s of the p u l s e s a r e v a r i e d f r o m 5 n s to 500 ps, l e a d i n g to dV/dt slopes of Vs f r o m 10 to 100 V/ns. T h e l o w e r i n g of the s n a p b a c k trigger v o l t a g e is also e v i d e n t here. F u r t h e r m o r e , t w o effects c a n be seen f r o m Fig. 11. First, there is a k i n d of s a t u r a t i o n in l o w e r i n g of the trigger v o l t a g e at the very fast rise t i m e pulses (trise = 1 ns a n d 500 ps),

C. Russ et aL/Journal of Electrostatics 42 (1998) 351-381

364

which could be considered as reduced effectiveness of the expected dV/dt triggering (the dV/dt trigger voltage can be lowered at maximum to Vh [8]). However, there is also a shortening of the turn-on time visible for the fast transient pulses. Compared to Fig. 7, it can be concluded that the time duration tara (avalanching while increasing Idev) shortens the entire response time and might therefore be beneficial for the trigger behaviour of the device.

2.4. Avalanche breakdown The location of avalanche breakdown in a gg-nMOSt manufactured in a 0.5 tam C M O S technology was studied by means of Emission Microscopy (EMMI) under DC conditions [38]. Almost uniform light emission was visible along the entire gate edge of the collector (drain) junction just before the device was triggered into snapback. The emission is consequently originated in the cylindrically shaped part of the junction, located next to the intrinsic base region (see also Fig. 9). However, no emission was observed at the bottom of the collector (drain) area. For the 2D considerations made in this paper, this leads to the conclusion that almost all carriers generated by impact ionisation contribute to the base current in the intrinsic base. Only a slight preference for avalanche was seen for spherical pn-junctions as they occur in a 3D structure in the corners ofpoly-to-LOCOS overlap and in the corners of the active area. The consequence for the equivalent circuit transistor model is that the avalanche s o u r c e s lay c and lav e do not have to be split up in a way as it was done for the junction capacitances.

2.5. Effective diffusion capacitance Krieger [27] discussed the influence of the lateral and the vertical region of the emitter/source of the gg-nMOSt. Only the part next to the intrinsic base region of the forward biased emitter can emit electrons which will enhance for bipolar action. The bottom part of the j unction injects electrons as stray charge in the substrate which will not actively contribute to the turn-on. Thus, the effective transit forward time of the real device is larger than in the ideal case. Both are linked by a fitting factor K estimating the slowed down turn-on by an increased transit time t~ as given in /'; ~--- t f g

= ~

-~- S S

xj /

(2.3)

K is determined by the source geometry with SX being the lateral dimension of the source and xj the junction depth (Fig. 9). It is based on an estimation of the ratio of electron injection into the base region and the stray electron injection under the bottom of the emitter. For the investigated device structures SX was approximately 5 ~tm and xj = 0.2 ~tm. These relatively large values for SX (larger than the minimum non-ESD design rule) are quite common in ESD protection structures as the spacing between the gate edge and the contact (or the silicided region of the junction) increases SX. This geometry would yield K = 26 for the L = 0.5 ~tm transistor and hence

365

C. Russ et al./Journal of Electrostatics 42 (1998) 351-381

Table 2 Overviewof the different transistor parameters used for the simulation study and the resulting turn-on time to, of snapback and the turn-offdelay toff Gate length Bipolarcurrent L (= bipolar gainbf base width) (lain)

Idealbipolar base transit time (as given in Table 1)

Bipolarbase Snapback transit time turn-ontime t~ used for to. obtained simulations from simulations

Turn-off delay time toff obtained from simulations(ns)

0.25 0.5 1.0 2.0 4.0 8.0

16 ps 63 ps 250 ps 1.0 ns 4.0 ns 16 ns

50 ps 200 ps 800 ps 3.2 ns 12.8 ns 51.2 ns

1.43 3.24 6.76 13.4 28.3 57.1

16 8 4 2 1 0.5

177 ps 588 ps 1.89 ns 5.73 ns 16.0 ns 40.7 ns

t~ = 1.64 ns. However, various experimental tests performed on the C D M ESD performance of single gg-nMOSt (L = 0.5 gm) and following failure mode analysis revealed that these transistors turn on during a non-socketed C D M event with a typical length of the first current pulse of less than 1 ns. The failure mode analysis showed a failure signature indicating uniform current flow in the device at the drain contact - and not at the collector-base junction [39]. Hence simulation suggests that the transit time and consequently the turn-on time of that device was short enough to bring the collector-base voltage out of the highly energy dissipating avalanche regime. A rigorous two-dimensional treatment of the stray charge distribution under C D M ESD was suggested by [27]. It was found by device simulations in [20] that the current distribution for the C D M precharge polarity 'substrate negative' (considered also in the current paper) shows a major lateral current flow. Although part of the current leaves the emitter area at the bottom, the emission of electrons contributing to the stray charge is significantly lower than assumed in [27]. Particularly, the contribution of the emitter part turned away from the intrinsic base region is much less pronounced. By graphically estimating the amount of emitter current in [20], we assume K ~ 3.2. In Table 2 an overview is given for the transistors. The current gain is based on typical values for lateral parasitic bipolar transistors [9, 10, 12, 32] and scaled for the different gate length according to [23]. The transit times are corrected by K = 3.2. From circuit simulations we obtained the turn-on times for the complete set of different transistors. It is evident that the smaller the bipolar base width the faster the snapback turn-on time ton. For current gains smaller than one (L = 8 gm), a turn-on time is obtained which is even shorter than the transit time. 2.6. Turn-off behaviour

In Fig. 12 the turn-off behaviour of the gg-nMOSt is shown. When the current through the device it turned off, the transistor is brought temporarily into saturation

C. Russ et al./Journal of Electrostatics 42 (1998) 351-381

366

12

....

; . . . . .

~

' I ....

_l 0.24

10 - - Q d b o l

8 >

q016

V

,

-t 0 1 2

6

\[

4 0 >

2

• v~

\

~ o

oo. o \l

r

40.04 ~

10% Qbo

~ ~"

0 , , J

-2 0

5

~ 10

0

. 0 15

4 20

time (nsec) Fig. 12. Turn-off b e h a v i o u r of the g g - n M O S t . At the time = I0 ns, the current is t u r n e d off. Both p n - j u n c t i o n s are f o r w a r d biased e x h i b i t i n g s a t u r a t i o n m o d e of the t r a n s i s t o r until the base c h a r g e is d r a i n e d a w a y after the turn-off delay t i m e toff (transistor parameters: Fig. 6, pulse parameters: tri*e = tra. = 10 ps, 1 A c o n s t a n t c u r r e n t forcing).

mode where both, the base-collector and the base-emitter junctions are forward biased. The turn-offdelay time toffis defined by the point where the diffusion charge in the base has decayed to 10% of its initial value Qab0. During the temporary saturation mode almost no voltage drop occurs between collector and emitter which results in very low internal impedance. The values of tofr are given in Table 2 for the different gate lengths and for an initial device current of 1 A. The turn-off time toff is depending on the initial amount of diffusion charge in the base Qabo and therefore on the device current and on the increased transit time t~. For the two-terminal snapback transistors where the intrinsic base is connected to emitter/substrate a dependence on the current gain flf is also found. Note that the turn-ofttimes torf are much larger than the turn-on times to,! As it will be discussed in Section 4, the low impedance state during the saturation mode will have a very strong impact on the C D M operation of the device. However, with respect to the prospected C D M performance of the transistors we can already conclude now from the observed turn-on and turn-off times: 1. The increased transit times can dramatically slow down the turn-on time which under C D M conditions becomes relevant. 2. The transistors are not as slow as they were expected under a worst case evaluation of K. 3. Short gate length transistors seem fast enough to respond under C D M ESD. 2. 7. Influence o f the current gain on the turn-on time

The snapback turn-on behaviour of the gg-nMOSt is investigated with respect to the influence of the bipolar current gain/?f inherent to the transistor. As the current gain is determined by the base and emitter doping levels, we keep the transit time (by

C. Russ et al./Journal of Electrostatics 42 (1998) 351-38l

367

14 13t

12

°i5

10 ~ >

8

>°

6

0.5 ],

it 2

4 2

~ l

0 0

~

2

0.158

~ -

~1~_

0.357--

8 I 0,2

I, =o.s.m l

o.58~

/ t = 0.2 nsec /

°~-

-

0,4

0,6

"

0,8

t i m e (nsec)

Fig. 13. Simulation study demonstrating the influence of the current gain flf on the snapback turn-on time ton. For an increased flf (transit time t} is kept constant) the turn-on time is increased (pulse parameters: V~ = 50 V, tris~ = 10 ps, R~ = 50 f2).

the gate length) of a given transistor constant and vary the current gain independently. The results in Fig. 13 reveal that the higher J3f the longer is the snapback turn-on time ton. As snapback of the parasitic bipolar is a positive feedback effect where the transistor is supplying itself the base current, there is consequently less internal base current occurring for a high fir. This means that it takes longer to provide the same required amount of base charge for turn-on at a high fir. Furthermore, also the holding voltage Vh is determined by the gain of that feedback loop. The higher/3f, the lower also the holding voltage and the larger AV. The results for the full transistor set (Table 2) are depicted in Fig. 14 showing a logarithmic dependence between the turn-on time ton and/3f. The original set for the inherent values of/~f are marked. The turn-on times to, obtained in Figs. 13 and 14 can be modelled by the following equation to, == to,[~_, (1 + Blnfif)

(2.4t

where to, l&_, is a constant depending proportionally on the transit forward time t'r, For the fitting factor B constant values of ~1.42 are obtained for all transistor lengths. The logarithmic influence of fir on the turn-on time is normally overlooked if only the pure length dependence of the transit time (Eq. (1.8)) on the turn-on time is considered. The consequences are: 1. The short gate length transistors, which exhibit a short transit time t} but a quite high current gain at the same time, cannot react as fast as it was expected from a pure estimation of t} only. 2. An increased current gain fif makes the device trigger slower into snapback mode but leads to a lower snapback holding voltage.

368

C. Russ et al./Journal of Electrostatics 42 (1998) 351-381

f 10 "6

"6' ,m.

•D • o × -....... + . . . . -- -~ .... - -,7---

transistors in table 2 L=O.25~tm astf=5Opsec L=O.5tam tf=2OOpsec L=lttrn tf=8OOpsec L=2,um tf=3.2nsec L=4pm tf=12.8nsec L=Spm ~

] /I ] [ [ /

r

f-r t

10 ~

~g E

10 .8

E

? E

~

lO-9

e~ c~ r- 10 1°

10-11

1

[

i

I

I I 1111___2_t~J

lO

forward current gain 13f Fig. 14. The logarithmic dependence between the snapback turn-on time ton and the bipolar current gain fir for different gate lengths L. Normally, flf of transistors in a certain technology is determined by the design parameter L and therefore fixed (marked transistors from Table 2). However, fir can also be changed by e.g. the base doping ( ~ p-well doping).

3. The absolute decay of V c b (Fig. 13) is larger at a given point in time and hence the amount of hazardous hot carriers from impact ionisation is reduced.

3. Characterisation of C D M E S D pulses

C D M ESD tester specification is done so far according to the C D M draft standard [40] and is based on the use of 4 and 30 pF discharge modules. However, knowledge on the shape of the current pulse measured with a real device is of great interest, because this can be related to the electrical behaviour of the device and the way it fails. Furthermore, a fit on pulses measured on real devices is necessary, as the devices define to a large extent the background capacitance Cb,ck [3,41, 42] (Figs. 1 and 3). Hence, we propose a very practical and easy-to-use method to derive values for lumped elements based on the most characteristic C D M waveform parameters (Fig. 15): the first (Ip0 and second (Ip2) current peak and the time (AT) in between or alternatively the duration of the first current peak (ATo). The C D M testers are modelled by a generic 2nd-order lumped element model which can be solved analytically for measured C D M pulses.

C Russ et al./Journal of Electrostatics 42 (1998) 351-381

369

The analytical solution of the differential equation for an R-L-C-oscillator results in the expression for the current given by for 0 < ~ < ~Oo ldev(t] = -VCI~M -

1

exp(- ~t)sin(~0

- ~2t)

[3.1a)

with c~-

Rto t 2L

and

~Oo=--

1

(3.1b)

For the given values of the precharge voltage VCOM,the current peaks (Ipl and lp2) and the time AT, Eq. (3.1) is solved for the element values of Rio,, L and Cback by (3.2)-(3.4). First, we get for the inductance L: L - Vc~M exp - - - /pl

arctan

r,

(3.2ai

7~

with lpt

K, = )-~p2 and

AT r = x/lnZ(Ki ) + n--5.

(3.2b)

Then, using the calculated values for L, K~ and r, the expressions for Rtot and Cb,ck are obtained by Rtot =

2L in Kl AT ' 1

Cback = --Z"2.

L

(3.3) (3.4)

All the required pulse parameters can be easily obtained from any current pulse measurement by simple graphical means. For a quick determination during the use of a C D M tester, the parameters can be read directly from a scope. However, one always has to be aware that any C D M pulse measurement can be distorted by the limited input bandwidth of the scope and the used current probe. In case of difficulties determining the time elapse AT between the current peaks l p l and Iv2, the time ATo from the start of the pulse until the first intersect with the time axis can be used as well, since it is mathematically proven from the analytical solution that AT = ATo. Therefore, the user is free to extract either the time AT or AT0 or their average from the measured data. For this paper, C D M waveforms were measured on a gg-nMOSt in a DIL-18 plastic package using a 1 G H z bandwidth scope (Tektronix SCD1000) and a 1 G H z current probe (Tektronix CT1). The s-CDM pulses showed only very little variations in the waveform of less than 2%. The uncertainty of the current measurement for n-CDM is not negligible due to the atmospheric conditions influencing the discharge spark. However, the variations found here were still less than 15%.

370

C. Russ et al,/Journal of Electrostatics 42 (1998) 351-381

Table 3 Values of the 2nd-order lumped element model values extracted for n - C D M and s - C D M pulses. The obtained model values can be considered as 'effective' parameters providing a description for C D M pulses C D M tester type n-CDM VCDM lpl lp2 AT L Riot = R + Re + Re

-- 500 V 4.97 A 2,71 A 0.895 ns 21.6 n H 29.2 f2

s-CDM -- 1100 V 4.78 A 1,20 A 2.98 ns 120 n H 111 f2

(Ro + Ro = 4.5 f2) Cb.ck

3.63 pF

6.28 pF

The obtained waveform parameters (VcDM,I p l , Iv2, A T ) are displayed in Table 3 for both, socketed (s-CDM) and a non-socketed (n-CDM). The determined element values are given in Table 3 and the resulting waveforms are plotted in Fig. 15. The value for the resistor R applied in the simulation has to be reduced by the value of the on-resistance of the device (Re + Re).

4. gg-nMOSts under CDM ESD stress for different gate lengths The gg-nMOS transistor model (Sections 1 and 2) is combined with the lumped element equivalent circuit (Section 3) in order to study their interaction (Fig. 3). The different transistor phenomena investigated in Sections 2.1-2.7 all have impact on the C D M behaviour of the gg-nMOSt. However, due to the oscillating nature of C D M pulses the different effects can appear superimposed and thus were considered separately. The focus is first put on the simulation of typical non-socketed CDM pulses using the lumped element parameter values from Table 3. The extension and discussion to socketed CDM pulses is then facilitated. 4.1. Electrical behaviour under n-CDM stress

In Fig. 16 the device voltage for a set of different gg-nMOSts (W = 150 Ixm, Rdev ~ 4.5 fL junction capacitances: x = 0.1, for other parameters see Table 2) is shown for a - 500 V n-CDM pulse (Table 3). The most noticeable effect visible here is that the larger the gate length L and thus the bipolar base width of the devices is, the higher is the voltage Vdev. However, this dependence is visible only during the first current peak of the CDM pulse. Moreover, for the very short gate length device (L = 0.25 tim) sudden additional voltage peaks show up at every negative and positive

371

C. Russ et al./Journal of Electrostatics 42 (1998) 351-381 -1100V socketed CDM - DILl8 5 .... , .... ] .... , .... ''"7 J ..... measured

~,,,

4

[; i ',\

3 < v2 "E #_ 1

'

1,

' \

AT

i

O 0

d 0

1

2

3 4 5 time (nsec)

6

7

8

-500V n o n - s o c k e t e d C D M - D I L l 8 5

4

I

~,

.....

measured -~

3

<.5.

2

1 0 -1

III

/

-2

I 1 ,,I,,,

-3 0

1

l,,,~1,,_,It~t, 2 3 time (nsec)

4

5

Fig. 15. Measured socketed and non-socketed CDM pulses on single gg-nMOSts in a DIL-18 plastic package and the analytical solution of a 2nd-order lumped element model.

amplitude of the C D M oscillation. Except these features, the voltage across the devices did not show any other significant differences. The different contributions to the device terminal voltage Vdev of Fig. 16 are discussed by means of the transistor model and its equivalent (Fig. 4). As the current forced through the device is nearly independent of the gate length, a large part of the voltage Vdev occurs as an ohmic voltage drop Vr across the series resistances of the device (Fig. 17). It is noticeable that the peak power at lpl reaches almost 100 W. The device internal behaviour becomes evident by the Figs. 18-21. The collectorbase voltage Vcb depicted in Fig. 18 shows clearly that the shorter the device length L, the shorter the device stays in avalanche breakdown mode with a high impact

372

C. Russ et al./Journal of Electrostatics 42 (1998) 351-381 S . . . . r'

40 -

~"

,

dev

2

30 20

Y : ¢ I

> glO >

-

Oi51am ~ l p . r n ~ \ I ~ I I " 2p'm / ~

I

\1[~41

lm

/

~. 2 bme(nse¢~) J ~

-

--

"0

0 -10 i~

-20 0

l i ] l l l

ill

Jlt

[ l i l t

1

[i

2 time

J ~,1

i1~i-

3

(nsec)

Fig. 16. Voltage across the gg-nMOSt for different gate lengths under CDM ESD stress (substrate precharge voltage VCDM= -- 500 V leading to reverse bias of the drain sided junction). Inset: the current through the device, which is almost independent of the gate length.

® 20 > II

>

0

>-10 0

i i ~ ~ I , , , , I N..,--,/ I , , , , I , , , ~ I , , , , 1 2 3 time

(nsec)

Fig. 17. Sum of the major ohmic voltages drops across collector and emitter resistor. They are independent from the gate length L and only influenced by the nearly current forcing CDM event. The dissipated power in these parts of the device is considerably high.

ionisation coefficient (voltage Vcb close to Vcbo). It is evident that snapback occurs only as an intermediate operation stage, because the device stays either in avalanche breakdown mode (as the snapback turn-on to, is large compared to the duration of the first C D M current peak ATo) or the potential at the collector decreases faster than the base potential due to the C D M oscillation. Consequently, the collector-base diode is forward biased (V~b ~ - 0.7 V). As the base-emitter junction is also forward biased at this time, the transistor enters saturation mode which leads to a very small residual voltage drop between collector and emitter. Externally at the device terminals only the drop across Vr is visible. As the base-collector junction of the gate lengths 0.5, 1, 2, 4 and 8 ktm remains forward biased during the entire CDM event, the current is sustained by saturation mode without interruption. The L = 0.25 ~tm device, however, turns off and the base-collector junction goes again into (weak) avalanche. The transistor has to trigger again! As the base-emitter

C. Russ et al./Journal oJ Electrostatics 42 (1998) 351-381

14

-,

.- - _\~

12 10

\ 8

> .¢J

>,.,

373

. -~; . . . . . . . . . . . . . . . . . . . . . . / snapback I holding avalanche j voltage " breakdown

\

\

q

6 -

4 2

•.

0 -2

0.25gin 0.5p.m I ~ 21arn 4!.t 81arn rn '! ','

-

............. 0

"

forward t I biased

I juncti°n ~

L; . . . . . . . . . . .

1

2

3

time (nsee) Fig. 18. Voltages across collector-base indicating the different operation states for differently fast switching devices: avalanching and forward biasing. The fast transients applied to the device let at the most snapback occur only as an intermediate state. For the shortest gg-nMOSt the turn-off delay is too short to sustain current flow over the entire CDM pulse, this device has to be triggered again.

10 8

L=

6

>

/ ,, ~ f

/--~/ /~

21arn l~tm

2 0

0

1

2

3

time (nsec) Fig. 19. Voltages across the intrinsic base resistance are only visible for the long gate length devices and during the first current peak. This voltage drop is responsible for the 'kink' in the rising edge of the device voltage (L = 8 I~m, Fig 16).

2 0

L~:~

....... ?---T--

-

~-2

/f°rward biased junction

-

-

i

:

;

~

I j snaoback / / I holding ~ / | voltage

[/ I.)

--

-6

i

L=O.251am

~ ~

-

>

! f-~

!

i"

l

S

i

0

i

*

i

t

i

i

I

i

I

t

i

i

h

[

t

,

t

1

: :

_~. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ¥.

-8

:

S

,

i

2

i

i

i

',

,

i

,

i"

3

time (nsec) Fig. 20. Voltages across the base-emitter indicating forward bias during avalanching of the collector-base, sustaining of the current by saturation mode (both junctions forward biased), or if the turn-off delay is too short (L = 0.25 lam) repeated turn-on's.

374

C. Russ et aL/Journal of Electrostatics 42 (1998) 351-381

0.4

....

[ ....

I '" ' ' I . . . . ~ L = O.251Ltm [ . . . . . . . . .

~"

Qdbe] Qdbc ~r edb j

"E'= o.2 0~

~ 0

"---.

,

, I ....

o.8~ ....

, ....

turn-off point ,- ~-~

j ....

,

. . . .

.

L = O.5~tm

G

.

v

"~ 0"4

/

"--

"~

-

-..

.

.

.

...... .

.

Qdbc |

.

~evi~o~--/~-~

~turn-offpoint

o~be ]

oobl ~

k ; 1.Ogre ....... OdbeI

~

G

-o.8

o

.77

I 0

,

,/,,

~

~

-

?53 -

..... 1

2

3

time (nsec)

Fig. 21. Diffusioncharges of the base-emitter(Qab~),the base-collector(Qdb~)pn-junction and their sum (Qdb).The charge storing effectin the base leadingto saturation is visualisedhere:The small amount of Qab, of the short gate length devicedrops too fast to zero (turn-off)to bridge the negativepart of the pulse before Qdb~is being built up (reverse turn-on) by either emitter avalanche or hole injection via the substrate contact.

junction is already weakly forward biased (due to the previous saturation mode period), the base-collector junction does not have to go again deep into avalanche mode. However, the collector-base voltage Vcb reaches still voltages in the order of the snapback holding voltage before it decays. The transient behaviour of the voltage across the intrinsic base resistance Vbi (Fig. 19) explains the additionally increased device voltage at the onset of the C D M pulse for the long gate length (L = 8 ~tm). Due to the base charge dependence of the intrinsic base resistance Rbi (Eq. (1.10)), this voltage contribution is significant for the small base charge occurring at the on-set of the C D M pulse. As Rbl is directly proportional to the gate length L and implicitly depending on L by the zero bias base charge Qbo, the amount of Vb~ is only significant for the larger gate lengths, 8 and 4 lain. The voltage Vbe displays the forward biasing of base-emitter (Fig. 20) due to the potential rise caused by the avalanching base-collector diode. The gate lengths 0.5, 1, 2, 4 and 8 ~tm remain forward biased during the entire C D M event sustaining the saturation mode. The L = 0.25 pm length turns off also for the negative current peak

C. Russ et al./Journal of Electrostatics 42 (1998) 351-381

]0 -

8

v

L (Ixm)

o.25

-

--

V

t , (nsec) q

0.687

~--

~

~2_-- V~ | ..... 4

4.5

5

5

4

~4

!1 ___ 5.5

375

c0 <

_11 6

time(nsec)

6.5

7

Fig. 22. Simulation experiment for the transistor in saturation mode. Both, base-collector and base-emitter pn-junction are temporarily forward biased when the forced current changes from + 5 to - 2A and brings the transistor into saturation mode during t~,,. The duration of this effect was found to be dependent on the ratio between the amplitude of the positive and the negative current (can be related to Ipl and/p2 of a CDM pulse) and on the gate length (see inset).

and now the base-emitter junction goes into (weak) avalanche requiring re-triggering. Approximately, the holding voltage of (reverse) snapback is reached. By means of Fig. 21, the influence of the base charge on the capability of the device sustaining the saturation mode becomes evident. For the very short gate length device (L = 0.25 gm), only a small base charge is required to turn on the transistor, as the base region of this device is also small. This in fact speeds up the transition from avalanche mode to saturation mode and leads to a very fast turn-on. However, the falling edge of the C D M pulse with its high -dV/dt also makes the small amount of stored charge decay very fast. When the diffusion charge of the base-emitter junction Qdbe intersects the x-axis, the transistor switches from (reverse) saturation to the (reverse) off-state (note that the device polarity has already changed at this point in time). Avalanche of the emitter-base diode starts and the device enters a new triggering cycle, For the device with L = 0.5 gm, the base region is just large enough to store sufficient charge which delivers the current during the - d V/dt part of the CDM pulse (from ,~lp~ to ,~Ip2). For devices equal to or larger than 1.0 gm, the buildup of the base charge delays the turn-on, but Qdbo is also large enough to prevent the charge Qdbe from dropping to zero. Hence, the transistor stays in the saturation mode and does not turn off during the entire rest of the C D M oscillation. A study for the time elapse to maintain the saturation mode is performed (Fig. 22). The applied pulse triggers the device into snapback mode; stable conditions are reached after the snapback turn-on time. At the time 5 ns, the device current lacy of 5 A is almost abruptly switched to - 2 A. The resulting time where saturation mode is established due to the polarity change until the sustaining of current by the base charge is exhausted, is called tsat. The strong dependence of tsat on the gate length is depicted in the inset of Fig. 22. The currents + 5 and - 2 A are chosen deliberately

376

C Russ et al./Journal o f Electrostatics 42 (1998) 351-381

here as they reflect approximately the peak currents Ipl and lp2 of the applied CDM pulse. The time t~,t is found to be strongly related to the ratio I p z / l p l , but not to the independent values of these currents. In fact, lpa determines the amount of charge supplied to the base region during this first current peak, whereas Ip2 determines the amount of current removing this charge. In conclusion we can state, that: 1. Both, the snapback turn-on time ton (although not very much pronounced during a CDM oscillation) and the CDM period time AT0 determine the time necessary to reach the saturation mode. 2. If the device is exhibiting fast snapback (L = 0.25 gm) the snapback holding voltage is already reached during the rising edge of the pulse (before lpl). This device and the ones with L = 0.5, 1, 2 ~tm reach saturation during the falling edge of the pulse, successively due to their larger turn-on time. Finally when the device voltage is close to change the polarity, also the long devices (L = 4 and 8 gm) are necessarily driven in saturation mode. 3. dV/dt triggering is found to only slightly reduce the avalanche breakdown voltage, even for an increased effective junction capacitance (xCj~b). The reason is that the CDM event forces currents through the device which are much higher compared to the maximal obtainable displacement currents. Consequently, the CDM current will flow as an avalanche current during turn-on. 4. The current ratio Ip2/Ivl providing the base charge during the first positive peak and removing it during the first negative current peak and the time period A To of the oscillation are crucial to sustain the saturation mode for the gg-nMOSt under CDM stress. 4.2. Thermal behaviour under n-CDM stress In order to study the thermal behaviour in the devices the power dissipation of the base-collector diode is calculated by means of Vcb and the real part of the device current ldev (Fig. 23). The length-dependent behaviour of Vcb is directly reflected here: the larger the gate length, the higher the peak power dissipation. Due to the longer turn-on times, also the power dissipation lasts longer. The advantage of the saturation mode with respect to the power dissipation is evident. The base-collector junction temperature resulting from the power dissipation is shown in Fig. 24. The shorter the gate length, the faster the device enters saturation and by this a state of very low power dissipation. For the devices of which the turn-on times are in the order of AT0 or larger (L = 1, 2, 4, 8 Jam),the rise of the temperature is much higher. A saturation in the heating is visible here as the maximum power dissipation is limited by the product of the base-collector junction breakdown voltage and the device current. The observed high power dissipation in the series resistances R~ and Re is compared to the base-collector power. It was assumed for the thermal model (Section 1.2) that there is uniform lateral current flow in the entire depth of the n + junction area. Thus, the power density is smaller due the larger volume. The resulting temperatures in these regions are much lower than in the base-collector junction region. However, this

C. Russ et al./Journal of Electrostatics 42 (1998) 351-381 '''

5O c 0

I ....

I''

'

T

'

~

'

-

-

~

377

"~

40

~- 30

.--,

L=

O,25pm

o m 2O

0.5pm lgm

.~__..

0 Q.

0 1

0

2

3

time (nsec)

Fig. 23. Power dissipation in the base-collector junction. When the turn-on times exceed ATo (L/> 1 pm), the power saturates around 50 W. The shortest gate length device exhibits additional power dissipation because of re-triggering.

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Fig. 24. Effective temperatures in the base-collector junction display the differences in self-heating with respect to the turn-on times.

m i g h t c h a n g e with respect to silicided j u n c t i o n s , where the c u r r e n t is first carried in a highly c o n d u c t i v e layer of silicide. At the t r a n s i t i o n from the silicide to the silicide-blocked region, where the c u r r e n t s p r e a d s o u t in a m u c h less c o n d u c t i n g layer, very high local p o w e r densities m i g h t occur. 4.3. Discussion 4.3.1. Simulations vs. C D M stress experiments T h e s i m u l a t i o n s were tested a g a i n s t e x p e r i m e n t a l n o n - s o c k e t e d a n d s o c k e t e d C D M test results on single g g - n M O S t s . B o t h s h o w e d a s t r o n g gate length d e p e n d e n c e of the

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failure thresholds distinguishing between 'short' and 'long' gate length devices [10, 39]. A 'short' gate length device was characterised by a uniform failure signature, indicating a uniform current flow and therefore a uniform and short turn-on. The 'long' gate length devices showed a pronounced non-uniform failure in the drain area always in the same device corner. The determination 'short' and 'long' was also related to the type of C D M ESD stress, either socketed or non-socketed. Both types of CDM stress, simulations as well as experiments indicate the importance of comparing the bipolar turn-on time ton (Table 2) to the width A To (Table 3) of the first CDM current peak (non-socketed CDM: Fig. 16, socketed-CDM: not shown): the earlier the voltage across the device decreases (shorter ton), the less the power dissipation (simulation) and the higher the C D M threshold (experiment). If the gate length L results in the turn-on time ton which is either shorter or in the same order of ATo then the transistor is fast enough to react on the C D M pulse. This device is called 'short' transistor. If ton is significantly larger then AT0 then the device is called 'long' transistor. Focusing on the collector-base (Vcb, Fig. 18) and base-emitter (Vbe, Fig. 20) voltages in different long gg-nMOSt under CDM stress and their thermal behaviour (Figs. 23 and 24), it is clear that 1. The shortest gate length gg-nMOSts turn on and off very fast, resulting in the need to go into weak avalanche again (to supply the bipolar base current during the following oscillations), and, in turn resulting into an increased power dissipation in the intrinsic bipolar device. 2. The medium gate length gg-nMOSts do not turn off, but instead, due to the high - d V / d t they are brought into the low-Ohmic, low-voltage saturation mode (both junctions are forward biased); this is the most interesting clamping mode with respect to power dissipation and self-heating. 3. The large gate length gg-nMOSts are too slow to turn on and therefore they clamp the C D M current in the avalanche conduction mode at a high voltage; from a dissipation point of view, this is clearly the least effective clamping mode. As the bipolar time constants and the C D M time constants AT0 are comparable, a different C D M tester (either socketed or non-socketed) or a different bipolar base width might induce different C D M stress conduction modes and as such different electrical and physical failure signatures E38].

4.3.2. Comparison of gg-nMOSts under CDM and H B M ESD stress The previous considerations in Section 4 revealed that the most preferred operation mode of a transistor under C D M stress (substrate negatively charged) is the saturation or the reverse saturation mode. Avalanche breakdown and more particularly snapback mode occur under CDM stress only as intermediate operation states until the medium and long gate length devices are triggered into saturation mode. Under HBM stress, however, snapback is found to be the predominant mode sustaining the current over the entire pulse. The saturation mode, which is strongly limiting the power in the internal transistor, is actually very beneficial for the C D M stress. Therefore, the question arises: can it also be utilised for HBM stress? The HBM ESD pulse does not have a change in the voltage polarity in the decaying pulse part (time constant 150 ns) and the pulse is only

C. Russ et al./Journal of Electrostatics 42 (1998) 351-381

379

exhibiting a -dV/dt slope which is orders of magnitude smaller than the falling edge of a CDM pulse. Hence, there exists no possibility to reduce the voltage at the collector faster than the internal base potential which is required to forward bias the collector-base junction and to drive the transistor into the low power dissipation saturation mode.

5. Conclusions The transient behaviour of NPN ESD protection devices (inherent to a grounded gate nMOS) during CDM ESD stress is studied. A compact transistor model with internal symmetrical properties, which accounts for the oscillating CDM pulse, is presented. The model is suitable for other kinds of oscillating ESD pulses, such as the Machine Model (MM) test. It is identified that, under CDM stress, grounded gate nMOS transistors can be brought into the saturation mode where both the collector-base and base-emitter junctions are forward biased. This is the least power dissipating and therefore most desirable operation mode. The very short gate length devices risk to turn off during polarity switching under CDM. Consequently, they need to be re-triggered which may cause extra snapback and avalanche related dissipation. Long gate length transistors risk to stay in avalanche conduction mode and thus not to switch to the (lower dissipating) snapback mode. The thermal model for the intrinsic transistor reflects the gate length dependency and the thermal nature of the CDM failure modes confirming earlier experimental observations. The relation between the intrinsic bipolar snapback turn-on time and the gate length is shown. The turn-on time is linked to both the transit time and the current gain of the transistor. Very short gate length gg-nMOSts, with high current gain, do not trigger as fast as expected. Longer gate length devices trigger a bit faster than expected. The dV/dt triggering is identified as a beneficial trigger mechanism. The carriers injected by fast risetime pulses build up the necessary base charge to establish full bipolar action faster than otherwise by normal avalanche caused snapback. Under very high current pulses the influence of dV/dt triggering, however, decreases due to the dominance of series resistance effects. An extraction method based on a second-order lumped element CDM tester model was developed. The CDM stress-device interaction (ultra-fast polarity change across the device, both dI/dt and dV/dt) was studied by subjecting the transistor model to the simulated test model.

Acknowledgements Mahmoud Rasras and Ingrid De Wolf (IMEC) are gratefully acknowledged for performing EMMI measurements. We wish to thank Andreas D. Stricker (Swiss

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Federal Institute of Technology, Zurich, Switzerland), Jan Marc Luchies (Philips Semiconductors, Nijmegen, The Netherlands) and Gaudenzio Meneghesso (University of Padova, Italy) for their valuable discussions. Christian Russ received a fellowship by the Commission of the European Community under the Human Capital and Mobility Program. Part of the work was supported by Alcatel Bell in the frame of a project with the Flemish Institute for Technological Research in Industry (IWT).

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