ESD circuit model based protection network optimisation for extended-voltage NMOS drivers

Microelectronics Reliability 45 (2005) 1430–1435 www.elsevier.com/locate/microrel

ESD circuit model based protection network optimisation for extended-voltage NMOS drivers V.Vassileva, V.Vashchenkob, Ph.Jansena, G.Groesenekena,c, M.Terbeekb a

IMEC, Kapeldreef 75, 3001 Leuven, Belgium also at KU Leuven, ESAT Department, Leuven, Belgium b National Semiconductor Corp.,2900 Semiconductor Drive, Santa Clara, CA 95052-8090, USA c

Abstract New snapback circuit models for drain extended MOS (DEMOS) and complementary DEMOS-SCR structures used for ESD protection in high-voltage tolerant applications have been developed. The models were experimentally validated in a standard 0.35 m CMOS process which requires 20V compatible structures. It is shown that the new ESD models provide accurate representation of the structure breakdown, turn-on behaviour into conductivity modulation mode and dV/dt triggering effect, both in static and ESD transient conditions. A major application of this model is for initial ESD optimisation of complex mixed voltage analog circuits. Ó 2005 Elsevier Ltd. All rights reserved.

A variety of analog applications require the extension of the low-voltage process capabilities towards 12-20 Volts or higher for a limited number of Input/Output pins. The most cost effective way to achieve this is to extend low-voltage sub-micron CMOS processes by implementing extended voltage lateral BJT, self-aligned lateral DMOS and non selfaligned devices [1] with extended drain, either by reusing existing CMOS layers or by adding extra implant layers. The ESD protection of these high-voltage devices in the low-voltage process presents a new challenge. The most robust way to protect the extended voltage DEMOS devices is by implementation of a siliconcontrolled rectifier DEMOS-SCR protection structure [2-4]. Since both the driver nDEMOS and the protection nDEMOS-SCR ESD trigger behaviour is controlled by the same NWELL-PWELL junction breakdown, circuit level ESD protection optimisation with respect to structure trigger behaviour, gate and

substrate coupling effects is required to fit the ESD performance of the clamp in the narrow design window shown in Fig.1. This window is limited by the circuit power supply voltage VDD, the breakdown voltage VBR of the high-voltage output driver devices, the latch-up current ILU and the failure level of the protection element.

Current

1. Introduction

ILU

ESD device power to failure Safe ESD operation area normal operation non-ESD VDD

Output Driver failure V BR

Voltage

Fig. 1 Illustration of the ESD design window for a HV tolerant output driver.

The purpose of this work is to develop nDEMOS

0026-2714/$ - see front matter Ó 2005 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2005.07.037

V. Vassilev et al. / Microelectronics Reliability 45 (2005) 1430–1435

2. ESD protection device technology and operation The non self-aligned nDEMOS devices, addressed in this study, are designed to support 20V operation voltages in a non-silicided 0.35µm CMOS process. The high-voltage drain has been realized using a thick fieldoxide (TFO) and NWELL (Fig.2a). The ESD protection nDEMOS-SCR device has an additional P-emitter anode region (Fig.2b). This junction becomes forward biased after the snapback of the parasitic NPN structure and provides the holes injected into the discharge region that support the conductivity modulation process. WELL SOURCE POLYGATE

insignificant reduction of the critical snapback voltage upon increased gate bias VGS, as seen in Fig.3a. In contrast, for the nDEMOS-SCR device, a strong reduction of the snapback voltage was observed when increasing the gate bias, as shown in Fig.3b. This effect is used further to separate the triggering of the two structures by a gate coupling circuit , which controls the nDEMOS-SCR pulsed turn-on characteristics. A test chip that included the reference nDEMOS and nDEMOS-SCR ESD devices was used for a comparative evaluation of the various snapback device triggering characteristics and to provide data for compact model development and device layout optimisation. The ESD performance evaluation was performed using curve tracing, TLP and HBM ESD testing. All nDEMOS-SCR devices demonstrated >8kV HBM stress robustness, while the nDEMOS devices failed immediately after triggering. 100 TLP CURRENT (A)

and nDEMOS-SCR ESD circuit models and to demonstrate simulation based optimisation of ESD protection for 20V voltage drivers implemented in a standard 0.35 m CMOS process. The second section of the paper outlines the nDEMOS and nDEMOS-SCR devices and ESD performance characteristics. The main physical effects that determine the ESD behaviour of the structures are outlined in the third section, together with the developed novel circuit level snapback models. The last section demonstrates circuit level ESD optimisation of a high voltage tolerant open drain driver, using nDEMOS and nDEMOS-SCR devices.

DRAIN

VGS=2.5

10-1

10-2

VGS=0

10-3 0

p+

n+

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5

10

n+

15

20

25

30

TLP VOLTAGE (V)

a) NWELL

BLOCKING JUNCTON

100

P-SUBSTRATE

a) WELL SOURCE POLYGATE p+

P-EMITTER DRAIN

n+

p+

n+

CURRENT (A)

PWELL

GATE-SOURCE BIAS (V)

10-1

5 2.5

2

10-2

1 10-3

PWELL

BLOCKING JUNCTON

VGS=0.5V

NWELL

VGS=0

10-4 P-SUBSTRATE

b)

0

5

10

15

20

25

30

VOLTAGE (V)

b) Fig. 2 Cross section of nDEMOS (a) and nDEMOS-SCR (b) devices

Typical TLP snapback characteristics of the reference non-self-aligned nDEMOS and the nDEMOS SCR devices are presented in Fig.3. The reference nDEMOS device showed a breakdown voltage BVDSS~19V, measured at 1 A current and at VGS=0. This type of device produced

Fig. 3 TLP characteristics (tp=100ns, tr=10ns) at different gate bias for W=200 m nDEMOS (a) and nDEMOS-SCR devices (b)

3. Snapback device modelling Under ESD stress conditions, several effects that are specific for such high-voltage tolerant device

V. Vassilev et al. / Microelectronics Reliability 45 (2005) 1430–1435

architectures play a role and govern the snapback behaviour. For the nDEMOS device at high drain-source bias, the breakdown is initiated in the depletion zone of the NWELL-PWELL junction, as illustrated by the MEDICI simulation shown in Fig.4a. When increasing the drain bias, a significant voltage drop occurs across the lowly doped NWELL region since it is depleted . This is seen in the I-V characteristics in Fig.3 after junction breakdown. When the depletion region expands with increasing drain bias, it will eventually reach the highly doped N+ drain region. The conductivity modulated NWELL region gets flooded by the generated electrons and holes. This results in a shift of the maximum electric field (and impact ionisation generation) towards the N+/ NWELL interface, as shown in Fig.4b. This is the well-known Kirk or base-push out effect [5]. In this regime, the parasitic bipolar device is activated, triggering the structure into snapback.

nDEMOS-SCR structures operation under ESD conditions. In contrast to previously reported works, e.g. [6], in which two different sets of model parameters are used to describe the high-voltage nDEMOS operation in two different regimes (breakdown and snapback), our approach is aimed at developing a self-consistent snapback circuit model. The new snapback nDEMOS model equivalent circuit topology is shown in Fig.5.

G

S

ID

IS IC c

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Rsub ISUBV

VNw BJT IavcNw Iavc

c

B D

S G

Oxide

N+

Fig. 5 Equivalent circuit of the nDEMOS snapback model

N+

Nwell Pwell In breakdown

a.)

D

S G

Oxide

N+

N+

Nwell

Qualitatively, the high-voltage nDEMOS behaviour is similar to the low-voltage NMOS structure operation, for which snapback models have been already developed [7]. However, it is not possible to use these models to represent the significant offset between breakdown and trigger voltage for the nDEMOS shown in Fig.3a. For the low-voltage transistors, this offset is in the order of 0.7V, which is the substrate-to-source potential required to trigger the parasitic bipolar. For the nDEMOS this voltage offset is significantly increased by the voltage drop across the NWELL region, and a new equivalent circuit topology, shown in Fig.5 has to be used. Initially, at low drain bias, the equivalent bipolar device and avalanche current source IavcBJT, representing the impact ionisation at the N+/ NWELL junction, are not active. The IavcNw avalanche current source describes the breakdown of the NWELL-PWELL junction and is expressed as IavcNw =MchIS. Mch is the multiplication factor for the channel current and it is given by the standard model 1 (1) 1 M ch

Pwell

1

In snapback

b.)

Fig. 4 MEDICI simulation of the impact ionisation region drift inside a nDEMOS device due to the Kirk effect

This understanding of the device behaviour is used to develop circuit models for the nDEMOS and

VD

V BR

n

NW

VNw in Fig. 5 represents the voltage drop across the carrier modulated NWELL region. It accounts for the modulation of the NWELL resistance with the increase of the injected carriers and it is modelled as

D

V. Vassilev et al. / Microelectronics Reliability 45 (2005) 1430–1435

V

NW

I avc NW lw I avc NW Aeff q mn N d Aeff qvsat

(2)

In (2), lw and Aeff represent the effective length and cross-section of current flow in the NWELL region and are treated as fitting (extracted) parameters, q, n, Nd and vsat are the electron charge, mobility, doping and saturation velocity, respectively. They have their nominal physical values. A similar equation is used for modelling the voltage source VRsub that represents the substrate potential increase under junction breakdown conditions. 1.E+01 1.E-01 1.E-03 W=1um W=10um W=100um W=500um

ID [A]

1.E-05 1.E-07 1.E-09

region, which leads to the activation of the parasitic bipolar structure. IavcBJT is described as IavcBJT =MBJT(kIS+IC). MBJT is described using a similar equation as MCH (with different breakdown parameters) and k is a parameter used to control the gate coupling effect in snapback operation. Note that when IavcBJT is activated, IavcNw is self-consistently deactivated due to the bias VNw. This voltage drop reduces the effective bias across the NWELL-PWELL junction and, correspondingly, the avalanche multiplication that generates IavcNw.. Such model behaviour is equivalent to the above mentioned shift of the avalanche region inside the NWELL. Fig.6 shows a comparison between the TCAD I-V characteristics calibrated with experimental data and the circuit simulation generated characteristics using the model in Fig.5. It is seen that the model accurately represents the breakdown and trigger behaviour for different structure dimensions.

VHBM =8kV

1.E-11

VHBM =4kV

1.E-13 VHBM =500V

0

10

20

VD [V]

1.E-15 30

VD [V]

1.E+01

W=500um

1.E-01 1.E-03

ID [A]

1.E-05

W=1um W=10um W=100um

1.E-07 1.E-09

VHBM =8kV VHBM =4kV VHBM =500V

1.E-11 VD [V]

1.E-13 1.E-15

0

10

20

30

VD [V] Fig. 6 Calibrated to experiment TCAD IV (top) and circuit (bottom) nDEMOS snapback simulation characteristics at VG=0V for different device widths.

The avalanche current source IavcBJT in Fig.5 represents the avalanche current for the N+/ NWELL

Fig. 7 HBM response of the reference calibrated TCAD structure (top) and the compact model (bottom) for different HBM pre-charge voltages.

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V. Vassilev et al. / Microelectronics Reliability 45 (2005) 1430–1435

G ID

C

A

ICNPN

Re

VRNw

ISUB B

IavcNPN

IavcNw

Rc Rbpnp

VRsub

Rcpnp

ICPNP

TLP trigger voltage seen in Fig.3b, due to the slower HBM pulse rise time. The latter controls the triggering of the usually slow SCR structures. 10

VG=5V 1m

VG=2V VG=1V

IC [A]

The transient device characteristics are also well represented by the model. As seen in Fig.7, the HBM response of the reference TCAD structure (top) and the circuit model (bottom) for different HBM pre-charge levels show good agreement. Initially, the drain voltage increases with the transient increase of the amplitude of the incident HBM pulse. The peak voltage indicates the snapback triggering condition, which causes the voltage collapse. When the discharge current becomes sufficiently low, the device switches off, and the voltage starts to increase again due to charging of the drain capacitance by the remaining small HBM discharge current. It is seen that at low HBM precharge voltage the structure tends to oscillate due to the very low discharge current, which is not sufficient to support the bipolar snapback operation. This is captured well by the circuit model. The nDEMOS-SCR model is formed by adding a PNP bipolar device to the nDEMOS snapback model, as shown in Fig.8. The equivalent emitter and base resistance Repnp and Rbpnp are used to control the activation and the high-current operation of the equivalent PNP transistor. Rcpnp is used to represent the PWELL resistance and substrate current flow that does not contribute to the operation of the NPN device.

100n

VG=0V

10p

0

10

20

30

VC [V] Fig. 9 DC snapback simulation using the nDEMOS-SCR model at different gate bias conditions

VD, ID [V,A]

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V g =0V V g =2V

VD

V g =5V

ID

Repnp

Fig. 8 Simplified equivalent circuit for the nDEMOS-SCR snapback model.

Fig.9 shows the simulated DC snapback triggering behaviour of the nDEMOS-SCR device at several gate bias conditions, using the model in Fig.8. Note the significant reduction of the trigger voltage with increasing VG, which also corresponds to the experimental observations shown in Fig. 3b. This behaviour is beneficial for protecting the nDEMOS structures present in high-voltage output drivers. Fig.10 shows the simulated transient 2kV HBM response of the nDEMOS-SCR device. A significant decrease of the voltage overshoot is observed when increasing the gate bias, e.g. by using a gate coupling technique. The peak voltage is slightly higher than the

Fig. 10 Circuit simulation of 2kV HBM response at different gate bias for a W=200 m nDEMOS-SCR

4. Application to HV protection development A simplified schematic of an open drain driver circuit, which combines nDEMOS and nDEMOS-SCR structures, is shown in Fig.11. The nDEMOS device has a 30k resistor attached to its gate to mimic the dynamic coupling load from the driver circuit. Under ESD conditions, depending on circuit and structural parameters, the ESD current can discharge either through the nDEMOS-SCR ESD protection clamp or through the nDEMOS driver.

V. Vassilev et al. / Microelectronics Reliability 45 (2005) 1430–1435

Output nDEMOS Output driver

RLOAD 30k

nDEMOS-SCR Protection

RGATE

Fig. 11 Simplified schematic of ESD protection for open drain output driver

Fig. 12 shows an example of the circuit waveforms for positive stress between output and ground for two values of the nDEMOS-SCR gate resistor RGATE. The latter represents a possible ESD circuit optimisation design parameter. When RGATE is sufficiently high (~10k ) it provides ESD current clamping through the nDEMOS-SCR, Fig, 12a. When RGATE is reduced down to 1k it results in snapback of the nDEMOS device, Fig.12b, which in reality causes irreversible circuit failure due to the low ESD robustness of the nDEMOS structures.

Output

nDEMOS-SCR

nDEMOS a)

Output

nDEMOS nDEMOS-SCR b) Fig. 12 Voltage current waveforms for two values of RGATE (see Fig.11) - 10k (a) and 1k b) representing two possible circuit designs

A similar effect of forcing the triggering of the nDEMOS-SCR structure before the triggering of the protected device can be achieved when using a substrate coupling technique [8]. Snapback models for both the protection (nDEMOS-SCR) and the protected (nDEMOS) devices are thus required to achieve correct simulation results under ESD conditions and to properly optimise the circuit for the desired ESD performance. Conclusions The application of extended voltage nDEMOSSCR devices for ESD protection of 20V tolerant nDEMOS output drivers, implemented in a standard 0.35 m CMOS process, is discussed. New snapback circuit models for these devices have been developed and experimentally validated under static and transient conditions and represent well the structure breakdown, turn-on and dV/dt trigger behaviour. Circuits using transient coupling techniques can now be used for the ESD reliability optimisation of complex high-voltage circuits. The overall value of such a protection strategy is in its straightforward capability to provide dedicated protection solutions for high-voltage circuits and to achieve both high ESD robustness and optimum functionality of the analog circuit blocks operating at different supply voltages. References [1] G.M.Dolny, et al, Enhanced CMOS for analog-digital power IC applications by IEEE Trans. Electron Devices, V33, N12, 1986, p.1985 [2] G.Groph, and J. Bernier ESD protection for high frequency integrated circuits , Sol.-St. Electron.,V.38,1998, pp.1681-1689. [3] A.Concannon, V. A. Vashchenko, M. ter Beek, P. Hopper, ESD Protection of Double-Diffusion Devices in Submicron CMOS Processes , in Proc. ESSDERC, 2004, pp. 261-264 [4] V.A.Vashchenko, and M. ter Beek, ESD protection window targeting using LDMOS-SCR devices with PWELL-NWELL Super-Junction in Proc. IRPS, April 2005. pp. 612-613 [5] S.M.Sze, Physics of Semiconductor devices , John Wiley & Sons [6] M.Mergens et al., Analysis of lateral DMOS power devices under ESD stress conditions , in IEEE TED, Vol.47, No11, 2000, pp.2128-2136 [7] V.Vassilev et al., Analysis and Improved Compact Modelling of the Breakdown Behaviour of sub-0.25 micron ESD Protection ggNMOS Devices , in Proc. EOS/ESD Symp., pp. 62-70 [8] Ch.Duvvury et al., Substrate Pump NMOS for ESD Protection Applications , in Proc EOS/ESD Symp. 2000, pp. 7-17

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