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A comprehensive simulation model for immunity prediction in integrated circuits with respect to substrate injection
ARTICLE IN PRESS Microelectronics Journal 40 (2009) 1788–1795
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Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
A comprehensive simulation model for immunity prediction in integrated circuits with respect to substrate injection Ali Alaeldine a,, Richard Perdriau a, Ali Haidar b a b
ESEO, 4, rue Merlet-de-la-Boulaye - BP 30926, 49009 ANGERS Cedex 01, France BAU, Beirut Arabic University, P.O.Box: 11-5020, Beirut, Lebanon
a r t i c l e in f o
a b s t r a c t
Article history: Received 18 November 2008 Received in revised form 15 October 2009 Accepted 19 October 2009
This paper presents a comprehensive modelling methodology for the electromagnetic immunity of integrated circuits (ICs) to direct power injection (DPI). The aim of this study is to predict the susceptibility of ICs by the means of simulations performed on an appropriate electrical model of different integrated logic cores located in the same die. These cores are identical from a functional point of view, but differ by their design strategies. The simulation model includes the whole measurement setup as well as the integrated circuit under test, its environment (PCB, power supply) and the substrate model of each logic core. Simulation results and comparisons with measurement results demonstrate the validity of the suggested model. Moreover, they highlight the interest of the aforementioned protection strategies against electromagnetic disturbances. & 2009 Elsevier Ltd. All rights reserved.
Keywords: EMC IC DPI Protection techniques Substrate modelling Susceptibility modelling
1. Introduction For many years, digital and analogue integrated circuits have become more and more emissive from an electromagnetic point of view, due to an increased number of active devices and higher data rates. Therefore, the development of an efficient and accurate electrical model of the electromagnetic emission of integrated circuits, such as the ICEM model [1], and capable of predicting the emission of an IC in its environment, even before tape-out, is becoming of paramount importance in the area of electromagnetic compatibility. At the same time, these ICs are becoming not only more emissive, but also more susceptible to electromagnetic disturbances, due to a steady reduction in power supply voltage and, consequently, noise margin [2,3]. In particular, substrate noise can disturb the operation of an IC. This noise may originate from the external world or from other blocks inside the circuit. Therefore, susceptibility reduction techniques must take into account this substrate noise [4]. Several measurement methods have been developed, some of them standardised, to characterise the electromagnetic susceptibility of integrated circuits. In this paper, the direct power injection (DPI) method [5] will be used in order to inject a continuous-wave disturbance into the substrate of an IC. In the same manner as for emission, electrical models enabling the prediction of the immunity of an IC before tape-out would be profitable. Corresponding author. Tel.: + 33 2 4186 67 03.
E-mail address: [email protected] (A. Alaeldine). URL: http://perso.eseo.fr/~aalaeldine/ (A. Alaeldine). 0026-2692/$ - see front matter & 2009 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2009.10.004
An electrical model of a DPI setup has already been developed for an injection into the power rail of an IC [6]. However, it is not suited to substrate injection, due to the lack of a proper model taking into account, in a simplified manner, the dissipation of an electromagnetic disturbance into the substrate. This study is based on a specific IC (CESAME) including several emission reduction strategies [7]. The interest of these strategies for susceptibility reduction has already been pointed out [8], but only by the means of measurements. Consequently, this paper presents a comprehensive simulation model of the direct power injection into the substrate of an IC, and compares simulation results for these strategies with the ones previously obtained through measurements. The paper is organised as follows. First of all, the different logic cores of the test chip used in this study are described in Section 2. Then, the immunity measurement method is detailed in Section 3, with an emphasis on the modelling of the injection setup and the circuit under test including substrate models. Section 4 deals with a comparison between measurement and simulation results in order to validate the suggested model. Finally, Section 5 underlines the key points of this study.
2. Description of the test chip The test chip used in this study, called CESAME [9], has been developed by STMicroelectronics in 0:18 mm CMOS technology (die area: 11 mm2 ), specifically for the investigation of several EMI
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reduction techniques [7]. CESAME is composed of six logic cores which are identical from a functional point of view, but differing by their power supply strategies. Each core is composed of 240 identical base cells, each one including D flip–flops, a clock tree and standard gates, intended to reflect the activity of a typical digital core and each base cell consists of 400 transistors. This IC is mounted on a custom printed circuit board (PCB), called ALI [8]. These cores are built in an epitaxial substrate with a negligible horizontal resistance. In this paper, only three different cores (NORM, ISO and RC, surrounded in red in Fig. 1) out of six are used. Four cores (NORM, RC, NOR and GRID) are built in the global substrate of the IC, while the other ones (ISO and ISV) are built in local isolated substrates. NORM core: The only EMI protection strategy used in the NORM core consists of two small 1:7 O series resistors, one on each power supply rail. These resistors, along with the metal and MOS capacitances of the logic core, build up a RC filter, with a high cutoff frequency (about 200 MHz). ISO core: Another protection strategy is used for the ISO core. This core is embedded in its own local substrate, isolated from the rest of the chip thanks to a triple-well technique. The same Vdd rail is used for the sources of the upper PMOS transistors (in logic gates) and the polarisation of the local substrate. RC core: In this core, an additional 1-nF integrated decoupling capacitor is included between both supply rails. This distributed on-chip capacitor is made up of several poly1/poly2 capacitors, and increases the area of the RC core by 40% compared with the NORM core. By lowering the cutoff frequency of the RC filter (about 40 MHz), this technique allows the reduction of the power distribution noise arising from multiple drivers switching simultaneously [10]. GRID core: The GRID core, like the NORM core, only uses the series resistors as a protection technique. However, its power supply network is meshed on the highest (5 and 6) metal levels (hence the name), thus reducing the total power supply impedance. ISV core: The ISV core, like the ISO core, is built in a local isolated substrate. However, unlike in the ISO core, the Vdd of the PMOS transistors and the Vdd of the local substrate are separated on the die.
Fig. 1. CESAME test chip and the three cores under test (NORM, ISO and RC) in red. (For interpretation of the references to the colour in this figure legend, the reader is referred to the web version of this article.)
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NOR core: The NOR core is not fitted with 1:7 O series resistors. This is the simplest architecture available in the circuit, with no EMI protection strategy.
3. Direct power injection (DPI) method: set-up and modelling In order to characterise the behaviour of ICs to electromagnetic interference, several measurement methods are currently under standardisation process under the supervision of the International Electrotechnical Commission (IEC), one of which is the direct power injection (DPI) method [5]. This article introduces a complete electrical model of a DPI setup for substrate injection, making it possible to predict the immunity of an IC on a given printed circuit board (PCB) within the design phase. 3.1. Set-up of the injection system An example of DPI setup is displayed in Fig. 2. Continuous sinewave RF power (from 10 MHz to 1 GHz) delivered by a generator is fed into an amplifier and then injected into a pin of the IC under test (either a power pin or a signal input pin) through a capacitor blocking the DC voltage coming from the power supply (hence the name of the test). A directional coupler allows the measurement of incident and reflected powers by the means of a dual-input power metre. The output signal of the IC is monitored on an oscilloscope in order to check out the susceptibility of the circuit under test according to a given criterion which will be presented in this paper. Only the incident power will be used in this study in order to plot the measurement and simulation immunity curves of all aforementioned cores. For each frequency step, incident power is increased until a failure occurs (in time domain). It is then possible to establish a susceptibility plot, as a function of injected frequency, from these time-domain measurements or simulations. 3.2. Modelling of the injection system and the PCB The objective of the modelling process is the prediction of the immunity of the CESAME IC to EMI disturbances. A key point to the validation of the immunity model lies in the evaluation of the power actually injected into the circuit. Therefore, each part of the setup (injection probe, injection capacitor, PCB, IC including substrate, and directional coupler), except the active part (transistors) of the IC, must be modelled separately as a combination of equivalent passive elements; these individual models must then be combined in order to obtain the whole equivalent model. The first step is the injection system, each part (injection probe, connection between the probe and the GND of the PCB) of which was measured and modelled separately from
Fig. 2. DPI injection system.
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measurements obtained with the help of a vector network analyser (VNA). The model of the injection probe is inductive, with a low series resistance. This probe is attached to the IC under test through an injection capacitor of 1 nF, but its outer connector is soldered on the ground plane of the PCB. Consequently, the inner wire of the probe is coupled with the ground plane through a capacitance and a resistance, representing the dielectric of the coaxial cable. Moreover, the inductance of the small wire connecting the core of the cable with the IC pin is measured, its value is negligible. The DPI setup includes two discrete capacitors: a 1 nF injection capacitor, used to prevent the reinjection of the DC voltage supplied by the board into the RF power amplifier, and a 47 nF decoupling capacitor located on the PCB [11]. An accurate impedance measurement of these capacitors can be achieved s thanks to an Agilent N1020A probe connected to the VNA. These ceramic SMD capacitors can be modeled by a series RLC network. The same operation can be reiterated for the decoupling capacitor. The directional coupler used for power measurements can be identified as a 50 O lossless transmission line. Its propagation time Td is computed using Eq. (1): Td ¼ Z0 C0 ¼ 2471 ps
ð1Þ
in which C0 is measured with a VNA in Smith chart mode. The coupler has a very strong influence on the global impedance profile of the setup. Unfortunately, it is integrated in the power amplifier and can not be removed for DPI measurement purposes (only for impedance measurements). Therefore, the following simulations and measurements always take this coupler into account. Moreover, in this study, the DPI setup does not follow the standard proposal [5]. The custom-designed PCB (called ALI) includes its own power supply, composed of a 9 V battery and several regulators, including a 1.8 V regulator for the digital core and IOs of the IC, the only one to be modelled in this case. Conversely, the standard proposal requires the use of an external power supply, with a series choke inductor preventing the reinjection of RF power into the supply. The regulator, the battery and the PCB tracks (including vias) were modelled by series RLC networks. In particular, the inductances of the Vdd and Vss tracks, both located over a ground plane, were established thanks to Eq. (2) [12]: m ml 8h w þ ð2Þ LVdd ¼ LVss ¼ 0 r ln 2p w 4h in which l and w are respectively the length and the width of the track, h the distance between the track and the ground plane. On this PCB, w ¼ 300 mm and h varies between 0.5 and 1.5 mm depending on the routing layer.
3.3. Modelling of the integrated circuit package and bonding The CESAME circuit is encapsulated in a TQFP144 package. The electrical model of this package was obtained from a 3D s electromagnetic simulation with HFSSs (Ansoft ) [13]. In order to compute the inductances of the leadframe and the bonding, it can be noted that the Vdd and Vss pins are adjacent on the package, which implies that the current return path can be easily determined. Therefore, their equivalent inductances can be computed from Eq. (3) [12]: m ml 4h ð3Þ LVdd ¼ LVss ¼ 0 r ln 2p d in which l and d are respectively the length and the diameter of the leadframe or the bondwire, and h its distance to the ground plane.
Then, the CVdd=Vss coupling capacitance between both power supply rails can be computed from Eq. (4) [14]: " C12 ¼ e0 er l
2:22 0:64 # e 0:1 d e w d þ 1:21 þ 1:15 þ 0:54 þ 0:25ln 1 þ 7:17 d h h d h
ð4Þ In addition to that, intra-IC inductive coupling between Vdd and Vss is an important factor which widely influences the amount of RF power actually injected into the die [15]. The mutual inductance between both rails is given by Eq. (5), and the coupling factor by Eq. (6): " # m0 mr l ðd þ 4wÞ2 þ ð1:5w þ2hÞ2 ð5Þ ln MVdd =Vss ¼ 2p ðd þ wÞ2 þð1:5wÞ2 MVdd =Vss ffi KM ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffiffi LVdd LVss
ð6Þ
3.4. Modelling of CESAME cores As can be seen in the circuit description (paragraph 2), each logic core includes 240 identical base cells, each one composed of 400 transistors. In order to speed up time-domain simulation, only one base cell (reference cell) is included in the whole netlist [6]. The remaining cells are replaced by an equivalent parallel RC model representing the impedance of all CMOS transistors. This RC model is located in parallel with the reference cell. The reference cell is fed with a 20 MHz clock signal and a square 10 MHz data signal, and the output of the cell can be directly observed on an output pin of the chip. The parasitic elements of the pads and the on-die power supply rails are then modelled using the same methodology as the one used for the package. Moreover, the surface of the CESAME die is 11 mm2 , it is located about 1 mm above the ground plane, thus leading to an additional C_pcb ¼ 500 fF coupling capacitance between the substrate and the ground. By assembling all the models computed previously, a complete electrical SPICE model of the DPI setup can be established, which is depicted in Fig. 3. This full electrical model includes also the netlist of the reference cell which is identical in the three cores. Moreover, in this study, the power is injected through the Vss pin of the three cores NORM, ISO and RC, thus requiring accurate modelling of the own substrate of each core. 3.4.1. Substrate modelling for the NORM core In all cases, RF power is injected into the global substrate of the circuit via the Vss pin. As far as the NORM core is concerned, its substrate is actually the global substrate of the IC. As can be seen in Fig. 4 (top), the vertical resistance of the substrate is modelled and replaced by a resistor (R_epi_NORM). Then, the capacitive coupling between the substrate and the PCB ground is modelled by C_pcb. In addition to that, the IC includes five other cores, among which three (NOR, RC, GRID) are built in the global substrate. Another coupling between this substrate and the PCB ground is achieved through the package pins of these three cores; therefore, their Vss rail models must be included into the model. It can be noted that the coupling with the ISO and ISV cores, which are built in their own local substrate, can be neglected in firstorder approximation. Finally, the complete substrate model for the NORM core is displayed in Fig. 4 (bottom). The values of the passive devices in this model are displayed in Table 1. The model of the NORM substrate is then added to the complete model of the system under test are shown in Fig. 3. 3.4.2. Substrate modelling for the ISO core In the case of the ISO core, the NISO isolation layer between the local substrate of the core and the global substrate of the
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Fig. 3. Complete electrical model of the DPI setup.
Table 1 Device values for the substrate model (NORM core). Element
Value (O)
Element
Value
R_epi_NORM R_GRID R_RC R_NOR
30 30 30 30
C_pcb L_GRID L_RC L_NOR
500 fF 3.57 nH 3.67 nH 3.67 nH
integrated circuit CESAME must be taken into account. Consequently, two additional coupling capacitors are included [4]: the first one (C_pwell1) is located between the global P substrate and the NISO layer, while the second one (C_pwell2) is located between the isolation layer and the local Pwell substrate of the ISO core, as displayed in Fig. 5. Moreover, the resistive effect (R_nwell) of the N well of the Vdd pin is taken into account. Like in the NORM core model, a resistive value (R_epi_ISO) represents the resistance of the substrate; however, since the local substrate is thinner as the global substrate, its value is lower than the one of the NORM core. It can be noted that, at very high frequencies, this fact can have an adverse effect on shielding [4]. This time, four other cores (NOR, NORM, RC and GRID) are built in the global substrate. Consequently, the coupling with the PCB ground is achieved through four pins, with their inductance and resistance. The complete substrate model is shown in Fig. 5 (right), while the values of its elements are displayed in Table 2.
Fig. 4. Structure of an inverter of the NORM core (top) and electrical model of the substrate of the NORM core (bottom).
3.4.3. Substrate modelling for the RC core In the case of the RC core (built in the global substrate), the onchip decoupling capacitor is located between the Vdd and Vss power supply rails. It is modelled and replaced by two passive elements C_decoup and R_decoup in series. R_sub_RC, shown in
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Fig. 5. Structure of an inverter of the ISO core (top) and electrical model of the substrate of the ISO core (bottom).
Table 2 Device values for the substrate model (ISO core). Element
Value
Element
Value
R_epi_ISO C_pwell1
22 O 270 pF
R_nwell C_pwell2
2O 348 pF
Fig. 6, represents the substrate resistance seen from the Vdd power input. The same package coupling effect as for the NORM core can be observed with the three other cores built in the same substrate (NOR, NORM, GRID). Fig. 6 (bottom) represents the complete electrical model of the RC substrate which will be added to the whole electrical model of the system under test (Fig. 3). Device are displayed in the Table 3.
It can be noted that all cores are immune to a 10-W incident power below 60 MHz. Above this frequency, they are becoming more and more susceptible. Low- and high-immunity frequencies are almost identical between measurement and simulation results. Conversely, in the 460–640 MHz frequency range, the difference is greater then 6 dBm with the simulation being more ‘‘optimistic’’. These discrepancies may be due to power losses [16,17] which have not been included so far in the simulation model and still remain to be studied. Moreover, the peak observed at 679 MHz on the measurements of the three cores is due to the cavity resonance of the PCB. The cavity resonance is computed from Eq. (7) which provides the resonant frequency as a function of the relative permittivity of the PCB (FR4), its dimensions and its thickness: c Fm;n;p ¼ pffiffiffiffi 2 er
4. Results A first immunity simulation was performed from 10 MHz to 1 GHz. This time-domain simulation is performed for each frequency step (10 MHz); a failure in the IC is characterised by the ripple of the output signal reaching 20% of the logic ‘‘1’’ voltage level, or by the jitter of this output signal reaching 10% of the period [6]. Figs. 7–9 depict the comparison between experimental measurements [8] and simulation results of the immunity of the NORM, RC and ISO cores, respectively. The lower the injected power, the less immune the core.
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi m2 n 2 p2 þ þ L W T
ð7Þ
in which L, W and T are respectively the length (10.3 cm), the width (10.3 cm) and the thickness (1.6 mm) of the board. er ¼ 4:6 represents the relative permittivity of the FR4 board. m, n and p represent mode indices. The values of the cavity resonance induced by the PCB are displayed in Table 4. Another effect that must be taken into account is due to the behaviour of inputs and outputs. They can be represented as series RLC networks, as depicted in Fig. 10. In this figure, CPMOS and CNMOS represent the drain-source capacitances of the driver transistors, Rio and Lio the equivalent passive elements (bonding and leadframes) of the pin itself. At
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Fig. 6. Structure of an inverter of the RC core (top) and electrical model of the substrate of the RC core (bottom).
Table 3 Device values for the substrate model (RC core). Element
Value
Element
Value (O)
R_epi_RC C_decoup
30 O 1 nF
R_sub_RC R_decoup
34 1
their resonant frequencies, an improvement on IC immunity can be observed due to the ‘‘decoupling’’ behaviour of the network.
5. Discussion and comparison among results 5.1. Measurement results The DPI experiment consists in injecting continuous power into the substrate pin of the NORM core. Since this core is implemented in the global substrate of the integrated circuit, the injected power is dissipated in the whole substrate. This substrate
noise has an influence, not only on the NORM core itself, but also on the other cores of the circuit. DPI measurements were performed from 10 MHz to 1 GHz in 10 MHz frequency steps. For each frequency, the injected power at which the integrated circuit becomes susceptible is recorded. The whole frequency plot is represented in Fig. 11 for each core. Different protection strategies were initially used to decrease the parasitic emission of these cores, but can be useful to increase their immunity as well. The deep N insulation layer between the global substrate and the local substrate of the ISO core lowers the coupling capacitance between both substrates. Hence, the susceptibility of the ISO core is generally lower than the one of the NORM core, particularly from 10 to 210 MHz. However, it can be noted that the ISO core is less immune than the NORM core between 400 and 500 MHz; this may be due to an antiresonance of the coupling capacitor with the passive elements of the power supply network. The RC core includes an on-chip decoupling capacitor between the Vdd and Vss power supply rails. This on-chip decoupling capacitor enhances the immunity of the RC core in comparison with the others, except between 500 and 650 MHz where the RC
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40
40 Measurement Simulation
Measurement Simulation
35 Injected power (dBm)
Injected power (dBm)
35
30
25
20
30
25
20
15
DPI into the substrate of the RC core: −Output signal susceptibility
DPI into the substrate of the NORM core: −Output signal susceptibility
15
10 0
100
200
300
400
500
600
700
800
0
900 1000
100 200 300 400 500 600 700 800 900 1000
Frequency (MHz) Fig. 7. Immunity of the NORM core: measurement (solid) and simulation (dotted).
40 Measurement Simulation
Injected power (dBm)
35
30
Frequency (MHz) Fig. 9. Immunity of the RC core: measurement (solid) and simulation (dotted).
Table 4 Values of the cavity resonance induced by the PCB. m
n
p
L (mm)
W (mm)
T (mm)
er
Cavity resonance (MHz)
1 0
0 1
0 0
103 103
103 103
1.6 1.6
4.6 4.6
679 679
25
20
15 DPI into the substrate of the ISO core: −Output signal susceptibility 10 0
100 200 300 400 500 600 700 800 900 1000 Frequency (MHz)
Fig. 8. Immunity of the ISO core: measurement (solid) and simulation (dotted).
core is less immune than the ISO core; likewise, an antiresonance of the capacitor with the power supply network may explain this behaviour. In high frequency (above 650 MHz), the ISO and RC cores have similar susceptibility levels except at 780 MHz.
5.2. Simulation results Another interesting result consists in comparing simulation results for the three cores in the same figure (Fig. 12), in order to assess the relative efficiencies of the protection strategies and compare them with the ones obtained from measurements. The main explanation for the discrepancy between simulations and measurements may come from the non-inclusion of the layoutrelated parasitics of the chip (not available from the foundry) into the IC model. Consequently, propagation and transition times are identical for all circuit gates. Although the rise and fall times of the pulse generators were identical in both cases, simulations bear a much more ‘‘regular’’ pattern than measurements. Previous studies [18] have pointed out the efficiency of substrate noise
Fig. 10. Equivalent model of an I/O.
reduction techniques. Moreover, measurements for the three cores under test have already been presented in [19,8]; they demonstrated that the RC core is the most immune to DPI, followed by the ISO core and, finally, the NORM core. As far as simulations are concerned, it is important to notice that the hierarchy among the three cores is exactly identical. This result thus confirms the previous studies conducted on this topic.
6. Conclusion A comprehensive simulation model of direct power injection into the substrate of an integrated circuit, including the substrate coupling paths, has been presented in this paper as an extension of the ICEM model. The suggested substrate models can be added to the existing setup model, making it possible to perform immunity simulations. Moreover, the classification obtained from simulations for these strategies matches the one obtained from
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40 NORM ISO RC
1795
fabricated, with several analogue and digital integrated blocks and new shielding methods, in order to study the efficiency of these techniques on external and internal immunities.
35 Injected power (dBm)
References 30
25
20
15 DPI into the substrate of CESAME test chip: − Output signal susceptibility
10 0
100 200 300 400 500 600 700 800 900 1000 Frequency (MHz)
Fig. 11. Comparison among the measured immunities of the NORM, ISO and RC cores.
40 Simulation: NORM core Simulation: ISO core Simualtion: RC core
Injected power (dBm)
35
30
25
20 DPI into the substrate of the three cores (NORM, ISO and RC): −Output signal susceptibility
15 0
100 200 300 400 500 600 700 800 900 1000 Frequency (MHz)
Fig. 12. Comparison among the simulated immunities of the NORM, ISO and RC cores.
measurements, and demonstrates that the integrated decoupling capacitor seems to be the best EMI protection method against external sources of substrate noise. In the future, substrate noise injection will be applied into another test chip which will be specifically designed and
[1] IEC EMC Task Force, IEC62433-2: EMC IC modelling—part 2: models of integrated circuits for EMI behavioural simulation—conducted emissions modelling (ICEM-CE), Technical Report, IEC, October 2008. [2] S. Ben Dhia, M. Ramdani, E. Sicard, Electromagnetic Compatibility of Integrated Circuits, first ed., Springer, Berlin, 2006. [3] E. Charbon, P. Miliozzi, L.P. Carloni, A. Ferrari, A. Sangiovanni-Vincentelli, Modeling digital substrate noise injection in mixed-signal ICs, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 18 (3) (1999) 301–310. [4] R. Rossi, G. Torelli, V. Liberali, Model and verification of triple-well shielding on substrate noise in mixed-signal CMOS ICs, in: Proceedings of ESSDERC, Portugal, September 2003. [5] IEC EMC Task Force, IEC61967-4: integrated circuits, measurement of electromagnetic emissions, 150 kHz to 1 GHz—part 4: measurement of conducted emissions—1 O=150 O direct coupling method, Technical Report, IEC, July 2006. [6] A. Alaeldine, R. Perdriau, M. Ramdani, J.L. Levant, A direct power injection model for immunity prediction in integrated circuits, IEEE Transactions on Electromagnetic Compatibility 50 (1) (2008) 368–379. [7] A. Tankielun, P. Kralicek, U. Keller, E. Sicard, B. Vrignon, Influence of core optimisation and activity for electromagnetic near-field and conducted emissions of CESAME test chip, in: EMC Compo 04, Fourth International Workshop on Electromagnetic Compatibility of Integrated Circuits, March 2004, pp. 95–100. [8] A. Alaeldine, N. Lacrampe, A. Boyer, R. Perdriau, F. Caignet, M. Ramdani, E. Sicard, M. Drissi, A comparison between emissions and susceptibility reduction techniques in integrated circuits, Microelectronics Journal 29 (12) (2008) 1728–1735. [9] B. Vrignon, S. Ben Dhia, E. Lamoureux, E. Sicard, Characterization and modeling of parasitic emission in deep submicron CMOS, IEEE Transactions on Electromagnetic Compatibility 47 (2) (2005) 382–387. [10] P. Chahal, R. Tummala, M. Allen, M. Swaminathan, A novel integrated decoupling capacitor for MCM-L technology, IEEE Transactions on Components, Packaging and Manufacturing Technology 21 (2) (1998) 184–193. [11] V. Ricchiuti, A. Orlandi, G. Antonini, Buried capacitance technology for power bus decoupling on high speed digital PCBs, in: Proceedings of 14th International Zurich Symposium on Electromagnetic Compatibility, Zurich, Switzerland, February 2001. [12] E. Sicard, Le Couplage Diaphonique dans les Circuits CMOS Submicroniques, Habilitation a diriger des recherches, INSA de Toulouse, 1998 (in French). [13] Ansoft Corporation, HFSS /http://www.ansoft.com/S. [14] N. Delorme, M. Belleville, J. Chilo, Inductance and capacitance analytic formulas for VLSI interconnects, IEE Electronics Letters 32 (11) (1996) 996– 997. [15] H.B. Bakoglu, Circuits Interconnects and Packaging for VLSI, first ed., Addison-Wesley, Reading, MA, 1990. [16] A. Alaeldine, R. Perdriau, M. Ramdani, V. Veeragandham, Electrical model for power losses in direct power injection, IET Science, Measurement and Technology 1 (5) (2007) 284–289. [17] M. Xu, T. Hubing, Estimating the power bus impedance of printed circuit boards with embedded capacitance, IEEE Transactions on Advanced Packaging 25 (3) (2002) 424–432. [18] S. Ardalan, M. Sachdev, An overview of substrate noise reduction techniques, in: International Symposium on Quality Electronic Design (ISQED04), USA, 2004, pp. 291–296. [19] A. Alaeldine, N. Lacrampe, J.L. Levant, R. Perdriau, M. Ramdani, F. Caignet, M. Bafleur, E. Sicard, M. Drissi, Efficiency of embedded on-chip EMI protections to continuous harmonic and fast transient pulses with respect to substrate injection, in: IEEE International Symposium on Electromagnetic Compatibility (EMC2007), Hawaii, USA, July 2007.
Contents lists available at ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
A comprehensive simulation model for immunity prediction in integrated circuits with respect to substrate injection Ali Alaeldine a,, Richard Perdriau a, Ali Haidar b a b
ESEO, 4, rue Merlet-de-la-Boulaye - BP 30926, 49009 ANGERS Cedex 01, France BAU, Beirut Arabic University, P.O.Box: 11-5020, Beirut, Lebanon
a r t i c l e in f o
a b s t r a c t
Article history: Received 18 November 2008 Received in revised form 15 October 2009 Accepted 19 October 2009
This paper presents a comprehensive modelling methodology for the electromagnetic immunity of integrated circuits (ICs) to direct power injection (DPI). The aim of this study is to predict the susceptibility of ICs by the means of simulations performed on an appropriate electrical model of different integrated logic cores located in the same die. These cores are identical from a functional point of view, but differ by their design strategies. The simulation model includes the whole measurement setup as well as the integrated circuit under test, its environment (PCB, power supply) and the substrate model of each logic core. Simulation results and comparisons with measurement results demonstrate the validity of the suggested model. Moreover, they highlight the interest of the aforementioned protection strategies against electromagnetic disturbances. & 2009 Elsevier Ltd. All rights reserved.
Keywords: EMC IC DPI Protection techniques Substrate modelling Susceptibility modelling
1. Introduction For many years, digital and analogue integrated circuits have become more and more emissive from an electromagnetic point of view, due to an increased number of active devices and higher data rates. Therefore, the development of an efficient and accurate electrical model of the electromagnetic emission of integrated circuits, such as the ICEM model [1], and capable of predicting the emission of an IC in its environment, even before tape-out, is becoming of paramount importance in the area of electromagnetic compatibility. At the same time, these ICs are becoming not only more emissive, but also more susceptible to electromagnetic disturbances, due to a steady reduction in power supply voltage and, consequently, noise margin [2,3]. In particular, substrate noise can disturb the operation of an IC. This noise may originate from the external world or from other blocks inside the circuit. Therefore, susceptibility reduction techniques must take into account this substrate noise [4]. Several measurement methods have been developed, some of them standardised, to characterise the electromagnetic susceptibility of integrated circuits. In this paper, the direct power injection (DPI) method [5] will be used in order to inject a continuous-wave disturbance into the substrate of an IC. In the same manner as for emission, electrical models enabling the prediction of the immunity of an IC before tape-out would be profitable. Corresponding author. Tel.: + 33 2 4186 67 03.
E-mail address: [email protected] (A. Alaeldine). URL: http://perso.eseo.fr/~aalaeldine/ (A. Alaeldine). 0026-2692/$ - see front matter & 2009 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2009.10.004
An electrical model of a DPI setup has already been developed for an injection into the power rail of an IC [6]. However, it is not suited to substrate injection, due to the lack of a proper model taking into account, in a simplified manner, the dissipation of an electromagnetic disturbance into the substrate. This study is based on a specific IC (CESAME) including several emission reduction strategies [7]. The interest of these strategies for susceptibility reduction has already been pointed out [8], but only by the means of measurements. Consequently, this paper presents a comprehensive simulation model of the direct power injection into the substrate of an IC, and compares simulation results for these strategies with the ones previously obtained through measurements. The paper is organised as follows. First of all, the different logic cores of the test chip used in this study are described in Section 2. Then, the immunity measurement method is detailed in Section 3, with an emphasis on the modelling of the injection setup and the circuit under test including substrate models. Section 4 deals with a comparison between measurement and simulation results in order to validate the suggested model. Finally, Section 5 underlines the key points of this study.
2. Description of the test chip The test chip used in this study, called CESAME [9], has been developed by STMicroelectronics in 0:18 mm CMOS technology (die area: 11 mm2 ), specifically for the investigation of several EMI
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reduction techniques [7]. CESAME is composed of six logic cores which are identical from a functional point of view, but differing by their power supply strategies. Each core is composed of 240 identical base cells, each one including D flip–flops, a clock tree and standard gates, intended to reflect the activity of a typical digital core and each base cell consists of 400 transistors. This IC is mounted on a custom printed circuit board (PCB), called ALI [8]. These cores are built in an epitaxial substrate with a negligible horizontal resistance. In this paper, only three different cores (NORM, ISO and RC, surrounded in red in Fig. 1) out of six are used. Four cores (NORM, RC, NOR and GRID) are built in the global substrate of the IC, while the other ones (ISO and ISV) are built in local isolated substrates. NORM core: The only EMI protection strategy used in the NORM core consists of two small 1:7 O series resistors, one on each power supply rail. These resistors, along with the metal and MOS capacitances of the logic core, build up a RC filter, with a high cutoff frequency (about 200 MHz). ISO core: Another protection strategy is used for the ISO core. This core is embedded in its own local substrate, isolated from the rest of the chip thanks to a triple-well technique. The same Vdd rail is used for the sources of the upper PMOS transistors (in logic gates) and the polarisation of the local substrate. RC core: In this core, an additional 1-nF integrated decoupling capacitor is included between both supply rails. This distributed on-chip capacitor is made up of several poly1/poly2 capacitors, and increases the area of the RC core by 40% compared with the NORM core. By lowering the cutoff frequency of the RC filter (about 40 MHz), this technique allows the reduction of the power distribution noise arising from multiple drivers switching simultaneously [10]. GRID core: The GRID core, like the NORM core, only uses the series resistors as a protection technique. However, its power supply network is meshed on the highest (5 and 6) metal levels (hence the name), thus reducing the total power supply impedance. ISV core: The ISV core, like the ISO core, is built in a local isolated substrate. However, unlike in the ISO core, the Vdd of the PMOS transistors and the Vdd of the local substrate are separated on the die.
Fig. 1. CESAME test chip and the three cores under test (NORM, ISO and RC) in red. (For interpretation of the references to the colour in this figure legend, the reader is referred to the web version of this article.)
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NOR core: The NOR core is not fitted with 1:7 O series resistors. This is the simplest architecture available in the circuit, with no EMI protection strategy.
3. Direct power injection (DPI) method: set-up and modelling In order to characterise the behaviour of ICs to electromagnetic interference, several measurement methods are currently under standardisation process under the supervision of the International Electrotechnical Commission (IEC), one of which is the direct power injection (DPI) method [5]. This article introduces a complete electrical model of a DPI setup for substrate injection, making it possible to predict the immunity of an IC on a given printed circuit board (PCB) within the design phase. 3.1. Set-up of the injection system An example of DPI setup is displayed in Fig. 2. Continuous sinewave RF power (from 10 MHz to 1 GHz) delivered by a generator is fed into an amplifier and then injected into a pin of the IC under test (either a power pin or a signal input pin) through a capacitor blocking the DC voltage coming from the power supply (hence the name of the test). A directional coupler allows the measurement of incident and reflected powers by the means of a dual-input power metre. The output signal of the IC is monitored on an oscilloscope in order to check out the susceptibility of the circuit under test according to a given criterion which will be presented in this paper. Only the incident power will be used in this study in order to plot the measurement and simulation immunity curves of all aforementioned cores. For each frequency step, incident power is increased until a failure occurs (in time domain). It is then possible to establish a susceptibility plot, as a function of injected frequency, from these time-domain measurements or simulations. 3.2. Modelling of the injection system and the PCB The objective of the modelling process is the prediction of the immunity of the CESAME IC to EMI disturbances. A key point to the validation of the immunity model lies in the evaluation of the power actually injected into the circuit. Therefore, each part of the setup (injection probe, injection capacitor, PCB, IC including substrate, and directional coupler), except the active part (transistors) of the IC, must be modelled separately as a combination of equivalent passive elements; these individual models must then be combined in order to obtain the whole equivalent model. The first step is the injection system, each part (injection probe, connection between the probe and the GND of the PCB) of which was measured and modelled separately from
Fig. 2. DPI injection system.
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measurements obtained with the help of a vector network analyser (VNA). The model of the injection probe is inductive, with a low series resistance. This probe is attached to the IC under test through an injection capacitor of 1 nF, but its outer connector is soldered on the ground plane of the PCB. Consequently, the inner wire of the probe is coupled with the ground plane through a capacitance and a resistance, representing the dielectric of the coaxial cable. Moreover, the inductance of the small wire connecting the core of the cable with the IC pin is measured, its value is negligible. The DPI setup includes two discrete capacitors: a 1 nF injection capacitor, used to prevent the reinjection of the DC voltage supplied by the board into the RF power amplifier, and a 47 nF decoupling capacitor located on the PCB [11]. An accurate impedance measurement of these capacitors can be achieved s thanks to an Agilent N1020A probe connected to the VNA. These ceramic SMD capacitors can be modeled by a series RLC network. The same operation can be reiterated for the decoupling capacitor. The directional coupler used for power measurements can be identified as a 50 O lossless transmission line. Its propagation time Td is computed using Eq. (1): Td ¼ Z0 C0 ¼ 2471 ps
ð1Þ
in which C0 is measured with a VNA in Smith chart mode. The coupler has a very strong influence on the global impedance profile of the setup. Unfortunately, it is integrated in the power amplifier and can not be removed for DPI measurement purposes (only for impedance measurements). Therefore, the following simulations and measurements always take this coupler into account. Moreover, in this study, the DPI setup does not follow the standard proposal [5]. The custom-designed PCB (called ALI) includes its own power supply, composed of a 9 V battery and several regulators, including a 1.8 V regulator for the digital core and IOs of the IC, the only one to be modelled in this case. Conversely, the standard proposal requires the use of an external power supply, with a series choke inductor preventing the reinjection of RF power into the supply. The regulator, the battery and the PCB tracks (including vias) were modelled by series RLC networks. In particular, the inductances of the Vdd and Vss tracks, both located over a ground plane, were established thanks to Eq. (2) [12]: m ml 8h w þ ð2Þ LVdd ¼ LVss ¼ 0 r ln 2p w 4h in which l and w are respectively the length and the width of the track, h the distance between the track and the ground plane. On this PCB, w ¼ 300 mm and h varies between 0.5 and 1.5 mm depending on the routing layer.
3.3. Modelling of the integrated circuit package and bonding The CESAME circuit is encapsulated in a TQFP144 package. The electrical model of this package was obtained from a 3D s electromagnetic simulation with HFSSs (Ansoft ) [13]. In order to compute the inductances of the leadframe and the bonding, it can be noted that the Vdd and Vss pins are adjacent on the package, which implies that the current return path can be easily determined. Therefore, their equivalent inductances can be computed from Eq. (3) [12]: m ml 4h ð3Þ LVdd ¼ LVss ¼ 0 r ln 2p d in which l and d are respectively the length and the diameter of the leadframe or the bondwire, and h its distance to the ground plane.
Then, the CVdd=Vss coupling capacitance between both power supply rails can be computed from Eq. (4) [14]: " C12 ¼ e0 er l
2:22 0:64 # e 0:1 d e w d þ 1:21 þ 1:15 þ 0:54 þ 0:25ln 1 þ 7:17 d h h d h
ð4Þ In addition to that, intra-IC inductive coupling between Vdd and Vss is an important factor which widely influences the amount of RF power actually injected into the die [15]. The mutual inductance between both rails is given by Eq. (5), and the coupling factor by Eq. (6): " # m0 mr l ðd þ 4wÞ2 þ ð1:5w þ2hÞ2 ð5Þ ln MVdd =Vss ¼ 2p ðd þ wÞ2 þð1:5wÞ2 MVdd =Vss ffi KM ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffiffi LVdd LVss
ð6Þ
3.4. Modelling of CESAME cores As can be seen in the circuit description (paragraph 2), each logic core includes 240 identical base cells, each one composed of 400 transistors. In order to speed up time-domain simulation, only one base cell (reference cell) is included in the whole netlist [6]. The remaining cells are replaced by an equivalent parallel RC model representing the impedance of all CMOS transistors. This RC model is located in parallel with the reference cell. The reference cell is fed with a 20 MHz clock signal and a square 10 MHz data signal, and the output of the cell can be directly observed on an output pin of the chip. The parasitic elements of the pads and the on-die power supply rails are then modelled using the same methodology as the one used for the package. Moreover, the surface of the CESAME die is 11 mm2 , it is located about 1 mm above the ground plane, thus leading to an additional C_pcb ¼ 500 fF coupling capacitance between the substrate and the ground. By assembling all the models computed previously, a complete electrical SPICE model of the DPI setup can be established, which is depicted in Fig. 3. This full electrical model includes also the netlist of the reference cell which is identical in the three cores. Moreover, in this study, the power is injected through the Vss pin of the three cores NORM, ISO and RC, thus requiring accurate modelling of the own substrate of each core. 3.4.1. Substrate modelling for the NORM core In all cases, RF power is injected into the global substrate of the circuit via the Vss pin. As far as the NORM core is concerned, its substrate is actually the global substrate of the IC. As can be seen in Fig. 4 (top), the vertical resistance of the substrate is modelled and replaced by a resistor (R_epi_NORM). Then, the capacitive coupling between the substrate and the PCB ground is modelled by C_pcb. In addition to that, the IC includes five other cores, among which three (NOR, RC, GRID) are built in the global substrate. Another coupling between this substrate and the PCB ground is achieved through the package pins of these three cores; therefore, their Vss rail models must be included into the model. It can be noted that the coupling with the ISO and ISV cores, which are built in their own local substrate, can be neglected in firstorder approximation. Finally, the complete substrate model for the NORM core is displayed in Fig. 4 (bottom). The values of the passive devices in this model are displayed in Table 1. The model of the NORM substrate is then added to the complete model of the system under test are shown in Fig. 3. 3.4.2. Substrate modelling for the ISO core In the case of the ISO core, the NISO isolation layer between the local substrate of the core and the global substrate of the
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Fig. 3. Complete electrical model of the DPI setup.
Table 1 Device values for the substrate model (NORM core). Element
Value (O)
Element
Value
R_epi_NORM R_GRID R_RC R_NOR
30 30 30 30
C_pcb L_GRID L_RC L_NOR
500 fF 3.57 nH 3.67 nH 3.67 nH
integrated circuit CESAME must be taken into account. Consequently, two additional coupling capacitors are included [4]: the first one (C_pwell1) is located between the global P substrate and the NISO layer, while the second one (C_pwell2) is located between the isolation layer and the local Pwell substrate of the ISO core, as displayed in Fig. 5. Moreover, the resistive effect (R_nwell) of the N well of the Vdd pin is taken into account. Like in the NORM core model, a resistive value (R_epi_ISO) represents the resistance of the substrate; however, since the local substrate is thinner as the global substrate, its value is lower than the one of the NORM core. It can be noted that, at very high frequencies, this fact can have an adverse effect on shielding [4]. This time, four other cores (NOR, NORM, RC and GRID) are built in the global substrate. Consequently, the coupling with the PCB ground is achieved through four pins, with their inductance and resistance. The complete substrate model is shown in Fig. 5 (right), while the values of its elements are displayed in Table 2.
Fig. 4. Structure of an inverter of the NORM core (top) and electrical model of the substrate of the NORM core (bottom).
3.4.3. Substrate modelling for the RC core In the case of the RC core (built in the global substrate), the onchip decoupling capacitor is located between the Vdd and Vss power supply rails. It is modelled and replaced by two passive elements C_decoup and R_decoup in series. R_sub_RC, shown in
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Fig. 5. Structure of an inverter of the ISO core (top) and electrical model of the substrate of the ISO core (bottom).
Table 2 Device values for the substrate model (ISO core). Element
Value
Element
Value
R_epi_ISO C_pwell1
22 O 270 pF
R_nwell C_pwell2
2O 348 pF
Fig. 6, represents the substrate resistance seen from the Vdd power input. The same package coupling effect as for the NORM core can be observed with the three other cores built in the same substrate (NOR, NORM, GRID). Fig. 6 (bottom) represents the complete electrical model of the RC substrate which will be added to the whole electrical model of the system under test (Fig. 3). Device are displayed in the Table 3.
It can be noted that all cores are immune to a 10-W incident power below 60 MHz. Above this frequency, they are becoming more and more susceptible. Low- and high-immunity frequencies are almost identical between measurement and simulation results. Conversely, in the 460–640 MHz frequency range, the difference is greater then 6 dBm with the simulation being more ‘‘optimistic’’. These discrepancies may be due to power losses [16,17] which have not been included so far in the simulation model and still remain to be studied. Moreover, the peak observed at 679 MHz on the measurements of the three cores is due to the cavity resonance of the PCB. The cavity resonance is computed from Eq. (7) which provides the resonant frequency as a function of the relative permittivity of the PCB (FR4), its dimensions and its thickness: c Fm;n;p ¼ pffiffiffiffi 2 er
4. Results A first immunity simulation was performed from 10 MHz to 1 GHz. This time-domain simulation is performed for each frequency step (10 MHz); a failure in the IC is characterised by the ripple of the output signal reaching 20% of the logic ‘‘1’’ voltage level, or by the jitter of this output signal reaching 10% of the period [6]. Figs. 7–9 depict the comparison between experimental measurements [8] and simulation results of the immunity of the NORM, RC and ISO cores, respectively. The lower the injected power, the less immune the core.
rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi m2 n 2 p2 þ þ L W T
ð7Þ
in which L, W and T are respectively the length (10.3 cm), the width (10.3 cm) and the thickness (1.6 mm) of the board. er ¼ 4:6 represents the relative permittivity of the FR4 board. m, n and p represent mode indices. The values of the cavity resonance induced by the PCB are displayed in Table 4. Another effect that must be taken into account is due to the behaviour of inputs and outputs. They can be represented as series RLC networks, as depicted in Fig. 10. In this figure, CPMOS and CNMOS represent the drain-source capacitances of the driver transistors, Rio and Lio the equivalent passive elements (bonding and leadframes) of the pin itself. At
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Fig. 6. Structure of an inverter of the RC core (top) and electrical model of the substrate of the RC core (bottom).
Table 3 Device values for the substrate model (RC core). Element
Value
Element
Value (O)
R_epi_RC C_decoup
30 O 1 nF
R_sub_RC R_decoup
34 1
their resonant frequencies, an improvement on IC immunity can be observed due to the ‘‘decoupling’’ behaviour of the network.
5. Discussion and comparison among results 5.1. Measurement results The DPI experiment consists in injecting continuous power into the substrate pin of the NORM core. Since this core is implemented in the global substrate of the integrated circuit, the injected power is dissipated in the whole substrate. This substrate
noise has an influence, not only on the NORM core itself, but also on the other cores of the circuit. DPI measurements were performed from 10 MHz to 1 GHz in 10 MHz frequency steps. For each frequency, the injected power at which the integrated circuit becomes susceptible is recorded. The whole frequency plot is represented in Fig. 11 for each core. Different protection strategies were initially used to decrease the parasitic emission of these cores, but can be useful to increase their immunity as well. The deep N insulation layer between the global substrate and the local substrate of the ISO core lowers the coupling capacitance between both substrates. Hence, the susceptibility of the ISO core is generally lower than the one of the NORM core, particularly from 10 to 210 MHz. However, it can be noted that the ISO core is less immune than the NORM core between 400 and 500 MHz; this may be due to an antiresonance of the coupling capacitor with the passive elements of the power supply network. The RC core includes an on-chip decoupling capacitor between the Vdd and Vss power supply rails. This on-chip decoupling capacitor enhances the immunity of the RC core in comparison with the others, except between 500 and 650 MHz where the RC
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40
40 Measurement Simulation
Measurement Simulation
35 Injected power (dBm)
Injected power (dBm)
35
30
25
20
30
25
20
15
DPI into the substrate of the RC core: −Output signal susceptibility
DPI into the substrate of the NORM core: −Output signal susceptibility
15
10 0
100
200
300
400
500
600
700
800
0
900 1000
100 200 300 400 500 600 700 800 900 1000
Frequency (MHz) Fig. 7. Immunity of the NORM core: measurement (solid) and simulation (dotted).
40 Measurement Simulation
Injected power (dBm)
35
30
Frequency (MHz) Fig. 9. Immunity of the RC core: measurement (solid) and simulation (dotted).
Table 4 Values of the cavity resonance induced by the PCB. m
n
p
L (mm)
W (mm)
T (mm)
er
Cavity resonance (MHz)
1 0
0 1
0 0
103 103
103 103
1.6 1.6
4.6 4.6
679 679
25
20
15 DPI into the substrate of the ISO core: −Output signal susceptibility 10 0
100 200 300 400 500 600 700 800 900 1000 Frequency (MHz)
Fig. 8. Immunity of the ISO core: measurement (solid) and simulation (dotted).
core is less immune than the ISO core; likewise, an antiresonance of the capacitor with the power supply network may explain this behaviour. In high frequency (above 650 MHz), the ISO and RC cores have similar susceptibility levels except at 780 MHz.
5.2. Simulation results Another interesting result consists in comparing simulation results for the three cores in the same figure (Fig. 12), in order to assess the relative efficiencies of the protection strategies and compare them with the ones obtained from measurements. The main explanation for the discrepancy between simulations and measurements may come from the non-inclusion of the layoutrelated parasitics of the chip (not available from the foundry) into the IC model. Consequently, propagation and transition times are identical for all circuit gates. Although the rise and fall times of the pulse generators were identical in both cases, simulations bear a much more ‘‘regular’’ pattern than measurements. Previous studies [18] have pointed out the efficiency of substrate noise
Fig. 10. Equivalent model of an I/O.
reduction techniques. Moreover, measurements for the three cores under test have already been presented in [19,8]; they demonstrated that the RC core is the most immune to DPI, followed by the ISO core and, finally, the NORM core. As far as simulations are concerned, it is important to notice that the hierarchy among the three cores is exactly identical. This result thus confirms the previous studies conducted on this topic.
6. Conclusion A comprehensive simulation model of direct power injection into the substrate of an integrated circuit, including the substrate coupling paths, has been presented in this paper as an extension of the ICEM model. The suggested substrate models can be added to the existing setup model, making it possible to perform immunity simulations. Moreover, the classification obtained from simulations for these strategies matches the one obtained from
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40 NORM ISO RC
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fabricated, with several analogue and digital integrated blocks and new shielding methods, in order to study the efficiency of these techniques on external and internal immunities.
35 Injected power (dBm)
References 30
25
20
15 DPI into the substrate of CESAME test chip: − Output signal susceptibility
10 0
100 200 300 400 500 600 700 800 900 1000 Frequency (MHz)
Fig. 11. Comparison among the measured immunities of the NORM, ISO and RC cores.
40 Simulation: NORM core Simulation: ISO core Simualtion: RC core
Injected power (dBm)
35
30
25
20 DPI into the substrate of the three cores (NORM, ISO and RC): −Output signal susceptibility
15 0
100 200 300 400 500 600 700 800 900 1000 Frequency (MHz)
Fig. 12. Comparison among the simulated immunities of the NORM, ISO and RC cores.
measurements, and demonstrates that the integrated decoupling capacitor seems to be the best EMI protection method against external sources of substrate noise. In the future, substrate noise injection will be applied into another test chip which will be specifically designed and
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