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A design of low swing and multi threshold voltage based low power 12T SRAM cell
Computers and Electrical Engineering xxx (2014) xxx–xxx
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Computers and Electrical Engineering journal homepage: www.elsevier.com/locate/compeleceng
A design of low swing and multi threshold voltage based low power 12T SRAM cell q P. Upadhyay a,1, R. Kar a,⇑, D. Mandal a,2, S.P. Ghoshal b,3 a b
Department of Electronics and Communication Engg., National Institute of Technology, Durgapur, West Bengal 713209, India Department of Electrical Engg., National Institute of Technology, Durgapur, West Bengal 713209, India
a r t i c l e
i n f o
Article history: Received 15 June 2014 Received in revised form 25 October 2014 Accepted 27 October 2014 Available online xxxx Keywords: Charge sharing Leakage Low power Static noise margin SRAM Swing voltage
a b s t r a c t This paper focuses on the design of a novel low power twelve transistor static random access memory (12T SRAM) cell. In the proposed structure two voltage sources are used, one connected with the bit line and the other one connected with the bitbar line in order to reduce the swing voltage at the output nodes of the bit and the bitbar lines, respectively. Reduction in swing voltage reduces the dynamic power dissipation when the SRAM cell is in working mode. Low threshold voltage (LVT) transmission gate (TG) and two high threshold voltage (HVT) sleep transistors are used for applying the charge recycling technique. The charge recycling technique reduces leakage current when the transistors change its state from sleep to active (OFF to ON condition) and active to sleep (ON to OFF condition) modes. Reduction in leakage current causes the reduction in static power dissipation. Stability of the proposed SRAM has also improved due to the reduction in swing voltage. Simulation results of power dissipation, access time, current leakage, stability and power delay product of the proposed SRAM cell have been determined and compared with those of some other existing models of SRAM cell. Simulation has been done in 45 nm CMOS environment. Microwind 3.1 is used for schematic design and layout design purpose. Ó 2014 Elsevier Ltd. All rights reserved.
1. Introduction The demand of battery operated high speed portable devices like notebook, laptop computers, personal digital assistants, cellular phones, etc. increase day by day. High speed portable devices require primary memory that responds faster. For that purpose, static random access memory (SRAM) is used, which is faster and refreshing is not needed again and again. Dynamic power dissipation and leakage current are the main issues of high speed SRAM cells because this unwanted power dissipation reduces the battery backup life of portable devices. So it is required to have a SRAM cell design, having both low static and dynamic power dissipations.
q
Reviews processed and recommended for publication to the Editor-in-Chief by Associate Editor Dr. Srinivasan Rajavelu.
⇑ Corresponding author. Tel.: +91 9434788056.
E-mail addresses: [email protected] (P. Upadhyay), [email protected] (R. Kar), [email protected] (D. Mandal), spghoshalnitdgp@ gmail.com (S.P. Ghoshal). 1 Tel.: +91 9805406546. 2 Tel.: +91 9434788059. 3 Tel.: +91 9434788110. http://dx.doi.org/10.1016/j.compeleceng.2014.10.020 0045-7906/Ó 2014 Elsevier Ltd. All rights reserved.
Please cite this article in press as: Upadhyay P et al. A design of low swing and multi threshold voltage based low power 12T SRAM cell. Comput Electr Eng (2014), http://dx.doi.org/10.1016/j.compeleceng.2014.10.020
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Supply voltage is scaled to maintain the power consumption within limit. However, scaling of supply voltage is limited by the high performance requirement. Hence, the scaling of supply voltage only may not be sufficient to maintain the power density within limit, which is required for power sensitive applications. Circuit techniques and system level techniques are also required along with supply voltage scaling to achieve low power designs [1]. Aggressive scaling of the devices not only increases the subthreshold leakage but also has other negative impacts such as increased drain induced barrier lowering (DIBL), threshold voltage (Vth) roll off, reduced on current to off current ratio, and increased source to drain resistance [2]. Vth roll off increases the dependence of Vth on the channel length. A small variation in channel length might result in large threshold voltage variation, which makes device characteristics unpredictable. To avoid these short channel effects, oxide thickness scaling and higher and non uniform doping need to be incorporated [3] as the devices are scaled. The low oxide thickness gives rise to high electric field, resulting in considerable direct tunnelling current [4]. Higher doping results in high electric field across the reverse biased p–n junctions (source-substrate or drainsubstrate) which cause significant band to band tunnelling (BTBT) of electrons from the valence band of the p region to the conduction band of the n region. Peak halo doping (P+) is restricted such that the BTBT component is maintained reasonably small compared to the other leakage components. In another technique [5], a low area overhead adaptive body bias (ABB) circuit is proposed to compensate for aging and process variations to improve the SRAM reliability and yield. The proposed ABB circuit consists of a threshold voltage sensing circuit and an on chip analog controller for power reduction. A multi threshold complementary metal oxide semiconductor (MTCMOS) technology provides low leakage and high performance operation by utilizing high speed, low threshold voltage (LVT) transistors during active mode and low leakage, high threshold voltage (HVT) transistors during sleep mode, which reduces the static power dissipation of the SRAM circuit [6,7]. In [8], a technique to reduce both the active and standby powers, especially at room temperature, has been discussed. A bit line power calculator is used to adaptively set the cell supply voltage in the active mode. A digitally controllable retention circuit regulates in the standby mode with small control power. These circuits are implemented in a dual power supply SRAM in 28 nm CMOS technology. In another approach a 5T SRAM cell is proposed with fast performance, high density and low power consumption [9]. The proposed complementary metal oxide semiconductor (CMOS) SRAM cell consumes less power and has less read and write times. The cell is based on the single ended memory storage principle. This scheme is based on the static power reduction. In [10], a symmetrical topology based SRAM cell has been proposed for higher stability. In that two transistors isolate the cell storage nodes from the read operation path to maintain the data stability of the cell. This topology improves the data stability. A low power multiport SRAM with cross point write word lines shared write bit lines and shared write row access transistors approach has been shown in [11]. The design has one write, one read and two write, two read multi port SRAMs for register file applications in nanoscale CMOS technology. The cell features a cross point write word line structure to mitigate write half select disturb and improves the static noise margin (SNM). The write bit lines (WBLs) and write row access transistors are shared with adjacent bit cells to reduce the cell transistor count and area. The scheme halves the number of WBL, thus reducing WBL leakage and power consumption. In addition, column based virtual ground control is employed for the read stack to reduce the read power consumption. In [12], SRAM cell achieves low power dissipation due to its series connected drivers driven by bit lines and read buffers which offer stack effect. This approach is based on static power dissipation. In this present work a novel low power 12T SRAM cell is proposed. A charge recycling technique is used to minimize the leakage currents and static power dissipation during the mode transitions. Two voltage sources are used at the output nodes to reduce the swing voltages, resulting in reduction of dynamic power dissipation during switching activity. The different performance parameters have been determined for the proposed SRAM cell and compared with those of the other existing SRAM cells. The paper is organized as follows: Section 2 discusses about some existing SRAM cells, Section 3 describes circuit design and working principle of the proposed novel 12T SRAM cell. Section 4 describes the detailed analysis of the characteristics of the proposed cell and comparison with other existing SRAM cells and finally, Section 5 concludes the paper.
2. Existing SRAM cells Fig. 1(a) shows the circuit diagram of a conventional SRAM cell [13]. Before the read operation begins, the bit line (BL) and bitbar line ðBLÞ are precharged to as high as supply voltage Vdd. When the word line (WL) is selected, the access transistors are turned on. This will cause a current to flow from supply voltage (Vdd) through the pull up transistor TP1 of the node storing ‘‘1’’. On the other side, current will flow from the precharged bitbar line to ground, thus discharging bitbar line. Thus, a differential voltage develops between the BL and BL. This small potential difference between the bit lines is sensed and amplified by the sense amplifiers at the data output. The 6T single ended SRAM cell [14] is shown in Fig. 1(b). This cell design uses two assist transistors, one for the memory read access (MRA) purpose and the other for the memory write access (MWA) purpose. During write operation, with the BL precharged to required value, write word line (WWL) is held high and MWA is held OFF so as to weaken the cross coupled inverter and hence, get a successful write. During read, read word line (RWL) is held high and read occurs through M6 and MRA depending upon the value stored at the node QB. Please cite this article in press as: Upadhyay P et al. A design of low swing and multi threshold voltage based low power 12T SRAM cell. Comput Electr Eng (2014), http://dx.doi.org/10.1016/j.compeleceng.2014.10.020
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Fig. 1. Different existing SRAM cells.
Please cite this article in press as: Upadhyay P et al. A design of low swing and multi threshold voltage based low power 12T SRAM cell. Comput Electr Eng (2014), http://dx.doi.org/10.1016/j.compeleceng.2014.10.020
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The 7T SRAM [15] is shown in Fig. 1(c). Here this design uses two virtual ground rails. During write operation, the cell is disconnected from the ground rail by turning OFF the MW transistor (connected to virtual ground 1) and hence weakening the feedback in the cell and helps in faster write. During hold mode, MW transistor is held ON so that the strong feedback exists. During read, memory write (MW) and read word line (RWL) are held high; the node Q is read through the memory read (MR) (connected to virtual ground 2) transistor. This uses a separate read bit line to be read and hence has a very good read static noise margin (RSNM). Subthreshold 7T SRAM is shown in Fig. 1(d); it has single sided write operation [16]. The Write Bit line and M5 transistor are used to transfer new data (1 bit) into the cell. Single sided write operation reduces dynamic power consumption while besides that, read path is separated from the storage nodes, which increases the noise margin drastically. Transistors M6, M7 are used for reading the cell data. Standby leakage is minimized by connecting transistor M7 to virtual ground. The 8T SRAM cell [17] is shown in the Fig. 1(e). This cell uses the same 6T SRAM structure for the writing operation. For read operation, it uses separate bit lines, read bit line (RBL) and read word line (RWL) as its control signals. During write operation, the PMOS and NMOS transistors of the inverters can be maintained with minimum widths as the read operation is separated. The RBL is read according to the value stored at the storage nodes when RWL is high. The vertical stacked 8T SRAM cell [18] is shown in Fig. 1(f). In this architecture resistive devices (memristors) are connected directly to SRAM storage nodes (Q and QB), to enable the storage of complementary backup data, while maintaining nonvolatile characteristics. This sharing scheme enables word line transistors RSWL and RSWR, to provide SRAM mode write assist functions beyond its original storage capability. To reduce area overhead, the two memristor devices are vertical stacked above the 8T SRAM cell. The 9T SRAM [19] is shown in Fig. 1(g). Write occurs just as in the 6T SRAM cell. Reading occurs separately through N5, N6 and N7 controlled by the read signal (RD) going high. This design has the problem of the high bit line capacitance with more pass transistors on the bit line. Fig. 1(h) shows the design of 9T SRAM cell in subthreshold region [20]. During write, the bit lines (BL) and bit line bar (BLB) are driven with the data that are needed to be stored in the nodes. The footer M9 transistor is switched OFF during write by making the signal (write/read) WR go low. This weakens the feedback and hence faster writes. During read, WR signal is kept high so that the data at the nodes stay stable. Word line (WL) is kept low and read bit line (RBL) is precharged high. Reading a stored 0 at Q occurs when read word line (RWL) goes high. During the hold mode, WL and RWL are made low with WR made high to maintain the stored data. A single ended 9T SRAM cell [21] is shown in Fig. 1(i). The 9T SRAM cell consists of transistors M1-M4, and a Read/Write port M5-M9. The word line (WL) and virtual ground (VVSS) are row based, and write word line A (WWLA), write word line B (WWLB), and Bit line (BL) are column based. In Hold mode, WL, WWLA, and WWLB are disabled and VVSS is held at supply voltage (Vdd). Data are held by cross coupled inverters, M1–M4, and are decoupled from BL. The fully differential low power 10T SRAM [22] bit cell is shown in Fig. 1(j). The design strategy of cell is the series connection of a tail transistor. The gate electrode of this device is controlled by the output of an XOR gate, inputs of which are tapped from write word line (WWL) and read word line (RWL) control signals coming from the WWL and the RWL drivers. The XOR gate and the tail transistor are shared by all the cells in a row. The tail transistor has to be appropriately up sized for sinking currents from all the cells in the row. Without this read buffer, a cell with such small drivers and series connected tail transistor would exhibit unacceptably low read static noise margin (RSNM), resulting in read instability. A P–P–N based differential 10T SRAM cell [23] is shown in Fig. 1(k). In addition to the standard 6T SRAM cell with VDD, GND, one word line, and one bit line pair, one extra signal called VGND, denoting a virtual ground signal. This VGND signal is connected to GND only during the read operation. Otherwise, it is connected to VDD. This cell is called P–P–N based since each of the cross coupled inverters is composed of three transistors cascaded in a P–P–N sequence from top to bottom. The nodes between the two cascaded PMOS transistors are called pseudo storage nodes (including pQ and pQb in Fig. 1(k)), which are separated from the true storage nodes (named Q and Qb in Fig. 1(k)). In addition to the inverter pair, there is a discharging path on each side of this SRAM cell, each of which is formed by an access transistor plus some pull down transistors that connect a pseudo storage node to the VGND. The left hand side discharging path is formed by PGL (Pass Gate Left) and PDL1 (Pull Down Left 1). The discharging path is used to discharge a precharged high bit line during the read operation. The 11T SRAM [24] is shown in Fig. 1(l). Here the cell disconnects the node to which a logical HIGH is to be written from the ground and hence facilitates the write faster. In case of reading, it uses a separate read bit line and N5, N2, N8 and N9 are ON and hence N9 and N8 give low effective resistance to the read operation and hence faster read.
3. Proposed 12T SRAM cell In order to overcome the problem associated with conventional SRAM cells and other existing SRAM cells, the authors proposes a multi threshold complementary metal oxide semiconductor (MTCMOS) based 12T SRAM architecture to achieve low static and dynamic power dissipations for read and write operations and better stability. In the proposed design two voltage sources V1 and V2 are connected to the outputs of the bit line (BL) and bitbar line ðBLÞ, respectively. Two NMOS transistors VT1 and VT2 are used, one connected with the BL and the other with the BL directly to switch ON and switch OFF the voltage sources during write operations. The voltage sources reduce the swing voltage during write ‘0’ and write ‘1’ operation at higher frequencies. This reduction in swing voltage reduces the dynamic power dissipation. The two high threshold Please cite this article in press as: Upadhyay P et al. A design of low swing and multi threshold voltage based low power 12T SRAM cell. Comput Electr Eng (2014), http://dx.doi.org/10.1016/j.compeleceng.2014.10.020
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voltage (HVT) sleep transistors S1 and S2 are used. NMOS sleep transistor S1 connects node M (also called virtual ground node) to ground whereas the PMOS sleep transistor S2, connects node N (also called the virtual supply node) to Vdd supply. The low threshold voltage (LVT) transmission gate (TG) is connected between the two virtual nodes M and N for providing charge sharing. The proposed design is illustrated in Fig. 2. Sleep transistor control signal (ST) and charge sharing control signal (CS) provide the switching activity control on sleep transistors and transmission gate, respectively. Sleep transistors disconnect logic cells from the supply and/or ground. Charge recycling technique reduces the leakage current while transistors flip its mode from active to sleep and sleep to active. Reduction of leakage current reduces the static power dissipation. 3.1. Operation of sleep transistor Consider the configuration shown in Fig. 2. NMOS sleep transistor S1 connects the virtual ground, i.e., node M in Fig. 2, to the actual ground, whereas the other PMOS sleep transistor S2 connects the virtual supply, i.e., node N in Fig. 2, to the actual Vdd supply. During the active period, both sleep transistors S1 and S2 are in the linear region and the voltage values of the virtual ground node M and virtual supply node N are equal to 0 and Vdd, respectively. 3.1.1. Transition from active mode to sleep mode During the transition from active mode to sleep mode of the sleep transistors S1 and S2, the transistors are turned OFF, and since they are chosen to be high threshold (VT) devices, they allow very little subthreshold leakage currents to flow through them. Thus virtual nodes M and N are floating during the sleep period. Now, if the duration of the sleep period is sufficiently long, virtual ground node (M) will be charged up to some voltage value very close to Vdd (supply voltage) by the very small leakage current flowing through T3 (with T1 is ON). Similarly, if the duration of the sleep period is long enough, virtual supply node (N) will be discharged to some voltage value very close to 0 by the very small leakage current flowing through T4 (with T6 is ON). If we denote the total capacitance in the virtual ground node M and virtual supply node N by CM and CN, respectively, it is observed that during the active to sleep transition, CM is charged up from 0 to very closely Vdd while CN is discharged from Vdd to very closely 0.
Fig. 2. The proposed 12T SRAM cell.
Please cite this article in press as: Upadhyay P et al. A design of low swing and multi threshold voltage based low power 12T SRAM cell. Comput Electr Eng (2014), http://dx.doi.org/10.1016/j.compeleceng.2014.10.020
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3.1.2. Transition from sleep mode to active mode During the transition from sleep mode to active mode of the sleep transistors S1 and S2, the transistors are tuned ON. The voltage of virtual ground node (M) starts to fall toward 0, whereas the voltage of virtual supply node (N) starts to rise toward Vdd. Thus, CM will be discharged from Vdd to 0, while CN will be charged to Vdd from its initial value 0. These charging and discharging events on the virtual ground and virtual supply nodes produce wasteful static power dissipation from the circuit power dissipation point of view, which is equal to (CM V2dd + CN V2dd) for one complete cycle of write ‘‘1’’ and write ‘‘0’’ operations. To overcome this problem charge recycling technique has been introduced. 3.2. Operation of charge recycling technique So, to reduce the static power dissipation during switching between active and sleep modes of the circuit, a charge recycling technique [25,26] is used by employing a transmission gate TG between the virtual ground (M) and virtual supply (N) nodes, as shown in Fig. 2. The charge recycling strategy works as follows for active to sleep and sleep to active mode. 3.2.1. Transition from active mode to sleep mode Before active to sleep transition of the sleep transistors, the TG is turned ON first. Then, the voltage of M node or the capacitance CM will rise from 0 to A Vdd (A < 1), not closely Vdd (which occurs for active to sleep transition of the sleep transistors. Similarly, the voltage of N node or the capacitance CN will fall from Vdd to A Vdd, not closely 0 which occurs for active to sleep transition of the sleep transistors. Then active to sleep transition signal ST is applied to the sleep transistors. Now the voltage of M node or the capacitance CM will raise from A Vdd to closely Vdd and the voltage of N node or the capacitance CN will fall from A Vdd to closely 0, provided necessary sleep period is allowed. The common voltage value of nodes M and N after charge sharing is calculated by equating the total charge in both the capacitances before and right after charge recycling as follows in (1).
C N V dd ¼ ðC M þ C N Þ V write1
ð1Þ
Therefore,
V write1 ¼ C N V dd =ðC M þ C N Þ ¼ A V dd
ð2Þ
where A = CN/(CM + CN); CM = Capacitance at node M; CN = Capacitance at node N; Vdd = power supply voltage. The common voltage value of the virtual ground M node and virtual supply node N at the end of the charge sharing is AVdd. If the energy consumptions in the sleep transistors and TG are neglected, the energy drawn from the supply by charging of capacitance CM = CM Vdd (Vdd A Vdd) = (1 A) CM V2dd. Therefore, total energy dissipation for operation = A CM V2dd. 3.2.2. Sleep to active mode Before sleep to active transition of the sleep transistors, the TG is turned ON first. Then, the voltage of M node or the capacitance CM will fall from closely Vdd to B Vdd (B < 1), not 0 (as it occurs without charge recycling). Similarly, the voltage of N node or the capacitance CN will rise from closely 0 to B Vdd, not Vdd (as it occurs without charge recycling). Then sleep to active transition signal ST is applied to the sleep transistors. Now the voltage of M node or the capacitance CM will fall from B Vdd to 0 and the voltage of N node or the capacitance CN will rise from B Vdd to Vdd. The common voltage value of nodes M and N after charge sharing is calculated by equating the total charge in both the capacitances before and right after charge recycling, which is given in (3).
C M V dd ¼ ðC M þ C N Þ V write0
ð3Þ
Therefore,
V write0 ¼ C M V dd =ðC M þ C N Þ ¼ B V dd
ð4Þ
where B = CM/(CM + CN); CM = Capacitance at node M; CN = Capacitance at node N. The common voltage value of the virtual ground M node and virtual supply node N at the end of the charge sharing is BVdd. If the energy consumptions in the sleep transistors and TG are neglected, the energy drawn from the supply by charging of capacitance CN = CN Vdd.(Vdd B Vdd) = (1 B) CN V2dd. Therefore, the total energy dissipation for operation = B CN V2dd. 3.3. Energy saving ratio and static power dissipation The total energy dissipation during the transitions of active mode to sleep mode and sleep mode to active mode is shown in (5).
Etotal ¼ A C M V 2dd þ B C N V 2dd
ð5Þ
Energy saving ratio (ESR) due to charge recycling is ratio of total energy dissipated with charge recycling technique to the total energy dissipated without charge recycling technique, as shown in (6). Please cite this article in press as: Upadhyay P et al. A design of low swing and multi threshold voltage based low power 12T SRAM cell. Comput Electr Eng (2014), http://dx.doi.org/10.1016/j.compeleceng.2014.10.020
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ESR ¼ ðA C M V 2dd þ B C N V 2dd Þ=ðC M V 2dd þ C N V 2dd Þ
7
ð6Þ
Substituting the values of A and B in (6) and substituting for X = CM/CN, one can get
ESRðXÞ ¼ 2X=ð1 þ XÞ2
ð7Þ
The optimum value for X which maximizes ESR(X) is obtained by equating the derivative of this ratio to zero, which results in X = 1, or CM = CN. In other words, in order to obtain the best energy saving, one needs to have equal capacitances in virtual ground and virtual supply nodes. Then the maximum energy saving can be obtained by putting the value of X = 1 in (7) and one gets energy saving ratio (ESR) = 0.5. This means that a maximum energy saving of 50% can be obtained by using the charge recycling method. However, considering the power needed to turn ON or OFF the TG, the total saving ratio is less than 50%. This energy directly related to the current as shown in (8).
Energy ¼ Voltage Current Time
ð8Þ
So from (8), if the supply voltage and the time are held constant then the current is directly related to energy. So as the current dissipation (leakage or unwanted current) in the SRAM cell is reduced during transition modes (active to sleep and sleep to active), the energy reduces. This reduction in leakage current reduces the static power dissipation of SRAM cell according to [27]is given in (9).
Pstatic ¼ Ileakage :V dd
ð9Þ
So, from (7-9), it is clear that the charge recycling technique reduces the energy dissipation and this reduces the current leakage during transition modes and reduction in leakage current finally causes the reduction of static power dissipation of the proposed SRAM cell. 3.4. Dynamic power dissipation by using voltage sources During the write ‘0’ operation, bit line (BL) is low and bitbar line ðBLÞ goes high. So the transistor VT2 is ON and the transistor VT1 goes to OFF condition. Thus the voltage source V2 forces the voltage swing to decrease at the output of the BL line. Similarly, when the write ‘1’ operation is performed, the transistor VT1 is ON and the transistor VT2 goes to OFF condition, so the voltage source V1 decreases the voltage swing at the output of the bitbar line (BL) line. The analog simulation diagram for write operations is shown in Fig. 3. During switching activity from ‘‘0’’ to ‘‘1’’ or ‘‘1’’ to ‘‘0’’ at bit line (BL) or bitbar line ðBLÞ, swing voltage is required. This extra voltage increases the dynamic power dissipation shown in (10). The dynamic power may be expressed as [27]
Pdynamic ¼ aCV dd V Swing f
ð10Þ
where C = load capacitance; a = activity factor; f = clock frequency; VSwing = voltage swing at the output node; Vdd is the power supply voltage.
Fig. 3. Analog simulation diagram of the proposed 12T SRAM cell.
Please cite this article in press as: Upadhyay P et al. A design of low swing and multi threshold voltage based low power 12T SRAM cell. Comput Electr Eng (2014), http://dx.doi.org/10.1016/j.compeleceng.2014.10.020
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So from (10), as the frequency increases the switching activity also increases and this increases the dynamic power dissipation. But voltage sources V1 and V2 reduce voltage swings simultaneously at the outputs. So as the frequency increases, simultaneously the swing voltage decreases. Due to that, at higher frequency the dynamic power dissipation is found to be almost constant for the proposed SRAM cell. Stability of the proposed SRAM cell also improves because voltage sources provide better switching capability.
3.5. Effect of size of transmission gate Sizing of the transmission gate (TG) is a factor that affects the energy saving ratio (ESR) as well as the wake up time (voltage rise time after sleep) of the circuit. In case of the original 8T configuration with sleep transistors, when there is no charge recycling, the wake up time may be defined as the time between turning ON of the sleep transistors and the voltage of the virtual ground reaching within 10% of its final value. However, in a circuit that uses charge recycling, the wake up time may be defined as the time between when the TG is turned ON to when the virtual ground voltage goes below 10% of its final value. In each active sleep active cycle, the TG is needed to be switched ON twice; once before turning the sleep transistors ON, and once after turning them OFF. Every time TG is turned ON, both the NMOS and PMOS transistors in the TG are actually turned ON, i.e., the capacitance is switched two times more. Clearly, TG is turned OFF after the charge sharing is complete. Therefore, the static power consumption of the TG for one complete active sleep cycle can be calculated. Therefore, to calculate the actual energy saving ratio (ESR), one needs to subtract the correction ratio from the ideal ESR. This correction ratio is proportional to the size of the TG. By increasing the size of the TG, the charge sharing process can be speeded up, and as a result it reduces the wake up time; however, this will also increase the correction ratio hence, decreasing the energy saving ratio of the circuit. Therefore, there is a trade off between the wake up time and energy saving ratio. In Fig. 3, left half of the diagram from time 0 ns to 2.5 ns shows the write ‘‘1’’ operation. Similarly, the next half from time 2.5 ns to 5 ns shows the write ‘‘0’’ operation. Bit line (BL), bit line bar (BBL), word line (WL), charge sharing control (CS) and sleep transistor control (ST) signals show inputs and bit line output (BL_OUT) and bitbar line output (BBL_OUT) signals show outputs during write operation. For write ‘‘1’’ operation, BL = High (1 V), BBL = Low (0 V), ST = Low, WL = High and CS = High (after 1 ns it goes low again) are applied as inputs. After simulation operation the output shows BL_OUT = High and BBL_OUT = Low. Similarly, for write ‘‘0’’ operation, BL = Low, BBL = High (0 V), ST = High, WL = High and CS = high (after 1 ns it goes low again) are applied as inputs. After simulation operation the output shows BL_OUT = Low and BBL_OUT = High. The Layout designs of 8T SRAM cell and the proposed SRAM cell are shown in Figs. 4 and 5, respectively. The layout design is based on the k rules. Here the value of k is equal to half of the length of transistors used in the standard foundry. Because the number of transistors in the proposed SRAM cell is more, the layout area for the proposed SRAM cell is larger than those of other existing SRAM cells but lesser power and better stability in the proposed SRAM can easily dominate over this drawback.
4. Results and discussions In this section power dissipation, static noise margin, access time, current leakage and power delay product are computed for the proposed 12T SRAM cell and the simulation results are compared with those of other existing SRAM cells. Analog and
Fig. 4. Layout diagram of 8T SRAM cell.
Please cite this article in press as: Upadhyay P et al. A design of low swing and multi threshold voltage based low power 12T SRAM cell. Comput Electr Eng (2014), http://dx.doi.org/10.1016/j.compeleceng.2014.10.020
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Fig. 5. Layout diagram of the proposed 12T SRAM cell.
Table 1 Parameters used for simulation. Tool for schematic design Tool used for analog simulation CMOS technology Supply voltage Transistors width (W)
Transistors length (L) Threshold voltage for sleep transistors
Microwind 3.1 BSiM4 45 nm 1.0 V T1 and T4 T2 and T5 T3 and T6 VT1 and VT2 Sleep NMOS S1 Sleep PMOS S2 TG NMOS TG PMOS 45 nm for all the transistors 0.614 V
75 nm 115 nm 175 nm 350 nm 350 nm 500 nm 350 nm 500 nm
schematic simulations have been done in 45 nm environment with the help of Microwind 3.1 by using BSimM4 model. Table 1 shows the different parameters used for the simulation purpose. 4.1. Power dissipation The total power dissipation in a SRAM circuit consists of two components, the static power dissipation and dynamic power dissipation. Many SRAM circuit techniques have been proposed to reduce these components. For dynamic power dissipation there are two components. One is the switching power due to charging and discharging of load capacitance. The other is the short circuit power due to the nonzero rise and fall times of input waveforms. The switching power of a single gate is expressed in (9). Static power dissipation is due to current leakage. There are three dominant components of leakage in a MOSFET in the nanometer regime. The first one is subthreshold leakage which is the leakage current from drain to source. The second component is direct tunnelling gate leakage which is due to the tunnelling of electrons (or holes) from the bulk silicon through the gate oxide potential barrier into the gate and the third ones are source/substrate and drain/substrate reverse biased p–n junction leakage currents called reverse saturation currents. Table 2 shows the comparison of static power dissipation and dynamic power dissipation for write and read operations of the proposed 12T SRAM cell with the existing SRAM cells. The proposed SRAM dissipates the least static power and dynamic powers as 2.895 lW and 3.734 lW, respectively, during write operation. Similarly, for read operation the proposed SRAM dissipates 1.893 lW and 2.736 lW, which are the least static power and dynamic power, respectively. Please cite this article in press as: Upadhyay P et al. A design of low swing and multi threshold voltage based low power 12T SRAM cell. Comput Electr Eng (2014), http://dx.doi.org/10.1016/j.compeleceng.2014.10.020
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Table 2 Comparison power dissipation. SRAM cells
Static power dissipation for write operation (lW)
Dynamic power dissipation for write operation (lW)
Static power dissipation for read operation (lW)
Dynamic power dissipation for read operation (lW)
Conventional 6T [13] 6T single ended [14] 7T [15] Sub threshold 7T [16] 8T [17] Vertical stacked 8T [18] 9T [19] 9T in sub threshold region [20] Single ended 9T [21] Fully differential 10T [22] PNP based differential 10T [23] 11T [24]
6.263 4.478 3.362 3.119 5.945 3.038 6.117 5.265 4.158 4.021 4.190 3.867
9.234 7.178 6.924 6.374 8.478 6.158 7.901 6.156 5.789 5.923 5.895 4.957
7.731 4.399 4.472 3.293 5.126 3.283 5.992 3.034 3.731 2.836 2.246 2.038
6.967 4.571 5.345 5.171 6.179 4.321 7.901 5.150 4.978 4.149 3.957 3.598
Proposed 12T
2.895
3.734
1.893
2.736
Fig. 6. Butterfly curve for calculation of SNM.
Table 3 Comparison of static noise margin. SRAM cells
Write static noise margin (mV)
Read static noise margin (mV)
Conventional 6T [13] 6T Single ended [14] 7T [15] Sub threshold 7T [16] 8T [17] Vertical stacked 8T [18] 9T [19] 9T in Sub threshold Region [20] Single ended 9T [21] Fully differential 10T [22] PNP based differential 10T [23] 11T [24]
196.31 201.45 267.54 246.87 257.83 279.03 256.10 239.57 249.50 289.33 293.49 314.29
206.27 221.67 288.62 269.30 281.29 293.51 278.90 250.16 268.57 290.23 311.10 334.56
Proposed 12T
421.56
436.58
4.2. Static noise margin SNM is the noise stability measure of the SRAM cell and is defined as the minimum dc noise voltage necessary to change the state of the SRAM cell. SNM is computed as the side length of a maximum square nested between the two voltage transfer characteristic (VTC) curves of the SRAM cell (i.e., one VTC for the bit line inverter and the other VTC for the bitbar line inverter). The SNM curve is shown in Fig. 6. Table 3 shows the comparison of write static noise margin and read static noise margin of the proposed 12T SRAM cell with those of the other existing SRAM cells. The proposed SRAM cell has higher values 421.56 mV for write static noise margin and 436.58 mV for read static noise margin, which shows that the proposed SRAM cell is more stable than the other existing SRAM cells. Please cite this article in press as: Upadhyay P et al. A design of low swing and multi threshold voltage based low power 12T SRAM cell. Comput Electr Eng (2014), http://dx.doi.org/10.1016/j.compeleceng.2014.10.020
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4.3. Access times Read and write access times of SRAM cell are the total times required for completing one cycle of read and write, respectively. The access time depends on the charging and discharging of load capacitance. Table 4 shows the write and read access times of the proposed and the reported SRAM cells. Table 4 shows the write access time is 9.109 ns and the read access time is 12.494 ns for the proposed 12T SRAM cell. Both access times are poorer than those of 6T and 7T SRAM cells. The speed of the proposed SRAM cell is slower because the sleep transistors S1 and S2 increase the charging and discharging times during read/write operation. 4.4. Current leakage When the SRAM cell changes its state from active mode to sleep mode or sleep mode to active mode some current is dissipated in the form of leakage. In the proposed 12T SRAM cell the transmission gate (TG) tries to reduce the mode transition leakage during write operation. Figs. 7 and 8 show the current leakage during the transition from active mode to sleep mode and sleep mode to active mode, respectively, during write operation. Current leakages during these above mode transitions for the proposed and existing SRAM cells are depicted in Table 5. Table 5 shows the current leakages of the proposed SRAM cell, which are 1.073 pA and 2.392 pA for active mode to sleep mode transition and sleep mode to active mode transition, respectively; both are lesser than those of other existing SRAM cells. 4.5. Power delay product It is simply the product of total power dissipation and access time of SRAM cell. Table 6 shows comparison of power delay products for the proposed SRAM cell and the other existing SRAM cells during write and read operations. The proposed SRAM cell has power delay products of 0.6371e18 and 0.5721e19 for write and read operations, respectively. The same table
Table 4 Comparison of access time. SRAM cells
Write access time (ns)
Read access time (ns)
Conventional 6T [13] 6T Single ended [14] 7T [15] Sub threshold 7T [16] 8T [17] Vertical stacked 8T [18] 9T [19] 9T in sub threshold region [20] Single ended 9T [21] Fully differential 10T [22] PNP based differential 10T [23] 11T [24]
5.351 6.822 6.323 10.033 11.432 10.663 12.644 14.669 11.421 9.754 12.540 15.861
7.672 9.201 10.451 14.611 15.402 15.011 16.633 17.821 13.442 12.877 15.429 19.392
9.109
12.494
Proposed 12T
Fig. 7. Current leakage curve for active to sleep mode.
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Fig. 8. Current leakage curve for sleep to active mode.
Table 5 Comparison of current leakage. SRAM cells
Current leakage during active to sleep mode (pA)
Current leakage during sleep to active mode (nA)
Conventional 6T [13] 6T Single ended [14] 7T [15] Sub threshold 7T [16] 8T [17] Vertical stacked 8T [18] 9T [19] 9T in sub threshold region [20] Single ended 9T [21] Fully differential 10T [22] PNP based differential 10T [23] 11T [24]
9.725 6.294 7.197 4.913 7.315 5.223 8.371 4.280 5.821 4.852 4.374 3.893
11.359 9.257 10.013 6.790 9.157 7.331 10.226 7.016 7.433 6.291 6.195 5.033
Proposed 12T
1.073
2.392
Table 6 Comparison of power delay product. SRAM cells
Power delay product during write operation
Power delay product during read operation
Conventional 6T [13] 6T Single ended [14] 7T [15] Sub threshold 7T [16] 8T [17] Vertical stacked 8T [18] 9T [19] 9T in sub threshold region [20] Single ended 9T [21] Fully differential 10T [22] PNP based differential 10T [23] 11T [24]
1.814e18 1.492e18 1.386e18 1.225e18 1.410e18 1.036e18 1.628e18 1.157e18 0.972e18 1.173e18 0.956e18 0.829e18
1.331e19 1.034e19 1.267e19 1.541e19 0.651e19 0.851e19 1.944e19 1.737e19 0.971e19 1.076e19 1.241e19 0.738e19
Proposed 12T
0.6371e18
0.5721e19
shows that even the access time of the proposed SRAM cell is high but the power delay product is lesser because of more reduction in total power dissipation as compared with the other existing SRAM cells. So from the above results it is evident that the 12T proposed SRAM cell can provide better power solution than the other existing SRAM cells for portable devices if area of the device is not of prime concern.
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5. Conclusions Stability and power dissipation are the major issues in high speed SRAM cells. In this paper, a novel low power 12T MTCMOS based SRAM has been proposed, which dissipates less dynamic power during write/read operation due to less swing voltages which are provided by the voltage sources V1 and V2. The proposed SRAM cell also dissipates less static power during mode transitions due to charge recycling. Low leakage currents and the voltage sources provide better stability. Simulation has been done for power dissipations, static noise margin, access time, leakage current and power delay product for the proposed 12T SRAM cell and the results of the proposed SRAM cell are compared with those of other reported existing cells. The simulation shows that the proposed SRAM cell dissipates lesser dynamic power; has better stability; dissipates lesser current leakage during the mode transitions than the other existing SRAM cells. Although the speed decreases and the area increases in comparison with those of other SRAM cells but total low power dissipation and better stability can dominate over the drawbacks. This proposed 12T SRAM cell can be used to provide low power solution in high speed devices like laptops, mobile phones, programmable logic devices, etc. References [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27]
Borkar S. Design challenges of technology scaling. IEEE Micro 1999;19(4):23. Brews J. High speed semiconductor devices. New York: Wiley; 1990. pp. 139–210. Roy K, Prasad SC. Low power CMOS VLSI circuit design. New York: Wiley Interscience Publications; 2000. p. 27–29. Taur Y, Ning TH. Fundamentals of modern VLSI devices. New York: Cambridge University Press; 1998. pp. 285–286. Mostafa H, Anis M, Elmasry M. Adaptive body bias for reducing the impacts of NBTI and process variations on 6T SRAM cells. IEEE Trans Circ Syst – I 2011;58(12):2859–71. Kao J, Chandrakasan A, Antoniadis D. Transistor sizing issues and tool for multi threshold cmos technology. In: IEEE 34th design automation conference (DAC); 1997. p. 409–14. Kao J, Narenda S, Chandrakasan A. MTCMOS hierarchical sizing based on mutual exclusive discharge patterns. In: IEEE 35th design automation conference (DAC); 1998. p. 495–500. Tachibana F, Hirabayashi O, Takeyama Y, Shizuno M, Kawasumi A, Kushida K, et al. A 27% active and 85% standby power reduction in dual-powersupply SRAM using BL power calculator and digitally controllable retention circuit. IEEE J Solid-State Circ 2014;49(1). Gupta R, Gill SS. A novel low leakage and high density 5T CMOS SRAM cell in 45 nm technology. In: Conference on recent advances in engineering and computational sciences; 2014. p. 1–6. Saeidi R, Sharifkhani M, Hajsadeghi K. A subthreshold symmetric SRAM cell with high read stability. IEEE Trans Circ Syst – II 2014;61(1):26–30. Wang DP, Lin HJ, Chuang CT, Hwang W. Low-power multiport SRAM with cross-point write word-lines, shared write bit-lines, and shared write rowaccess transistors. IEEE Trans Circ Syst – II 2014;61(3):188–92. Islam A, Hasan Mohd. Variability aware low leakage reliable SRAM cell design technique. J Microelectr Reliab 2012;52:1247–52 [No. 6]. Kim TH, Liu J, Keane J, Kim CH. Circuit techniques for ultra-low power subthreshold SRAMs. In: IEEE international symposium on circuits and systems (ISCAS); 2008. p. 2574–77. Singh J, Pradhan DK, Hollis S, Mohanty SP, Mathew J. Single ended 6T SRAM with isolated readport for low-power embedded systems. In: Design, automation & test in europe conference & exhibition; 2009. p. 917–22. Azam T, Cheng B, Cumming DRS. Variability resilient low power 7T-SRAM design for nano scaled technologies. In: 11th international symposium on quality electronic design (ISQED); 2010. p. 9–14. Sil A, Bakkamanthala S, Karlapudi S, Bayoumi M. Highly stable, dual-port, subthreshold 7T SRAM cell for ultra-low power application. In: IEEE 10th international conference on new circuits and systems (NEWCAS); 2012. p. 493–7. Chen G, Sylvester D, Blaauw D, Mudge T. Yield-driven near-threshold SRAM design. IEEE Trans Very Large Scale Integr (VLSI) Syst 2010;18:1590–8. No. 11. Chiu P, Chang M, Wu C, Chuang C, Sheu S, Chen Y, et al. Low store energy, low VDDmin, 8T2R nonvolatile latch and SRAM with vertical stacked resistive memory (memristor) devices for low power mobile applications. IEEE J Solid-State Circ 2012;47(6):1483–96. Liu Z, Kursun V. Characterization of a novel nine-transistor SRAM cell. IEEE Trans Very Large Scale Integr (VLSI) Syst 2008;16:488–92. No. 4. Ramani AR, Choi K. A novel 9T SRAM design in subthreshold region. In: IEEE international conference on electro/information technology (EIT); 2011. p. 1–6. Tu M, Lin J, Tsai M, Lu C, Lin Y, Wang M, et al. A single ended disturb-free 9T subthreshold SRAM with cross-point data-aware write word-line structure, negative bit-line, and adaptive read operation timing tracing. IEEE J Solid-State Circ 2012;47(6):1469–82. Singh S, Arora N, Gupta N, Suthar M. Leakage reduction in differential l0T SRAM cell using gated VDD control technique. In: International conference on computing, electronics and electrical technologies; 2012. p. 610–4. Lo CH, Huang SY. P–P–N based 10T SRAM cell for low-leakage and resilient subthreshold operation. IEEE J Solid-State Circ 2011;46(3):695–704. Singh AK, Prabhu CMR, Soo WP, Hou TC. A proposed symmetric and balanced 11-T SRAM cell for lower power consumption. In: IEEE TENCON region 10 conference; 2009. p. 1–4 [23–26]. Upadhyay P, Ghosh S, Kar R, Mandal D, Ghoshal SP. Low static and dynamic power MTCMOS based 12T SRAM cell for high speed memory systems. In: 11th IEEE international joint conference on computer science and software engineering (JCSSE-14); 2014. p. 212–7. Upadhyay P, Agarwal N, Kar R, Mandal D, Ghoshal SP. Power and stability analysis of a proposed 12T MTCMOS SRAM cell for low power devices. In: IEEE 4th international conference on advanced computing & communication technologies, (ACCT-14); 2014. p. 112–7. Weste NHE, Harris D, Banerjee A. CMOS VLSI Design, Pearson Education, 3rd ed.; 2005. p. 55–7.
Prashant Upadhyay passed B.E. degree in Electronics and Instrumentation Engineering, from University Institute of Engineering and Technology, Dr. B.R. Ambedkar University, Agra, Uttar Pradesh, India in the year 2006. He received the M.Tech degree in Electronics and Communication from National Institute of Technical Teachers Training and Research, Chandigarh, India in 2010. Presently, he is working towards the Ph.D. in the Department of Electronics and Communication Engg., NIT Durgapur. His research interest includes Low power VLSI design. He has published more than 25 research papers in International Journals and Conferences. Rajib Kar passed B.E. degree in Electronics and Communication Engineering, from Regional Engineering College, Durgapur, West Bengal, India in the year 2001. He received the M.Tech and Ph.D. degrees from National Institute of Technology, Durgapur, West Bengal, India in the year 2008 and 2011 respectively. Presently, he is attached with National Institute of Technology, Durgapur, West Bengal, India, as Assistant Professor in the Department of Electronics and Communication Engineering. His research interest includes VLSI signal Processing, Filter optimization via Evolutionary Computing Techniques. He has published more than 250 research papers in International Journals and Conferences.
Please cite this article in press as: Upadhyay P et al. A design of low swing and multi threshold voltage based low power 12T SRAM cell. Comput Electr Eng (2014), http://dx.doi.org/10.1016/j.compeleceng.2014.10.020
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Durbadal Mandal passed B.E. degree in Electronics and Communication Engineering, from Regional Engineering College, Durgapur, West Bengal, India in the year 1996. He received the M.Tech and Ph.D. degrees from National Institute of Technology, Durgapur, West Bengal, India in the year 2008 and 2011 respectively. Presently, he is attached with National Institute of Technology, Durgapur, West Bengal, India, as Assistant Professor in the Department of Electronics and Communication Engineering. His research interest includes Array Antenna design; filter Optimization via Evolutionary Computing Techniques. He has published more than 240 research papers in International Journals and Conferences. Sakti Prasad Ghoshal passed B.Sc and B.Tech, degrees in 1973 and 1977, respectively, from Calcutta University, West Bengal, India. He received M.Tech degree from I.I.T (Kharagpur) in 1979. He received Ph.D. degree from Jadavpur University, Kolkata, West Bengal, India in 1992. Presently he is acting as Professor of Electrical Engineering Department of N.I.T. Durgapur, West Bengal, India. His research interest areas are: Application of Evolutionary Computing Techniques to Electrical Power systems, Digital Signal Processing, Array antenna optimization and VLSI. He has published more than 270 research papers in International Journals and Conferences.
Please cite this article in press as: Upadhyay P et al. A design of low swing and multi threshold voltage based low power 12T SRAM cell. Comput Electr Eng (2014), http://dx.doi.org/10.1016/j.compeleceng.2014.10.020
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A design of low swing and multi threshold voltage based low power 12T SRAM cell q P. Upadhyay a,1, R. Kar a,⇑, D. Mandal a,2, S.P. Ghoshal b,3 a b
Department of Electronics and Communication Engg., National Institute of Technology, Durgapur, West Bengal 713209, India Department of Electrical Engg., National Institute of Technology, Durgapur, West Bengal 713209, India
a r t i c l e
i n f o
Article history: Received 15 June 2014 Received in revised form 25 October 2014 Accepted 27 October 2014 Available online xxxx Keywords: Charge sharing Leakage Low power Static noise margin SRAM Swing voltage
a b s t r a c t This paper focuses on the design of a novel low power twelve transistor static random access memory (12T SRAM) cell. In the proposed structure two voltage sources are used, one connected with the bit line and the other one connected with the bitbar line in order to reduce the swing voltage at the output nodes of the bit and the bitbar lines, respectively. Reduction in swing voltage reduces the dynamic power dissipation when the SRAM cell is in working mode. Low threshold voltage (LVT) transmission gate (TG) and two high threshold voltage (HVT) sleep transistors are used for applying the charge recycling technique. The charge recycling technique reduces leakage current when the transistors change its state from sleep to active (OFF to ON condition) and active to sleep (ON to OFF condition) modes. Reduction in leakage current causes the reduction in static power dissipation. Stability of the proposed SRAM has also improved due to the reduction in swing voltage. Simulation results of power dissipation, access time, current leakage, stability and power delay product of the proposed SRAM cell have been determined and compared with those of some other existing models of SRAM cell. Simulation has been done in 45 nm CMOS environment. Microwind 3.1 is used for schematic design and layout design purpose. Ó 2014 Elsevier Ltd. All rights reserved.
1. Introduction The demand of battery operated high speed portable devices like notebook, laptop computers, personal digital assistants, cellular phones, etc. increase day by day. High speed portable devices require primary memory that responds faster. For that purpose, static random access memory (SRAM) is used, which is faster and refreshing is not needed again and again. Dynamic power dissipation and leakage current are the main issues of high speed SRAM cells because this unwanted power dissipation reduces the battery backup life of portable devices. So it is required to have a SRAM cell design, having both low static and dynamic power dissipations.
q
Reviews processed and recommended for publication to the Editor-in-Chief by Associate Editor Dr. Srinivasan Rajavelu.
⇑ Corresponding author. Tel.: +91 9434788056.
E-mail addresses: [email protected] (P. Upadhyay), [email protected] (R. Kar), [email protected] (D. Mandal), spghoshalnitdgp@ gmail.com (S.P. Ghoshal). 1 Tel.: +91 9805406546. 2 Tel.: +91 9434788059. 3 Tel.: +91 9434788110. http://dx.doi.org/10.1016/j.compeleceng.2014.10.020 0045-7906/Ó 2014 Elsevier Ltd. All rights reserved.
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Supply voltage is scaled to maintain the power consumption within limit. However, scaling of supply voltage is limited by the high performance requirement. Hence, the scaling of supply voltage only may not be sufficient to maintain the power density within limit, which is required for power sensitive applications. Circuit techniques and system level techniques are also required along with supply voltage scaling to achieve low power designs [1]. Aggressive scaling of the devices not only increases the subthreshold leakage but also has other negative impacts such as increased drain induced barrier lowering (DIBL), threshold voltage (Vth) roll off, reduced on current to off current ratio, and increased source to drain resistance [2]. Vth roll off increases the dependence of Vth on the channel length. A small variation in channel length might result in large threshold voltage variation, which makes device characteristics unpredictable. To avoid these short channel effects, oxide thickness scaling and higher and non uniform doping need to be incorporated [3] as the devices are scaled. The low oxide thickness gives rise to high electric field, resulting in considerable direct tunnelling current [4]. Higher doping results in high electric field across the reverse biased p–n junctions (source-substrate or drainsubstrate) which cause significant band to band tunnelling (BTBT) of electrons from the valence band of the p region to the conduction band of the n region. Peak halo doping (P+) is restricted such that the BTBT component is maintained reasonably small compared to the other leakage components. In another technique [5], a low area overhead adaptive body bias (ABB) circuit is proposed to compensate for aging and process variations to improve the SRAM reliability and yield. The proposed ABB circuit consists of a threshold voltage sensing circuit and an on chip analog controller for power reduction. A multi threshold complementary metal oxide semiconductor (MTCMOS) technology provides low leakage and high performance operation by utilizing high speed, low threshold voltage (LVT) transistors during active mode and low leakage, high threshold voltage (HVT) transistors during sleep mode, which reduces the static power dissipation of the SRAM circuit [6,7]. In [8], a technique to reduce both the active and standby powers, especially at room temperature, has been discussed. A bit line power calculator is used to adaptively set the cell supply voltage in the active mode. A digitally controllable retention circuit regulates in the standby mode with small control power. These circuits are implemented in a dual power supply SRAM in 28 nm CMOS technology. In another approach a 5T SRAM cell is proposed with fast performance, high density and low power consumption [9]. The proposed complementary metal oxide semiconductor (CMOS) SRAM cell consumes less power and has less read and write times. The cell is based on the single ended memory storage principle. This scheme is based on the static power reduction. In [10], a symmetrical topology based SRAM cell has been proposed for higher stability. In that two transistors isolate the cell storage nodes from the read operation path to maintain the data stability of the cell. This topology improves the data stability. A low power multiport SRAM with cross point write word lines shared write bit lines and shared write row access transistors approach has been shown in [11]. The design has one write, one read and two write, two read multi port SRAMs for register file applications in nanoscale CMOS technology. The cell features a cross point write word line structure to mitigate write half select disturb and improves the static noise margin (SNM). The write bit lines (WBLs) and write row access transistors are shared with adjacent bit cells to reduce the cell transistor count and area. The scheme halves the number of WBL, thus reducing WBL leakage and power consumption. In addition, column based virtual ground control is employed for the read stack to reduce the read power consumption. In [12], SRAM cell achieves low power dissipation due to its series connected drivers driven by bit lines and read buffers which offer stack effect. This approach is based on static power dissipation. In this present work a novel low power 12T SRAM cell is proposed. A charge recycling technique is used to minimize the leakage currents and static power dissipation during the mode transitions. Two voltage sources are used at the output nodes to reduce the swing voltages, resulting in reduction of dynamic power dissipation during switching activity. The different performance parameters have been determined for the proposed SRAM cell and compared with those of the other existing SRAM cells. The paper is organized as follows: Section 2 discusses about some existing SRAM cells, Section 3 describes circuit design and working principle of the proposed novel 12T SRAM cell. Section 4 describes the detailed analysis of the characteristics of the proposed cell and comparison with other existing SRAM cells and finally, Section 5 concludes the paper.
2. Existing SRAM cells Fig. 1(a) shows the circuit diagram of a conventional SRAM cell [13]. Before the read operation begins, the bit line (BL) and bitbar line ðBLÞ are precharged to as high as supply voltage Vdd. When the word line (WL) is selected, the access transistors are turned on. This will cause a current to flow from supply voltage (Vdd) through the pull up transistor TP1 of the node storing ‘‘1’’. On the other side, current will flow from the precharged bitbar line to ground, thus discharging bitbar line. Thus, a differential voltage develops between the BL and BL. This small potential difference between the bit lines is sensed and amplified by the sense amplifiers at the data output. The 6T single ended SRAM cell [14] is shown in Fig. 1(b). This cell design uses two assist transistors, one for the memory read access (MRA) purpose and the other for the memory write access (MWA) purpose. During write operation, with the BL precharged to required value, write word line (WWL) is held high and MWA is held OFF so as to weaken the cross coupled inverter and hence, get a successful write. During read, read word line (RWL) is held high and read occurs through M6 and MRA depending upon the value stored at the node QB. Please cite this article in press as: Upadhyay P et al. A design of low swing and multi threshold voltage based low power 12T SRAM cell. Comput Electr Eng (2014), http://dx.doi.org/10.1016/j.compeleceng.2014.10.020
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Fig. 1. Different existing SRAM cells.
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The 7T SRAM [15] is shown in Fig. 1(c). Here this design uses two virtual ground rails. During write operation, the cell is disconnected from the ground rail by turning OFF the MW transistor (connected to virtual ground 1) and hence weakening the feedback in the cell and helps in faster write. During hold mode, MW transistor is held ON so that the strong feedback exists. During read, memory write (MW) and read word line (RWL) are held high; the node Q is read through the memory read (MR) (connected to virtual ground 2) transistor. This uses a separate read bit line to be read and hence has a very good read static noise margin (RSNM). Subthreshold 7T SRAM is shown in Fig. 1(d); it has single sided write operation [16]. The Write Bit line and M5 transistor are used to transfer new data (1 bit) into the cell. Single sided write operation reduces dynamic power consumption while besides that, read path is separated from the storage nodes, which increases the noise margin drastically. Transistors M6, M7 are used for reading the cell data. Standby leakage is minimized by connecting transistor M7 to virtual ground. The 8T SRAM cell [17] is shown in the Fig. 1(e). This cell uses the same 6T SRAM structure for the writing operation. For read operation, it uses separate bit lines, read bit line (RBL) and read word line (RWL) as its control signals. During write operation, the PMOS and NMOS transistors of the inverters can be maintained with minimum widths as the read operation is separated. The RBL is read according to the value stored at the storage nodes when RWL is high. The vertical stacked 8T SRAM cell [18] is shown in Fig. 1(f). In this architecture resistive devices (memristors) are connected directly to SRAM storage nodes (Q and QB), to enable the storage of complementary backup data, while maintaining nonvolatile characteristics. This sharing scheme enables word line transistors RSWL and RSWR, to provide SRAM mode write assist functions beyond its original storage capability. To reduce area overhead, the two memristor devices are vertical stacked above the 8T SRAM cell. The 9T SRAM [19] is shown in Fig. 1(g). Write occurs just as in the 6T SRAM cell. Reading occurs separately through N5, N6 and N7 controlled by the read signal (RD) going high. This design has the problem of the high bit line capacitance with more pass transistors on the bit line. Fig. 1(h) shows the design of 9T SRAM cell in subthreshold region [20]. During write, the bit lines (BL) and bit line bar (BLB) are driven with the data that are needed to be stored in the nodes. The footer M9 transistor is switched OFF during write by making the signal (write/read) WR go low. This weakens the feedback and hence faster writes. During read, WR signal is kept high so that the data at the nodes stay stable. Word line (WL) is kept low and read bit line (RBL) is precharged high. Reading a stored 0 at Q occurs when read word line (RWL) goes high. During the hold mode, WL and RWL are made low with WR made high to maintain the stored data. A single ended 9T SRAM cell [21] is shown in Fig. 1(i). The 9T SRAM cell consists of transistors M1-M4, and a Read/Write port M5-M9. The word line (WL) and virtual ground (VVSS) are row based, and write word line A (WWLA), write word line B (WWLB), and Bit line (BL) are column based. In Hold mode, WL, WWLA, and WWLB are disabled and VVSS is held at supply voltage (Vdd). Data are held by cross coupled inverters, M1–M4, and are decoupled from BL. The fully differential low power 10T SRAM [22] bit cell is shown in Fig. 1(j). The design strategy of cell is the series connection of a tail transistor. The gate electrode of this device is controlled by the output of an XOR gate, inputs of which are tapped from write word line (WWL) and read word line (RWL) control signals coming from the WWL and the RWL drivers. The XOR gate and the tail transistor are shared by all the cells in a row. The tail transistor has to be appropriately up sized for sinking currents from all the cells in the row. Without this read buffer, a cell with such small drivers and series connected tail transistor would exhibit unacceptably low read static noise margin (RSNM), resulting in read instability. A P–P–N based differential 10T SRAM cell [23] is shown in Fig. 1(k). In addition to the standard 6T SRAM cell with VDD, GND, one word line, and one bit line pair, one extra signal called VGND, denoting a virtual ground signal. This VGND signal is connected to GND only during the read operation. Otherwise, it is connected to VDD. This cell is called P–P–N based since each of the cross coupled inverters is composed of three transistors cascaded in a P–P–N sequence from top to bottom. The nodes between the two cascaded PMOS transistors are called pseudo storage nodes (including pQ and pQb in Fig. 1(k)), which are separated from the true storage nodes (named Q and Qb in Fig. 1(k)). In addition to the inverter pair, there is a discharging path on each side of this SRAM cell, each of which is formed by an access transistor plus some pull down transistors that connect a pseudo storage node to the VGND. The left hand side discharging path is formed by PGL (Pass Gate Left) and PDL1 (Pull Down Left 1). The discharging path is used to discharge a precharged high bit line during the read operation. The 11T SRAM [24] is shown in Fig. 1(l). Here the cell disconnects the node to which a logical HIGH is to be written from the ground and hence facilitates the write faster. In case of reading, it uses a separate read bit line and N5, N2, N8 and N9 are ON and hence N9 and N8 give low effective resistance to the read operation and hence faster read.
3. Proposed 12T SRAM cell In order to overcome the problem associated with conventional SRAM cells and other existing SRAM cells, the authors proposes a multi threshold complementary metal oxide semiconductor (MTCMOS) based 12T SRAM architecture to achieve low static and dynamic power dissipations for read and write operations and better stability. In the proposed design two voltage sources V1 and V2 are connected to the outputs of the bit line (BL) and bitbar line ðBLÞ, respectively. Two NMOS transistors VT1 and VT2 are used, one connected with the BL and the other with the BL directly to switch ON and switch OFF the voltage sources during write operations. The voltage sources reduce the swing voltage during write ‘0’ and write ‘1’ operation at higher frequencies. This reduction in swing voltage reduces the dynamic power dissipation. The two high threshold Please cite this article in press as: Upadhyay P et al. A design of low swing and multi threshold voltage based low power 12T SRAM cell. Comput Electr Eng (2014), http://dx.doi.org/10.1016/j.compeleceng.2014.10.020
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voltage (HVT) sleep transistors S1 and S2 are used. NMOS sleep transistor S1 connects node M (also called virtual ground node) to ground whereas the PMOS sleep transistor S2, connects node N (also called the virtual supply node) to Vdd supply. The low threshold voltage (LVT) transmission gate (TG) is connected between the two virtual nodes M and N for providing charge sharing. The proposed design is illustrated in Fig. 2. Sleep transistor control signal (ST) and charge sharing control signal (CS) provide the switching activity control on sleep transistors and transmission gate, respectively. Sleep transistors disconnect logic cells from the supply and/or ground. Charge recycling technique reduces the leakage current while transistors flip its mode from active to sleep and sleep to active. Reduction of leakage current reduces the static power dissipation. 3.1. Operation of sleep transistor Consider the configuration shown in Fig. 2. NMOS sleep transistor S1 connects the virtual ground, i.e., node M in Fig. 2, to the actual ground, whereas the other PMOS sleep transistor S2 connects the virtual supply, i.e., node N in Fig. 2, to the actual Vdd supply. During the active period, both sleep transistors S1 and S2 are in the linear region and the voltage values of the virtual ground node M and virtual supply node N are equal to 0 and Vdd, respectively. 3.1.1. Transition from active mode to sleep mode During the transition from active mode to sleep mode of the sleep transistors S1 and S2, the transistors are turned OFF, and since they are chosen to be high threshold (VT) devices, they allow very little subthreshold leakage currents to flow through them. Thus virtual nodes M and N are floating during the sleep period. Now, if the duration of the sleep period is sufficiently long, virtual ground node (M) will be charged up to some voltage value very close to Vdd (supply voltage) by the very small leakage current flowing through T3 (with T1 is ON). Similarly, if the duration of the sleep period is long enough, virtual supply node (N) will be discharged to some voltage value very close to 0 by the very small leakage current flowing through T4 (with T6 is ON). If we denote the total capacitance in the virtual ground node M and virtual supply node N by CM and CN, respectively, it is observed that during the active to sleep transition, CM is charged up from 0 to very closely Vdd while CN is discharged from Vdd to very closely 0.
Fig. 2. The proposed 12T SRAM cell.
Please cite this article in press as: Upadhyay P et al. A design of low swing and multi threshold voltage based low power 12T SRAM cell. Comput Electr Eng (2014), http://dx.doi.org/10.1016/j.compeleceng.2014.10.020
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3.1.2. Transition from sleep mode to active mode During the transition from sleep mode to active mode of the sleep transistors S1 and S2, the transistors are tuned ON. The voltage of virtual ground node (M) starts to fall toward 0, whereas the voltage of virtual supply node (N) starts to rise toward Vdd. Thus, CM will be discharged from Vdd to 0, while CN will be charged to Vdd from its initial value 0. These charging and discharging events on the virtual ground and virtual supply nodes produce wasteful static power dissipation from the circuit power dissipation point of view, which is equal to (CM V2dd + CN V2dd) for one complete cycle of write ‘‘1’’ and write ‘‘0’’ operations. To overcome this problem charge recycling technique has been introduced. 3.2. Operation of charge recycling technique So, to reduce the static power dissipation during switching between active and sleep modes of the circuit, a charge recycling technique [25,26] is used by employing a transmission gate TG between the virtual ground (M) and virtual supply (N) nodes, as shown in Fig. 2. The charge recycling strategy works as follows for active to sleep and sleep to active mode. 3.2.1. Transition from active mode to sleep mode Before active to sleep transition of the sleep transistors, the TG is turned ON first. Then, the voltage of M node or the capacitance CM will rise from 0 to A Vdd (A < 1), not closely Vdd (which occurs for active to sleep transition of the sleep transistors. Similarly, the voltage of N node or the capacitance CN will fall from Vdd to A Vdd, not closely 0 which occurs for active to sleep transition of the sleep transistors. Then active to sleep transition signal ST is applied to the sleep transistors. Now the voltage of M node or the capacitance CM will raise from A Vdd to closely Vdd and the voltage of N node or the capacitance CN will fall from A Vdd to closely 0, provided necessary sleep period is allowed. The common voltage value of nodes M and N after charge sharing is calculated by equating the total charge in both the capacitances before and right after charge recycling as follows in (1).
C N V dd ¼ ðC M þ C N Þ V write1
ð1Þ
Therefore,
V write1 ¼ C N V dd =ðC M þ C N Þ ¼ A V dd
ð2Þ
where A = CN/(CM + CN); CM = Capacitance at node M; CN = Capacitance at node N; Vdd = power supply voltage. The common voltage value of the virtual ground M node and virtual supply node N at the end of the charge sharing is AVdd. If the energy consumptions in the sleep transistors and TG are neglected, the energy drawn from the supply by charging of capacitance CM = CM Vdd (Vdd A Vdd) = (1 A) CM V2dd. Therefore, total energy dissipation for operation = A CM V2dd. 3.2.2. Sleep to active mode Before sleep to active transition of the sleep transistors, the TG is turned ON first. Then, the voltage of M node or the capacitance CM will fall from closely Vdd to B Vdd (B < 1), not 0 (as it occurs without charge recycling). Similarly, the voltage of N node or the capacitance CN will rise from closely 0 to B Vdd, not Vdd (as it occurs without charge recycling). Then sleep to active transition signal ST is applied to the sleep transistors. Now the voltage of M node or the capacitance CM will fall from B Vdd to 0 and the voltage of N node or the capacitance CN will rise from B Vdd to Vdd. The common voltage value of nodes M and N after charge sharing is calculated by equating the total charge in both the capacitances before and right after charge recycling, which is given in (3).
C M V dd ¼ ðC M þ C N Þ V write0
ð3Þ
Therefore,
V write0 ¼ C M V dd =ðC M þ C N Þ ¼ B V dd
ð4Þ
where B = CM/(CM + CN); CM = Capacitance at node M; CN = Capacitance at node N. The common voltage value of the virtual ground M node and virtual supply node N at the end of the charge sharing is BVdd. If the energy consumptions in the sleep transistors and TG are neglected, the energy drawn from the supply by charging of capacitance CN = CN Vdd.(Vdd B Vdd) = (1 B) CN V2dd. Therefore, the total energy dissipation for operation = B CN V2dd. 3.3. Energy saving ratio and static power dissipation The total energy dissipation during the transitions of active mode to sleep mode and sleep mode to active mode is shown in (5).
Etotal ¼ A C M V 2dd þ B C N V 2dd
ð5Þ
Energy saving ratio (ESR) due to charge recycling is ratio of total energy dissipated with charge recycling technique to the total energy dissipated without charge recycling technique, as shown in (6). Please cite this article in press as: Upadhyay P et al. A design of low swing and multi threshold voltage based low power 12T SRAM cell. Comput Electr Eng (2014), http://dx.doi.org/10.1016/j.compeleceng.2014.10.020
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ESR ¼ ðA C M V 2dd þ B C N V 2dd Þ=ðC M V 2dd þ C N V 2dd Þ
7
ð6Þ
Substituting the values of A and B in (6) and substituting for X = CM/CN, one can get
ESRðXÞ ¼ 2X=ð1 þ XÞ2
ð7Þ
The optimum value for X which maximizes ESR(X) is obtained by equating the derivative of this ratio to zero, which results in X = 1, or CM = CN. In other words, in order to obtain the best energy saving, one needs to have equal capacitances in virtual ground and virtual supply nodes. Then the maximum energy saving can be obtained by putting the value of X = 1 in (7) and one gets energy saving ratio (ESR) = 0.5. This means that a maximum energy saving of 50% can be obtained by using the charge recycling method. However, considering the power needed to turn ON or OFF the TG, the total saving ratio is less than 50%. This energy directly related to the current as shown in (8).
Energy ¼ Voltage Current Time
ð8Þ
So from (8), if the supply voltage and the time are held constant then the current is directly related to energy. So as the current dissipation (leakage or unwanted current) in the SRAM cell is reduced during transition modes (active to sleep and sleep to active), the energy reduces. This reduction in leakage current reduces the static power dissipation of SRAM cell according to [27]is given in (9).
Pstatic ¼ Ileakage :V dd
ð9Þ
So, from (7-9), it is clear that the charge recycling technique reduces the energy dissipation and this reduces the current leakage during transition modes and reduction in leakage current finally causes the reduction of static power dissipation of the proposed SRAM cell. 3.4. Dynamic power dissipation by using voltage sources During the write ‘0’ operation, bit line (BL) is low and bitbar line ðBLÞ goes high. So the transistor VT2 is ON and the transistor VT1 goes to OFF condition. Thus the voltage source V2 forces the voltage swing to decrease at the output of the BL line. Similarly, when the write ‘1’ operation is performed, the transistor VT1 is ON and the transistor VT2 goes to OFF condition, so the voltage source V1 decreases the voltage swing at the output of the bitbar line (BL) line. The analog simulation diagram for write operations is shown in Fig. 3. During switching activity from ‘‘0’’ to ‘‘1’’ or ‘‘1’’ to ‘‘0’’ at bit line (BL) or bitbar line ðBLÞ, swing voltage is required. This extra voltage increases the dynamic power dissipation shown in (10). The dynamic power may be expressed as [27]
Pdynamic ¼ aCV dd V Swing f
ð10Þ
where C = load capacitance; a = activity factor; f = clock frequency; VSwing = voltage swing at the output node; Vdd is the power supply voltage.
Fig. 3. Analog simulation diagram of the proposed 12T SRAM cell.
Please cite this article in press as: Upadhyay P et al. A design of low swing and multi threshold voltage based low power 12T SRAM cell. Comput Electr Eng (2014), http://dx.doi.org/10.1016/j.compeleceng.2014.10.020
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So from (10), as the frequency increases the switching activity also increases and this increases the dynamic power dissipation. But voltage sources V1 and V2 reduce voltage swings simultaneously at the outputs. So as the frequency increases, simultaneously the swing voltage decreases. Due to that, at higher frequency the dynamic power dissipation is found to be almost constant for the proposed SRAM cell. Stability of the proposed SRAM cell also improves because voltage sources provide better switching capability.
3.5. Effect of size of transmission gate Sizing of the transmission gate (TG) is a factor that affects the energy saving ratio (ESR) as well as the wake up time (voltage rise time after sleep) of the circuit. In case of the original 8T configuration with sleep transistors, when there is no charge recycling, the wake up time may be defined as the time between turning ON of the sleep transistors and the voltage of the virtual ground reaching within 10% of its final value. However, in a circuit that uses charge recycling, the wake up time may be defined as the time between when the TG is turned ON to when the virtual ground voltage goes below 10% of its final value. In each active sleep active cycle, the TG is needed to be switched ON twice; once before turning the sleep transistors ON, and once after turning them OFF. Every time TG is turned ON, both the NMOS and PMOS transistors in the TG are actually turned ON, i.e., the capacitance is switched two times more. Clearly, TG is turned OFF after the charge sharing is complete. Therefore, the static power consumption of the TG for one complete active sleep cycle can be calculated. Therefore, to calculate the actual energy saving ratio (ESR), one needs to subtract the correction ratio from the ideal ESR. This correction ratio is proportional to the size of the TG. By increasing the size of the TG, the charge sharing process can be speeded up, and as a result it reduces the wake up time; however, this will also increase the correction ratio hence, decreasing the energy saving ratio of the circuit. Therefore, there is a trade off between the wake up time and energy saving ratio. In Fig. 3, left half of the diagram from time 0 ns to 2.5 ns shows the write ‘‘1’’ operation. Similarly, the next half from time 2.5 ns to 5 ns shows the write ‘‘0’’ operation. Bit line (BL), bit line bar (BBL), word line (WL), charge sharing control (CS) and sleep transistor control (ST) signals show inputs and bit line output (BL_OUT) and bitbar line output (BBL_OUT) signals show outputs during write operation. For write ‘‘1’’ operation, BL = High (1 V), BBL = Low (0 V), ST = Low, WL = High and CS = High (after 1 ns it goes low again) are applied as inputs. After simulation operation the output shows BL_OUT = High and BBL_OUT = Low. Similarly, for write ‘‘0’’ operation, BL = Low, BBL = High (0 V), ST = High, WL = High and CS = high (after 1 ns it goes low again) are applied as inputs. After simulation operation the output shows BL_OUT = Low and BBL_OUT = High. The Layout designs of 8T SRAM cell and the proposed SRAM cell are shown in Figs. 4 and 5, respectively. The layout design is based on the k rules. Here the value of k is equal to half of the length of transistors used in the standard foundry. Because the number of transistors in the proposed SRAM cell is more, the layout area for the proposed SRAM cell is larger than those of other existing SRAM cells but lesser power and better stability in the proposed SRAM can easily dominate over this drawback.
4. Results and discussions In this section power dissipation, static noise margin, access time, current leakage and power delay product are computed for the proposed 12T SRAM cell and the simulation results are compared with those of other existing SRAM cells. Analog and
Fig. 4. Layout diagram of 8T SRAM cell.
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Fig. 5. Layout diagram of the proposed 12T SRAM cell.
Table 1 Parameters used for simulation. Tool for schematic design Tool used for analog simulation CMOS technology Supply voltage Transistors width (W)
Transistors length (L) Threshold voltage for sleep transistors
Microwind 3.1 BSiM4 45 nm 1.0 V T1 and T4 T2 and T5 T3 and T6 VT1 and VT2 Sleep NMOS S1 Sleep PMOS S2 TG NMOS TG PMOS 45 nm for all the transistors 0.614 V
75 nm 115 nm 175 nm 350 nm 350 nm 500 nm 350 nm 500 nm
schematic simulations have been done in 45 nm environment with the help of Microwind 3.1 by using BSimM4 model. Table 1 shows the different parameters used for the simulation purpose. 4.1. Power dissipation The total power dissipation in a SRAM circuit consists of two components, the static power dissipation and dynamic power dissipation. Many SRAM circuit techniques have been proposed to reduce these components. For dynamic power dissipation there are two components. One is the switching power due to charging and discharging of load capacitance. The other is the short circuit power due to the nonzero rise and fall times of input waveforms. The switching power of a single gate is expressed in (9). Static power dissipation is due to current leakage. There are three dominant components of leakage in a MOSFET in the nanometer regime. The first one is subthreshold leakage which is the leakage current from drain to source. The second component is direct tunnelling gate leakage which is due to the tunnelling of electrons (or holes) from the bulk silicon through the gate oxide potential barrier into the gate and the third ones are source/substrate and drain/substrate reverse biased p–n junction leakage currents called reverse saturation currents. Table 2 shows the comparison of static power dissipation and dynamic power dissipation for write and read operations of the proposed 12T SRAM cell with the existing SRAM cells. The proposed SRAM dissipates the least static power and dynamic powers as 2.895 lW and 3.734 lW, respectively, during write operation. Similarly, for read operation the proposed SRAM dissipates 1.893 lW and 2.736 lW, which are the least static power and dynamic power, respectively. Please cite this article in press as: Upadhyay P et al. A design of low swing and multi threshold voltage based low power 12T SRAM cell. Comput Electr Eng (2014), http://dx.doi.org/10.1016/j.compeleceng.2014.10.020
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Table 2 Comparison power dissipation. SRAM cells
Static power dissipation for write operation (lW)
Dynamic power dissipation for write operation (lW)
Static power dissipation for read operation (lW)
Dynamic power dissipation for read operation (lW)
Conventional 6T [13] 6T single ended [14] 7T [15] Sub threshold 7T [16] 8T [17] Vertical stacked 8T [18] 9T [19] 9T in sub threshold region [20] Single ended 9T [21] Fully differential 10T [22] PNP based differential 10T [23] 11T [24]
6.263 4.478 3.362 3.119 5.945 3.038 6.117 5.265 4.158 4.021 4.190 3.867
9.234 7.178 6.924 6.374 8.478 6.158 7.901 6.156 5.789 5.923 5.895 4.957
7.731 4.399 4.472 3.293 5.126 3.283 5.992 3.034 3.731 2.836 2.246 2.038
6.967 4.571 5.345 5.171 6.179 4.321 7.901 5.150 4.978 4.149 3.957 3.598
Proposed 12T
2.895
3.734
1.893
2.736
Fig. 6. Butterfly curve for calculation of SNM.
Table 3 Comparison of static noise margin. SRAM cells
Write static noise margin (mV)
Read static noise margin (mV)
Conventional 6T [13] 6T Single ended [14] 7T [15] Sub threshold 7T [16] 8T [17] Vertical stacked 8T [18] 9T [19] 9T in Sub threshold Region [20] Single ended 9T [21] Fully differential 10T [22] PNP based differential 10T [23] 11T [24]
196.31 201.45 267.54 246.87 257.83 279.03 256.10 239.57 249.50 289.33 293.49 314.29
206.27 221.67 288.62 269.30 281.29 293.51 278.90 250.16 268.57 290.23 311.10 334.56
Proposed 12T
421.56
436.58
4.2. Static noise margin SNM is the noise stability measure of the SRAM cell and is defined as the minimum dc noise voltage necessary to change the state of the SRAM cell. SNM is computed as the side length of a maximum square nested between the two voltage transfer characteristic (VTC) curves of the SRAM cell (i.e., one VTC for the bit line inverter and the other VTC for the bitbar line inverter). The SNM curve is shown in Fig. 6. Table 3 shows the comparison of write static noise margin and read static noise margin of the proposed 12T SRAM cell with those of the other existing SRAM cells. The proposed SRAM cell has higher values 421.56 mV for write static noise margin and 436.58 mV for read static noise margin, which shows that the proposed SRAM cell is more stable than the other existing SRAM cells. Please cite this article in press as: Upadhyay P et al. A design of low swing and multi threshold voltage based low power 12T SRAM cell. Comput Electr Eng (2014), http://dx.doi.org/10.1016/j.compeleceng.2014.10.020
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4.3. Access times Read and write access times of SRAM cell are the total times required for completing one cycle of read and write, respectively. The access time depends on the charging and discharging of load capacitance. Table 4 shows the write and read access times of the proposed and the reported SRAM cells. Table 4 shows the write access time is 9.109 ns and the read access time is 12.494 ns for the proposed 12T SRAM cell. Both access times are poorer than those of 6T and 7T SRAM cells. The speed of the proposed SRAM cell is slower because the sleep transistors S1 and S2 increase the charging and discharging times during read/write operation. 4.4. Current leakage When the SRAM cell changes its state from active mode to sleep mode or sleep mode to active mode some current is dissipated in the form of leakage. In the proposed 12T SRAM cell the transmission gate (TG) tries to reduce the mode transition leakage during write operation. Figs. 7 and 8 show the current leakage during the transition from active mode to sleep mode and sleep mode to active mode, respectively, during write operation. Current leakages during these above mode transitions for the proposed and existing SRAM cells are depicted in Table 5. Table 5 shows the current leakages of the proposed SRAM cell, which are 1.073 pA and 2.392 pA for active mode to sleep mode transition and sleep mode to active mode transition, respectively; both are lesser than those of other existing SRAM cells. 4.5. Power delay product It is simply the product of total power dissipation and access time of SRAM cell. Table 6 shows comparison of power delay products for the proposed SRAM cell and the other existing SRAM cells during write and read operations. The proposed SRAM cell has power delay products of 0.6371e18 and 0.5721e19 for write and read operations, respectively. The same table
Table 4 Comparison of access time. SRAM cells
Write access time (ns)
Read access time (ns)
Conventional 6T [13] 6T Single ended [14] 7T [15] Sub threshold 7T [16] 8T [17] Vertical stacked 8T [18] 9T [19] 9T in sub threshold region [20] Single ended 9T [21] Fully differential 10T [22] PNP based differential 10T [23] 11T [24]
5.351 6.822 6.323 10.033 11.432 10.663 12.644 14.669 11.421 9.754 12.540 15.861
7.672 9.201 10.451 14.611 15.402 15.011 16.633 17.821 13.442 12.877 15.429 19.392
9.109
12.494
Proposed 12T
Fig. 7. Current leakage curve for active to sleep mode.
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Fig. 8. Current leakage curve for sleep to active mode.
Table 5 Comparison of current leakage. SRAM cells
Current leakage during active to sleep mode (pA)
Current leakage during sleep to active mode (nA)
Conventional 6T [13] 6T Single ended [14] 7T [15] Sub threshold 7T [16] 8T [17] Vertical stacked 8T [18] 9T [19] 9T in sub threshold region [20] Single ended 9T [21] Fully differential 10T [22] PNP based differential 10T [23] 11T [24]
9.725 6.294 7.197 4.913 7.315 5.223 8.371 4.280 5.821 4.852 4.374 3.893
11.359 9.257 10.013 6.790 9.157 7.331 10.226 7.016 7.433 6.291 6.195 5.033
Proposed 12T
1.073
2.392
Table 6 Comparison of power delay product. SRAM cells
Power delay product during write operation
Power delay product during read operation
Conventional 6T [13] 6T Single ended [14] 7T [15] Sub threshold 7T [16] 8T [17] Vertical stacked 8T [18] 9T [19] 9T in sub threshold region [20] Single ended 9T [21] Fully differential 10T [22] PNP based differential 10T [23] 11T [24]
1.814e18 1.492e18 1.386e18 1.225e18 1.410e18 1.036e18 1.628e18 1.157e18 0.972e18 1.173e18 0.956e18 0.829e18
1.331e19 1.034e19 1.267e19 1.541e19 0.651e19 0.851e19 1.944e19 1.737e19 0.971e19 1.076e19 1.241e19 0.738e19
Proposed 12T
0.6371e18
0.5721e19
shows that even the access time of the proposed SRAM cell is high but the power delay product is lesser because of more reduction in total power dissipation as compared with the other existing SRAM cells. So from the above results it is evident that the 12T proposed SRAM cell can provide better power solution than the other existing SRAM cells for portable devices if area of the device is not of prime concern.
Please cite this article in press as: Upadhyay P et al. A design of low swing and multi threshold voltage based low power 12T SRAM cell. Comput Electr Eng (2014), http://dx.doi.org/10.1016/j.compeleceng.2014.10.020
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5. Conclusions Stability and power dissipation are the major issues in high speed SRAM cells. In this paper, a novel low power 12T MTCMOS based SRAM has been proposed, which dissipates less dynamic power during write/read operation due to less swing voltages which are provided by the voltage sources V1 and V2. The proposed SRAM cell also dissipates less static power during mode transitions due to charge recycling. Low leakage currents and the voltage sources provide better stability. Simulation has been done for power dissipations, static noise margin, access time, leakage current and power delay product for the proposed 12T SRAM cell and the results of the proposed SRAM cell are compared with those of other reported existing cells. The simulation shows that the proposed SRAM cell dissipates lesser dynamic power; has better stability; dissipates lesser current leakage during the mode transitions than the other existing SRAM cells. Although the speed decreases and the area increases in comparison with those of other SRAM cells but total low power dissipation and better stability can dominate over the drawbacks. This proposed 12T SRAM cell can be used to provide low power solution in high speed devices like laptops, mobile phones, programmable logic devices, etc. References [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27]
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Prashant Upadhyay passed B.E. degree in Electronics and Instrumentation Engineering, from University Institute of Engineering and Technology, Dr. B.R. Ambedkar University, Agra, Uttar Pradesh, India in the year 2006. He received the M.Tech degree in Electronics and Communication from National Institute of Technical Teachers Training and Research, Chandigarh, India in 2010. Presently, he is working towards the Ph.D. in the Department of Electronics and Communication Engg., NIT Durgapur. His research interest includes Low power VLSI design. He has published more than 25 research papers in International Journals and Conferences. Rajib Kar passed B.E. degree in Electronics and Communication Engineering, from Regional Engineering College, Durgapur, West Bengal, India in the year 2001. He received the M.Tech and Ph.D. degrees from National Institute of Technology, Durgapur, West Bengal, India in the year 2008 and 2011 respectively. Presently, he is attached with National Institute of Technology, Durgapur, West Bengal, India, as Assistant Professor in the Department of Electronics and Communication Engineering. His research interest includes VLSI signal Processing, Filter optimization via Evolutionary Computing Techniques. He has published more than 250 research papers in International Journals and Conferences.
Please cite this article in press as: Upadhyay P et al. A design of low swing and multi threshold voltage based low power 12T SRAM cell. Comput Electr Eng (2014), http://dx.doi.org/10.1016/j.compeleceng.2014.10.020
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P. Upadhyay et al. / Computers and Electrical Engineering xxx (2014) xxx–xxx
Durbadal Mandal passed B.E. degree in Electronics and Communication Engineering, from Regional Engineering College, Durgapur, West Bengal, India in the year 1996. He received the M.Tech and Ph.D. degrees from National Institute of Technology, Durgapur, West Bengal, India in the year 2008 and 2011 respectively. Presently, he is attached with National Institute of Technology, Durgapur, West Bengal, India, as Assistant Professor in the Department of Electronics and Communication Engineering. His research interest includes Array Antenna design; filter Optimization via Evolutionary Computing Techniques. He has published more than 240 research papers in International Journals and Conferences. Sakti Prasad Ghoshal passed B.Sc and B.Tech, degrees in 1973 and 1977, respectively, from Calcutta University, West Bengal, India. He received M.Tech degree from I.I.T (Kharagpur) in 1979. He received Ph.D. degree from Jadavpur University, Kolkata, West Bengal, India in 1992. Presently he is acting as Professor of Electrical Engineering Department of N.I.T. Durgapur, West Bengal, India. His research interest areas are: Application of Evolutionary Computing Techniques to Electrical Power systems, Digital Signal Processing, Array antenna optimization and VLSI. He has published more than 270 research papers in International Journals and Conferences.
Please cite this article in press as: Upadhyay P et al. A design of low swing and multi threshold voltage based low power 12T SRAM cell. Comput Electr Eng (2014), http://dx.doi.org/10.1016/j.compeleceng.2014.10.020