low voltage and scaling of MOSFETs

MICROELECTBOI~/C ENGINEEItlHG

ELSEVIER

Microelectronic Engineering 39 (1997) 7-30

Technology towards low power / low voltage and scaling of MOSFETs Hiroshi Iwai and Hisayo Sasaki Momose Toshiba Corporation 1, Komukai Toshiba-cho, Saiwai-ku, Kawasaki, 210, Japan This paper describes about technological aspects of low power / low voltage CMOS LSI for high performance operation related with the scaling of MOSFETs.

1.

INTRODUCTION

I.1 Progress and expectation in siliconLSI Silicon LSIs (Large Scale Integrated circuits) have progressed remarkably in the past 25 years. Integration, expressed as the number of transistors in an LSI chip, has increased by 104 - 10 s times, and the computation capability of an LSI chip, expressed as M I P S (millions of instructions per second) value of a microprocessor chip, has increased by 10 a times. As a result of this progress, LSIs already play a vital role in contemporary society, executing numerous intelligent functions. In the next century, the continuous progress of LSIs is expected to lead to wide-ranging social and cultural change in the fields of economy, manufacturing, transportation, communication, education, medical treatment, etc. and to enriches the human life. Especially in the future, in societies with aged demographic profiles and insufficient working population, functions of LSIs capable of substituting for humans in the execution of intelligent work with low cost will be essential for the realization of a desirable quality of life for all in equality•

1.2 Demands for lower power consumption Figure 1 (a) shows the trend in the operating speed of high-end microprocessors [1]. The operating frequency has made a tremendous progress and recently, very high clock frequency of more than 200 MHz has been realized. However, at the same time, power consumption has continued to increase and is 0167-9317/97/517.00 © Elsevier Science B.V. All rights reserved. PII: S0167-9317(97)00165-2

now close to the limit of the conventional air cooling, which is currently assumed to be around 25 W/chip, as shown in Fig. l(b) [1].

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(b) Power consumption Fig. 1 Trends in high-end microprocessors

8

H. Iwai, H.S. Momose/Microelectronic Engineering 39 (1997) 7-30

This is one of the most serious barriers to the increased speed and higher integration of LSIs. J: OD 3::

1 "~" f C V 2

Low V

mm

I (/)

p=

HIgh'end

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Merit:

Decrease In power

Oemerlt:

nl~c~l:Tubl~drsehold r

i

i,

0

"J

Small

( ' "~ Power Consumption

Large

Fig.2 Power and speed relation for different applications Another type of the requirement is low power operation of mobile equipments with battery power supply [2, 3]. In this case, small power consumption is the most desirable for the long lifetime of battery operation rather than the suppression of the heat generation. Thus, two types of the demands for low power consumption of LSIs exist as shown in Fig.2. 1.3 Low power/low voltage concept and scaling methods Basically, lowering the supply voltage is the most effective way to reduce power consumption, because power falls in proportion to the square of the supply voltage as shown in Fig.3. In fact, the supply voltage of microprocessors has already begun to fall: from 5 V to 3.3 and 2.5 V over the several years. Drain current of MOSFETs decreases significantly with the supply voltage reduction. This is good for low power consumption, but reduced drain current usually very much degrades the high speed operation of LSIs. An. other problem is the subthreshold leakage current of MOSFETs designed for low-voltage

Small

[ ~ " Subthreshold

Leakage [ , f

cheracterlsHca

4" Va 0V Fig.3 Low voltage method for low power: Merit and Demerit operation. The threshold voltage of MOSFETs should be also reduced with lowering the supply voltage. Because, subthreshold slope does not improve very much when reducing the supply voltage, the off-leakage current -- the leakage current at Vg = 0 V -becomes large when the threshold voltage is low, as shown in Fig. 3. On the system and circuits side, various new techniques have been proposed [2-10] along with conventional steady efforts in order to improve these problems under low voltage. On the technology side, however, steady approach -- such as effort to increase the drain current under low voltage, and effort to reduce the capacitances of MOSFET and interconnects -- can be basically taken because of the physical constrains of MOSFET design. MOSFET design for every new generation has been accomplished basically on the scaling method proposed by R. Dennard et al. [11], in which downsizing, supply voltage reduction, and performance improvement take

H. Iwai, H.S. Momose/Microelectronic Engineering 39 (1997) 7-30

place with close relation. In the originally proposed scaling method, the power consumption of an LSI chip remains constant for all generations as explained in next session. However, due to several reasons, the actual scaling violated the ideal scaling, which leads to significant increase of the power consumption. Considering the above, it is can be said that power consumption of MOSFETs have been determined by the scaling methods and that low power/low voltage technology is a part of the scaling method. In other words, choice of the scaling method in consideration of the trade-off in various conditions due to the application requirements, becomes important for the low power consumption of LSIs under low supply voltage. The low power methodology or the choice of the scaling method should be different depending on the applications, such as high speed devices and mobile devices. 1.4 Scope of this paper This paper focused on the low power/low voltage technology for high speed devices rather than mobile devices. Technologies for low power MOSFET operation is described with scaling methods. Prior to the explanation of low power/low voltage technologies, scaling methods themselves are explained in detail. Choice of low power/low voltage technologies for mobile telecommunication depends on the system architecture and it is difficult to describe in general. But, some recent results of low power/low voltage technology of mobile telecommunication devices are introduced and low power/low voltage approach is briefly described. 2. SCALING METHOD 2.1 Downsizing of MOSFET for high integration and high speed operation The tremendous progress of LSIs has been driven by the downsizing of their components such as MOSFET. Because downsizing of

9

MOSFETs decreases the switching time of the transistors, it is not only important for high integration but also for high speed operation of LSIs. In the context of downsizing MOSFET dimensions, downsizing of the gate length is most important, because the gate length determines the performance of a MOSFET. MOSFET gate length, which was 10 - 8 I~m in lk bit DRAM products introduced 25 years ago, is 0.35 I~m in current 64 Mbit DRAM products and 0.25 ~ in 256 Mbit DRAM to be mass-produced in a few years. As regards microprocessors, operating frequency, which was of less than 1 MHz 25 years ago, has been increased to more than 200 MHz by using recent high speed 0.25 l~m logic device technologies. In the research at single-transistor level, MOSFETs with deep-sub-0.1 l~m gate length have already been reported [12]. How far can gate length reduction of MOSFETs go? To predict the future of silicon LSIs, it is necessary to answer the question. 2.2 Two requirements when downsizing of MOSFETs; suppression of "off' leakage and reduction of "on" resistance Long-Channel "OFF"

Suppression of leakage current

*ON" Reduction

Short-Channel

Gate length Gate

,' =ource

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Space Charge Region

Leakage Current

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of "ON"

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resistance

ChannelR

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Diff.Layer R Comparable

Fig.4 Fundamental requirements for MOSFET downsizing In digital circuit applications a MOSFET functions as a switch. Thus, complete cutoff of leakage current in the "off' state, and low

H. Iwai, H.S. Momose/Microelectronic Engineering 39 (1997) 7-30

10

resistance or high current drive in the "on" state are the two fundamental requirements as shown in Fig.4. When making the gate length small, even in the "off' state, the space charge region near the drain "that is, the high potential region near the drain" touches the source in a deeper place where the gate bias cannot control the potential, resulting in a leakage electron current from source to drain via the space charge region. This is the well-known "short-channel effect" of MOSFETs. The short-channel effect is often measured as the threshold voltage reduction of MOSFETs when it is not severe. In the "on" state, reduction of the gate length is

desirable because it decreases the channel resistance of MOSFETs. However, when the channel resistance becomes as small as source and drain resistance, further improvement in the drain current or the MOSFET performance cannot be realized without development of a special technique to reduce the source and drain resistance. Thus, elimination of the short-channel effects and realization of concurrent high-drive current of the MOSFETs have always been the two major concerns when reducing the gate length.

2.3 Ideal scaling method: merit for low power consumption

Table I Scaling method Scaling rule (ideal)

Limiting factor Scale

Gate length (Lg)

1/1<

Lithography

6/an

0.1 pm

1/K 1/I<

Uthography [ Defect Direct tunellin~] Sheet resieterce

vadous 100 nm

various 3 nm

0.8 pm

0.04 pm

1/'20

Junction leakage current

1016cm'3

10 le(:m~

100

Transistor level Gate width (Wg) Gate oxide (tox) Junction depth (xj)

1/K

~1972

Substrate

K

Drain voltage (Vd) Drain current (ld)

r Lower limit in Vth 1/1< [Circuit _speed 1/K Circuit speed

Threshold voltage (Vth) Propagation delay time (tpd)

1/1< 1/1<

Impurnty conc. (Nsub)

Off leakage

Gate length (Lg) Gate width (Wg)

~ 1992

5V 1.5 V 3 rnA @W= 60 pm 0.5 mA@W= 1 pm .... L~O pNL~rp) .L-_ .-~q_.p.A//Jq)). 0.8V 0.4V 4 ns 15 ps 6./4~ . . . . . various various 100 nm

Ratio 1/60 1/60 1/30

1/3 116 1/2 1/270

0.4/Jrn various various 9 nm

1115 1115 1/225 1/11

3.3 V

1/1.5

Gate oxide (tox)

1/1< Lithography 1/K2 Lithography 1/K Defect

Supply voltage (V)

1/1(

Gate...capacitance((?,~/tox)

1/1(

1/20

Gate charge (Qg - Cg. V)

1/1<2

1/30

Propagation delay time (tlxl) (-Qg/ld) Clock fraquency/~)-1/tpd)

1/K

Number of Tr (n)

K2

Chip size (Sc - n. Sg)

I

Power (P) (- 1/2.I.n.C.V 2 )

1

Gate area (Sg)

LSI level

Change in 20 years (examples)

Parameter

K

[ ~;)lrWuei~~

Vth

5V

4 ns

80 ps

1/50

2 MHz

200 MHz

100

6K

3M

500

Yield

0.2=2

3c,~-

15

Heat generation

200 mW

10 W

50

r Power consumption "Circuit s.peed r Power consumption

-, t Chip_size

H. IwaL H.S. Momose / Microelectronic Engineering 39 (1997) 7-30

To avoid the short-channel effects and, thus, to secure good switching characteristics of MOSFETs, the scaling method was proposed by Dennard et al. [11], where the parameters of MOSFETs are shrunk or increased by the same factor K as shown in Table I, resulting in the reduction of the space charge region by the same factor K and suppression of the short-channel effects. In the scaling method, drain current, Id (= W/L x V2/t~), is reduced to 1/K. Even the drain current reduced to l/K, the propagation delay time of the circuit reduces to l/K, because the gate charge reduces to 1]K2. Thus, scaling is profitable for high speed operation of LSI circuit. If we can keep the increase of the number of transistor at K 2, the power consumption of the LSI -- which is calculated by 1/2fnCV2 as shown in Table I -- stays constant and does not increase with the scaling. Thus, in the ideal scaling, power increase will not occur. 2.4 Actual scaling and increase of power I

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Year Fig. 5 Trends of actual scaling So far, great success has been achieved with the scaling method in miniaturizing

l1

MOSFETs down to gate-length range of 0.1 pro. However, the actual scaling of the parameters has been a little different from that originally proposed, as also shown in Table I and Fig.5. The major difference is the supply voltage reduction. The supply voltage was not reduced in the early phase of LSI generations in order to keep a compatibility with the supply voltage of the conventional system and also in order to obtain higher operation speed under higher electric field. The supply voltage started to reduce from 0.5 ~m generation because the electric field across the gate oxide would have exceeded 4 MV/cm which is regarded as the maximum limitation in terms of TDDB (Time Dependent Break Down). However, now, it is not easy to reduce the supply voltage because of difficulties in reducing the threshold voltage of the MOSFETs. Too small a threshold voltage leads to significantly large subthreshold leakage current even at the gate voltage of 0 V. If it had been necessary to reduce the supply voltage to 0.08V (=5V/60) and the threshold voltage to 0.0013V (=0.8V/60) for the 0.1 ~tm MOSFETs, the scaling method would have been broken up. The higher voltage than expected from the original scaling is one of the reasons for the increase of the power. Because the supply voltage scaling has not proceeded aggressively, decrease in the drain current was not significant, as shown in Fig.2. Increase of the number of transistors in a chip more than the factor K 2, is another reason for the power increase. In fact, the transistor size reduces by factor 0.7 and the transistor area reduces by factor 0.5 (=0.7 x 0.7), for every generation, and, thus the number of the transistor is expected to increase by factor 2. In reality, however, the increase cannot wait the downsizing and actual increase is done by factor 4. The insufficient area for this is covered by increasing the chip area by factor 1.5 and also by introducing new technologies such as multi-layers interconnects. With these modifications of the scaling

12

H. Iwai, H.S. Momose / Microelectronic Engineering 39 (1997) 7-30

method, many new techniques listed in Table 2 have been introduced and developed. For example, the deep-channel-doping technique was used to solve the leakage current problem under higher supply voltage and silicide technique solved the resistance increase in the shallow source and drain diffusion layer in a small-geometry MOSFETs. Table 2

Doping

Technologies which extended the scaling limits 3D: LDD DeepIon Imp. 1970s Rapid thermal anneal Early 1990s Control of dust and contamination 1980s

Structure process

Thin gate oxide

Salicide Late 1980$ Multi-level interconnects 1980s LOCOS late 1960s Trench Eady 1990s

Wiring resistance Isolation

2.3 Difficulty of scaling below 0.1 p~a due to certain limitation in parameters So far, many research organizations have successfully fabricated 0.1 ~tm gate length MOSFETs. But looking at the parameters of the MOSFETs, it is known that certain parameters already reached the limit and that further scaling is not possible. For example, the gate oxide cannot be made less than 3 nm thick because of leakage currents caused by tunneling in common sense, and substrate impurity concentration cannot be raised more than 101S/cm3 because of tunneling leakage current across the highly-doped pn junctions of source/drain and s u b s t r a t e . . In fact, the trend of the gate-length reduction beyond 0.1 lpm

"~m

pan in the early 90's lost momentum as shown in Fig.6. This is sometimes called the 0.1 ~tm wall. 3. MOSFET DOWNSIZING BELOW 0.1 lxM 3.1

Lg tox Xj Na

40 nm gate length n-MOSFET 0.1 pm Scaling 40 nm MOSFE1 ~ MOSFET 0.1 pm X 2/5 40 nm 3 nm X 1 3 nm 40 nm X 1/4 10 nm 101ecm"3 X l 101%vri 3

Vd 1.5V

Xl

Lg 40 nm --~ i As

II

] - ~ ' ~

// Leff23nm

1.5V

Xj 10nm

ps6.2K~

Fig.7 Structure of 40 nm gate-length nMOSFET In order to realize deep-sub-0.1 ~m MOSFETs, further modification of scaling method is required because some of the parameters have already reached their scaling limitation in the 0.1 I~m generation. By device simulation, we have found that deep-sub-0.1 pm MOSFETs operate well if we adopt a new scaling scheme where only the junction depth is scaled drastically down to 10 nm [13, 14] as shown in Fig.7. In the following, experimental results respecting a 40 nm gate-length MOSFET fabricated by this scaling scheme are explained. To realize such ultra-smallgeometry MOSFETs, two techniques were developed. One is a resist thinning technique [15]. The resist pattern for the gate polysflicon electrode was made using an excimer laser stepper, and it was successfully 22

•t 10 E o. 21 ,_ 10

SIMS Profile

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0

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Fig.8 Impurity profiles: Solid phase diffusion and ion implantation

H. Iwai, H.S. Momose/Microelectronic Engineering 39 (1997) 7-30 8.0 7.0 6.0

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1111 O.Ol

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o.1 Lg (/am)

(c) Id- Lg Fig.9 Electrical characteristics of 40 nm

gate-length n-MOSFET

13

thinned to a width of 40 nm by 02 plasma ashing. The other is a solid-phase diffusion technique [16] to realize 10 nm source and drain junctions, as shown in Fig.8. Achieving 10 nm highly-doped diffused layers using conventional ion-implantation techniques was difficult, because of the deeply implanted ions through channels in the silicon crystal and damage-enhanced diffusion during subsequent annealing. However, such layers can be successfully fabricated by solid-phase diffusion from the PSG gate sidewall. Good transistor operation of these 40 nm gate.length n-MOSFETs at room temperature was confirmed, as shown in Fig. 9(a) and short-channel effects were almost completely suppressed due to the ultra-shallow junction. It was shown that hot carrier generation of the ultra-small gate-length MOSFET falls significantly with the reduction of drain voltage as shown in Fig. 9(b) and there is no problem of the hot carrier reliability. However, since the resistance of the ultra-shallow source and drain layers remains relatively high compared with that of the ultra-shortchaniiel region, and also as a result of velocity saturation, the drain current per unit gate width was only 30% greater than in 0.1 gm MOSFETs, as shown in Fig. 9(c), although the figure of 30 % itself might be a good improvement when considering the technological difficulties. Please note that in this figure, gate width and drain voltage are not reduced with gate length reduction, This is different from the previous cases used for the explanation of scaling. Thus, drain current should be increase basically in inverse proportion to the gate length. 3.2 Drain current improvement by use of 1.5 nm direct tunneling gate oxide In order to improve the performance of ultra-small gate-length MOSFETs, several methods have been studied. One is to increase a number of carriers by reducing the gate oxide thickness beyond the direct tunneling leakage limit, 3 nm. A uniform 1.5

14

H. Iwai, H.S. Momose/Microelectronic Engineering 39 (1997) 7-30

n m gate oxide was grown by rapid thermal oxidation (RTO) at 800°C for 10 seconds [17]. Contrary to the general opinion that tunneling leakage gate current would have an adverse effect on M O S F E T characteristics in a device fabricated with such a gate oxide, ul. tra-small gate lengths M O S F E T s show normal transistor operations, since the gate leakage with gate length reduction, as shown in Fig. 10. With such an ultra-thin gate oxide a record high drain current of more than 1 mA/~tm and transconductance of more than 1,000 m S / m m were achieved with a supply of 1.5 V. The extremely high drain current observed in this M O S F E T even with a supply voltage of 0.5 V makes it a very attractive possibility for low-power high-speed operation of LSIs.

0.0~

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2.0

0.0:

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~" 1.5

~.0.01 -

/~/'/

spacer

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1.0

Vd (V) (a) Lg = 10 ttm

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(RTA:1000°C,10Nc.) (a) Structure

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3.3 Drain current improvement by use of Silicided Silicon Sidewall Source Drain (S4D) structure In order to reduce the source and drain resistances significantly, Silicided SiliconSidewall Source and Drain (S4D) structure [18] is very effective. With this kind of elevated source and drain structure, the source and drain resistance falls dramatically to less than 100 ~ttm as shown in Fig. 11.

-2.0

(b) S/D resistance 1.5

(b) Lg = 0.14 p~n

Fig. 10 Id - Vd characteristics of 1.5 nm gate oxide n-MOSFETs

vgo~

Fig. 11 S4D (Silicided Slilicon-Sidewall Source and Drain) structure 3.4 Drain current improvement by use of intrinsic-doped epitaxicial channel In order to increase the mobility of channel carriers, it is effective to use ultra-thin undoped epitaxially grown silicon layer as the channel as shown in Fig. 12 [19]. Using this structure, mobility, drain current and transconductance increases 20 % compared with those of the conventional structures as shown in the figure.

15

H. Iwai, H.S. Momose/Microelectronic Engineering 39 (1997) 7-30

3.5 Expectation of performance improvement in combination of the above techniques intrinsic epitaxial Si " ~ : ' : ! ...............!!~:~:~:':'~"" Sisub. ~ epitaxialSigrowth

70( _ Vd=I.5V epitaxJal channel

~" 60( " ~

E ~,~.Uxn-MOSFET~K / ~v 50( ~ N : ~ , / 0"epi

Si sub. g=e, source and drain

bulk / ~ n:MOSFET ~ ' ~ . = 300 0.1 0:20.3 ~.40¢>.~.5 Lg(pm)

formation

Fig. 12 Undoped epitaxial channel MOSFETs The above experiments respecting the performance improvement were accomplished independently of each other, but if all the methods are combined for the 40 nm gate length MOSFETs, the performance will be increased at least more than 3 times. These experiments suggests that, in the deep-sub 0.1 I~m regime, good transistor operation with higher performance can be expected than is possible today at 0.1 pan regime. This is good news for the future of silicon MOSFETs.

gate electrode shows a significant resistance increase when the gate length is reduced down to deep sub-micron as shown in Fig. 13. Now, CoSi2 [21] is regarded as the most promising candidates also for the subo0.1 I~m regime. Nitrided-oxide technique [22, 23] will be also very important for suppressing the boron penetration from the p type polysilicon gate electrode for future p-MOS transistors with ultra-thin gate dielectric. Most of the conventional studies for 0.1 and sub-0.1 I~m MOSFETs have focused on the gate related issues including source/drain-extension portions. As a next step, efforts to reduce the total MOSFET area including that of source/drain, contact hole, isolation will become important. 4. POSSIBLE LIMIT OF MOSFET DOWNSIZING AND ITS PERFORMANCE 4.1

Possible limit of MOSFET downsizing

ll~m

OOnm

" Q , 4 0 n m

e-

3.6 Other important techniques for the high performance and integration of sub-0.1 pan MOSFETs 103

:

"NOO"ml

cc~ 10nm

of electron

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lnm

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Wavelengthl'l I

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I Atomic disiance I . . . . .~,. 0.1nm i , J, , i', 1970 1980 1990 2000 2010 2020

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Fig. 14 Extrapolation of gate length trend

Year

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1 10 W (pm) Fig. 13 Sheet resistance of salicided gate electrode

Study of new slilicide materials [20, 21] is also important for 0.1 and sub-0.1 ~tm devices, because conventionally used TiSi2 -polycide

So far, the future of MOSFET downsizing looks promising. However, of course, the downsizing of the MOSFET gate length will not continue forever as shown in Fig. 14. If we assumed that the past trend would continue in the future, the MOSFET gate length would reach the wavelength of an electron in several years and the atomic distance of the silicon crystal in 30 years. It is hard to be. lieve that the gate length of MOSFETs could

16

H. IwaL H.S. Momose/Microelectronic Engineering 39 (1997) 7-30

become less than the atomic distance, assuming that the gate electrode is constructed with at least some kind of atomic structures. Thus, the gate-length reduction will reach a limit sooner or later. What will be the limit in practice? The practical limit will be reached around 25 - 20 nm gate length, when the velocity saturation effect and source/drain resistance increase become dominant. Always the suppression of the short-channel effects is the most difficult part of MOSFET downsizing and thus, the junction depth should be made smaller. In these devices, some kind of elevated source and drain structure, such as S4D will be required to reduce the source and drain resistance. However, thin insulator gate sidewall is necessary to isolate the elevated silicon area from the polysilicon gate electrode. Even though elevated structure, source/drain dopant should diffuse into silicon substrate under the insulator sidewall to reach the edge of the gate electrode. If we assume the minimum thickness of the insulator sidewall is 5 nm, the diffusion depth will be also about 5 nm. By the scaling rule, the minimum gate length for 5 nm source/drain junction becomes around 20 - 25 nm. Also the junction depth of 5 nm is a close value to the channel inversion layer thickness -- 10 - 1 nm depending on the gate bias. If the junction depth becomes close to the inversion layer thickness, the resistance of the diffusion regions will be very high comparable to that of channel region, resulting in the large degradation of the current drive. This will also limit the downsizing of MOSFETs. These are very rough estimation, and practical limit in which performance improvement cannot be obtained might come earlier, and more detailed and accurate analysis using Monte Carlo simulation is looked forward to. According to our preliminary simulation results, a MOSFET with 1.5 nm gate oxide operates at least normally at the gate length of 25 nm at room temperature [13, 14].

4.2 Possible limit of MOSFET performance What will be the limitation of the performance, or operating speed of MOSFETs? Considering an ideal case where capacitance is ignored, the switching time or the transit time of electrons with the saturated velocity in 25 - 20 nm gate length MOSFETs is the order of 0.1 ps. In real circuits, charge and discharge time of the capacitance is dominant and much larger that that of the transit. Note that the minimum propagation delay time (t~) of a CMOS inverter at room temperature is already 11.4 ps/gate [21]. Thus, no improvement of the tpd more than 2 order of magnitude -- or "0.1 ps" -- would not be expected. Furthermore, the unscalable fringing component of the capacitance becomes the dominant element with the downsizing. Assuming that we can obtain several to 10 time improvement in the current drive of the 25 20 nm gate length MOSFETs compared with that of conventional 0.1 ~tm MOSFETs, the limit of the tpd reduction will be an order of ps. 5, LOW VOLTAGE/LOW POWER OPERATION WITH HIGH SPEED USING ULTRA-THIN GATE OXIDE 5.1 Necessity of gate oxide thinning for high performance operation of MOSFETs under low voltage Figures 15(a) shows the relation of the gate length and gate oxide thickness mainly obtained from paper presentations [24]. Except the 1.5 nm case [17, 25] plotted with filled circle, it is clear that the trend of gate oxide thinning has stooped at the gate length of 0.1 ttm at which the gate oxide thickness reached 3 nm. The 3 nm is the directtunneling limit. From this figure also, it can be said that the scaling method changed at the gate length of 0.1 ttm. Figure 15 (b) shows the corresponding relation between gate length and drain current per unit gate width. The supply voltage is different at

H. Iwai, H.S. Momose/Microelectronic Engineering 39 (1997) 7-30 ,

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.

.

• i

0.1

5V

.

.

.

.

.

*,l|

Lg (pro)

. . . .

1

10

(b) Lg vs. Id per unit Wg with Vd as a parameter

2OOO

,

,

,

, , * , , i

,

,

,

° l , , , i

•

•

, , , , , ,

1.5V.

1000

1.5 V e j / 1.0V ',.'

Vdcl-

E 200 100 0.01

......................... 0.1 1 Lg (pm)

10

(c) Lg vs. gm per unit Wg with Vd as a parameter Fig.15 Trends of tox, Id, MOSFETs

and gm for

17

each point and is labeled there. Clearly, there are 3 regions in the gate length. In the range with gate length larger than 0.5 I~m, the dependence of drain current on gate length is large and the slope is steep because drain voltage is constant at 5 V. In the range between 0.5 and 0.1 ~m, the slope become small because the supply voltage reduces with the gate length reduction from the 0.5 Ilm generation. In the sub-0.1 pm region, increase of drain current with reduction of the gate length cannot be seen and the curve is flat even the supply voltage stays constant around at 1.5V. This is because of the higher source-and-drain resistances and velocity saturation. In contrast, 1.5 nm gate oxide point shows significant increase in the drain current. Figure 15 (c) shows the corresponding relation between the gate length and transconductance. Similar relation as the drain current case was observed. These results suggest that gate oxide thickness need to be continuously scaled-down as original scaling suggests, even beyond 3 nm in the sub-0.1 ~m gate length region, in order to obtain the continuous improvement of the performance. 5.2 Case study for low voltage high speed operation of LSI using 1.5 nm gate oxide MOSFETs. For high performance operation, it has been pointed out that gate oxide thinning even beyond the direct-tunneling limit is important [24]. 1.5 nm gate oxide MOSFETs have also high performance under low supply voltage such as 0.5 V [1]. In the following, 1.5 nm gate oxide MOSFETs are taken as an example for the case study of high performance operation of LSI with low power consumption under low supply voltage [1]. Table 3 shows a typical parameters of high-end microprocessors using 0.4 ~m gate length MOSFETs. Now, we consider cases when the 0.4 ~m MOSFETs (Tr.A in Table 4) is replaced by Tr.B or Tr. C described in Table 4. Tr. B is with 0.1 Ilm gate length and 3 nm

18

H. Iwai, H.S. Momose/Microelectronic Engineering 39 (1997) 7-30

As the supply voltage is reduced, the ratio of threshold voltage to the supply voltage is increased so as to suppress the subthreshold leakage current at V~ = 0V, with the sacrifice of current drive.

Table 3 Typical characteristics of today's high-end MPU's SUPPLY VOLTAGE:

3.3 V

CLOCK FREQUENCY: ~ 200 MHz

POWER CONSUMPTION:

~ 10 W

GATE LENGTH:

PTORTAL :

"" 0.4 pm

NUMBER OF TRANSISTORS:

I

I total

"," 3 M

Pc-vc

+

PLs

+

I I I charge and discharge

I leakage

,

I

subthreshold

Table 4 Device parameters of MOSFETs for this case study Tr. A

Tr. B

Tunndblg g m ~ MOS~=To

0.4

0.1

Leff (pro)

~0.26

-0.05

~0.OO

TOX(nm)

9

3

1.5

$4) xJ (nm)

100

40

30

S/D(cm'~)

llrlO

Nsub (cm-1)

2x1017

II

2 f nCV~

direct tunneling

2 n : number of Tr f : clock frequency

c:cap~mce

Tr. C

Tylp4¢II MOSFET Coavmtlond ~ m~mMPUs &lpnt ~

Lg (pm)

1

Pc.m:

PLO

PLS

=

n

I LS Vdd

PLG

:

n

ILG Vdd

I LS

=

n I Vth I ( ) T

I

0.1

: subthreshold

LS leakage current

I ,,~: direct -tunneling

'-1° lukagecurrent

Vth

Ivth

:ld@Vth

s : s.bt~mho~d slope

2x10"

5x10TM

lx1011

lX101"

Table 5 Vth design for each supply voltage Vdd (V)

3.3

2.0

1.5

1.0

0.5

0.4

0.3

Vth (V)

0.S

0.4

0.3

0.2

0.15

0.12

0.1

i

t cat

oc

fMO

=

Q cat

C crlt Vdd

lu

Id

1

lu

t cHt

C c,tV~

t crlt : swltchng time of crltcal path circuit Qcrlt : charge of crltcal path circuit Ccrit : capacitance of cdtcal path circuit

f MO : maximum operation frequency

gate oxide, and Tr. C is 0.1 I~m gate length and 1.5 nm gate oxide. In low-voltage operation, the threshold voltage design of a MOSFET is very important. A low threshold voltage increases the subthreshold leakage current, resulting in an increase in the power consumed by leakage. On the other hand, a high threshold voltage reduces the drain current and degrades the circuit's operating speed. From experience, it is known that a suitable value of threshold voltage is in the range of 1/4- 116 of the supply voltage [26, 27]. In this study the threshold voltages given in Table 5 were adopted for each supply voltage.

Fig. 16 Euations for the power and speed relation of the MPU's The basic equations for calculating the power consumption and clock frequency are written in Fig. 16. The total power consumption of the microprocessor, PTOrAL,is divided into 3 parts, the charge-and-discharge component, Pc.pc, subthreshold leakage component, PLS, and tunneling gate oxide leakage component, Pro. PLG needs to be considered only in the case of direct-tunneling gate oxide MOSFET, Tr.C, case. Figure 17 shows the relation between P~Dc and clock frequency, f. When the supply voltage, VDD. is constant, the operating point of the MPU (microprocessor) in the P-f plane

19

H. Iwai, H.S. Momose/Microelectronic Engineering 39 (1997) 7-30 100

100

¢,h;;,z,,,~,.,./,;,,~/;,/~/,,/.#,~,~%~;¢,~,,,~,....... ~4.~.~,,,;::

10 : Upper//m/t wJlh

Current MPU " " ~ : ' : " "

"

! usual air cooling

~

,,: ~

,,,.

10

1

~

10m

! lm

~

,.,',:Xr.B!

...'..;:.:..

;:

100/J .

,~'~, ~::~,'" .-".'"

!,,~,"

,*

Fig. 17 Relationship between clock and power consumption considering only charge and discharge component , ,,..q

i B|,..I

,,

,,.q

. u|mq

, u m,q

" 0.5 V ~ /

v , 2.0 v

0.4V/6'~

15V

0.3 V 4~ 1.0 V

Gate leakage component ~ 0.5 v PLG j~ 0.4 V

lm

•

C l o c k f r e q u e n c y (Hz)

, ,,,,.q

100m

f m x x i m u m , . ¢~ M I V d d

1 p . , X . . . , . : X . . . . . . . . . . . . . . . . . . . . • ......• ............. 0.1 K 1 K ! 0 K 100K 1 M 10M 100M 1 G 10G

100

component PC-PC

10m

PC*DC= '~fmeedmumCVdd2

,',."

;ov

Ctmrge-dlecharge

Q.

~component ."

10/I r," ,';,',," ,,',,~'

! ln~n !

2.0 V(p 15V

:01

c n , , ~ o - a~.~.a,~., ~1

!: ~," ~.~.,*" ~,.~,~"~'~~~"~-,~,'" ,,,.',,"

i i~ll.q

O

F

"":'"

u illull

"

, ,,," ~,

100m

O

i u|lmq

To~ m 1.5 nm

,4~2q~,; ,;

:

r. :.

! iv,mq

Tr.C

. ,,,-.I..

~--.

100p

100K

''"""

'"'-'"

1M

'""-'

0.3V

'"--,

,,,,,,,.

i 0 M 100M 1G 10G Clock frequency (Hz)

,,--

10~:~

Fig. 19 Relationship between clock and power consumption considering both charge and discharge component and tunneling gate leakage component

Current MP.U "1%-,~=,'~~,~'"

~@ lOOm ,.,

: p - 2 p,~

.,',,':,:,'grJ:~

_.. P,o~' _ . ~ ~ " o ~ v - ...........

: .......

~

, ; ~ :.'~ : : ' : : . . . . . . . . .

0

1m

.

"lOOp 10p

,',.

,,

,"

,IL/~,,.',',::," ,," ,," ,I~F ,';,',," ,," ,'"

.

.

.

.

.

.

.

.

.

"'" "'"

O~.~.e~-~lV "~d/4~"-dl~,~//~' :'~ ". y ' ' " -

.

.

.

~.-ov .

.

.

.

.

.

v.,., = 2.0 v .

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

,,

Subthr.hold leaka~le

component

.. w

~/~,," ,';,',," , " , , " PLS..nWILs'V "~ (ILS.,IO e.t) "+:'" ~'--'~'-" . . . . . . . . . . . . . . . . +. . . . . . 9~;;~.~9" ,**," , ' .

, , " **°

1/~ °,.~,,,'." , 1 , . . . , ,.,.., , , , , . . . , . . . , , , . , . , , , , . . . ,,., 0.1K 1 K 1 0 K 10OK 1 M 10M 100M 1 G 10G

C l o c k f r e q u e n c y (Hz)

Fig. 18 Relationship between clock and power consumption considering both charge and discharge component and subthreshold leakage component moves on the dashed line of P ~
inverse of the charge-and-discharging time of the capacitances of the critical-path circuit of the MPU as expressed by Id/(CcVdd). f~o curve produced by connecting each f~o point for each Vm is drawn with hatched curve for the cases of Tr.A and Tr. B as examples. By improving the performance of transistor from Tr. A to Tr. B, the maximum operating point moves to higher frequency direction. In other words, if the transistor performance is improved, the MPU operates at the same fMo with lower Pc~Dc. Then, power consumption including both Pc.pc and PLS are plotted versus f, as shown in Fig.18. The subthreshold leakage current, ILs, is defined by threshold voltage, Vs. It increases exponentially with reduction in V~ as shown in Fig.16. Thus, Pus in the P-f plane is the horizontal dashed line defined by Vth and further by Vdd corresponding to each Vth in Table 5. When Vddbecomes small, PLS increases because Vth decreases in Table 5.

20

H. Iwai, I-LS. Momose / Microelectronic Engineering 3 9 (1997) 7-30

Now, let us focus on point Y in Fig. 18, where Pts line at Vdd 0.5 V and Pc~c line at Vdd = 0.5 V cross each other. This is the point where Pc.pc and PLs become the same value. Thus the total power PcDc + PLs become the 2 times of each power component, which can be plotted as point Z. By connecting the points corresponding to Z at each Vdd, the minimum power line can be plotted as shown by hatched thick dashed line. Next, Pro, the gate leakage component is considered in Fig.19 for Tr.C case. In this figure, P c . ~ c curve is plotted with filled circles and Pm curve is plotted with filled triangles. Fortunately, the Pm component is about 2 orders of magnitude smaller and can be ignored in this high-end MPU case with up to 3 million MOSFETs which the case studied here. Figure 20 summarizes the relation of PT~ TALand f, obtained by the above calculations. The area above the dashed 2PLs versus f line, and left-side of Pc.pc versus £x~ curve for each Tr. is the operating point for each case. The important portion is the Pc-pc vs. f ~ curves. Table 6 summarizes Vdd, PTOTALand fMO for the points labeled on the curves. It should be noted that improvement of the drain current by using 1.5 nm gate oxide is very effective for reducing the power consumption. For example, in the case of operating point (f) of Tr.C case, the MPU will operates at 2 times higher frequency than today's MPU with power consumption of 1/22, under 0.5 V power supply. In the (g) point case, it operates 1.6 times faster with power consumption of 1/42. Even Tr. B case with 3 nm gate oxide, the MPU operates at the same speed with power consumption of 1/43 at point (d). Thus, it is concluded the improvement of the transistor performance is not only useful for increasing the operating speed, but also very useful for reducing the power consumption by selecting appropriate operating point at low supply voltage.

lOO

,

.......1

. .......1

. ......,

. ..-...1 " . . . . , . . , ,S

~II.** .o *

=

10

"" "

""'~"

......~..~./...:..'%., ,°

. " ," l-o o" *

o°

•0100m

....:",

O.

,0m

,

. ~ #.#."

..

/~se,* • oo"~,~

":? .-," ..

,~.¢,.,,;,....:::.:.,,,

1 m "',':.

100K

...... (':'-"[. . . . . . . . . . . . . . . . . . . . . . . . . . . .

1M

10M 100M 1G Clock frequency (Hz)

10G

Fig. 20 Relationship between clock and power consumption considering all components Table 6

Relationship between clock and power consumption at various operation points in Fig.20 Vdd point i P (a.u.) i f (¢u.) Tr. A 3 . 3 V ( ~ ' ,

,¢

1_.

,'

- ..I -

1

20 v Tr. B

v o.sv® L1143 ,,, 1.o ~.sv(E) :111.2:4.1 f ..... o.svQ : I12~: 2.0 "1"

Tr. C

0.4V

1/42

,

I

1.6

6. OTHER LOW POWER TECHNIQUES In this section, some of other low power techniques are briefly introduced including those of circuit level. 6.1

Low capacitance technique Reducing the capacitance is another important factor of the low power technology regardless of whether supply voltage is high or

21

H. IwaL H.S. Momose/Microelectronic Engineering 39 (1997) 7-30

low. Many kinds of research and development -- such as introduction of low K dielectric materials as an interlayer of metal interconnects, study of SOI devices, optimization of impurity distribution in the silicon substrate -- have been intensively carrier out. In general, low capacitance techniques have been developed for high speed operation of the LSI, but it is also useful for the low power operation. 6.2 Parallel processing under low voltage Degradation of the speed under low supply voltage can be recovered by parallel processing of the circuits. Usually, the decrease of the power by reducing the supply voltage is larger than the increase by adding the parallel circuits. Thus, by adopting the parallel processing, the power can be reduced without harming the speed of the LSI under low supply voltage [2]. 6.3 Multiple Vt technologies Low threshold voltage is desirable for high speed operation, especially under low supply voltage. In order to minimize the subthreshold leakage problem, multiple threshold voltage in a chip can be adopted, in which low threshold voltage is used only for the critical path [28]. Another use of multiple threshold voltage is MT-CMOS (Multiple -Threshold CMOS) [8]. In this technique, high threshold-voltage transistors are used as a switch which cut off the path between the power supply and circuit in the sleep mode. They are also used for latch circuits which store the data in the sleep mode. The high threshold voltage suppress the leakage current. 6.4 Variable Threshold-Voltage (VT) scheme Threshold voltage with process variation can be automatically adjusted to a designed value by adjusting the substrate bias [9, 10], as shown in Fig.21. This is effective when setting the threshold voltage at the minimum allowable value without margin for the

4.3V@standby VBS.n-~ J' SLEEP ¢1) .#

. ~ee S.LEEP

2.0V@active I--'I VOOL" ~ T "-IMPll-- VDOL ~ i~ -0.TV@standby ' '--I_Vm~.p: -0.3V@active t

o. vo, v.

GND " - ~

" ~ ---IMNIr--- GND

OV@a~vo i

i

T

SLEEP -2.0V@standby Fig.21 Variable Threshold (VT) scheme [9,10] process variation. This technique is also useful for suppressing leakage current in a sleep mode by raising the threshold voltage in that mode. 6.5 Dynamic threshold voltage MOSFET (DTMOS) The threshold voltage of a MOSFET can be changed dynamically depending on the gate bias [29]. In this structure the gate polysilicon electrode is tied with the body of SOI MOSFETs, as shown in Figs.22 and 23. When the gate bias is 0V, the threshold volt. age is designed to sufficiently high value to suppress the leakage. When the gate bias become positive, the body is biased positive and threshold voltage becomes lower, which Sour

Drain

,n!l Buried O~
Fig.22 Schematic of DTMOS with body and gate tied [29]

22

H. IwaL H.S. Momose/Microelectronic Engineering 39 (1997) 7-30 12

I

OTMOS . . . . . StandardMOS I • BodyC-rmnt ~ I W=,5~.m, Technobw-E / i .

10"4~

~ =o%=-~-~". \ ,LlP~.~s I "~,,

~ / / ~ . ..$,~/=o, . . . .

.

• ,ot \, 10

.

.

.

.

.

.." .

-0.7 -0.5 -0.3 -0.1 0.I 0.3 Gate Voltage (V)

Fig.23

1o-~ ,

-!

/.,o,

-°

.

i

10

..'. ,o-,

y

".....

10-4

.

0.5

,o-,O

0.~

10-7

0

Subthreshold characteristics of DTMOSFET and standard one [29]

results in high drain current. Subthreshold slope becomes also steeper as shown in Fig.23. This technique is useful to obtain high drain current under low supply keeping subthreshold leakage suppressed.

10-6 10-5 10 .4 Id [A/pm ]

10-3

Fig. 24 Analog MOSFET: f r v s I d for various Lg

100

•

MOS

o

Si B J T

_O "D

g 0

6.6 Pass transistor logic

In CMOS logic circuit, usually, only the gate electrode is used as the input node of logic signal -- "0" or "1". By applying the logic signal also from the drain or source terminal, the number of transistors can be reduced [7], and thus, the power can be reduced. This is called "pass transistor logic". 7. ANALOG APPLICATION OF MOSFETS FOR RF TELECOMMUNICATION AND LOW VOLTAGE/LOW POWER CONCEPT 7.1 Application of C M O S for R F telecommunication devices With downsizing of M O S F E T s , not only the digital characteristics, but also the high frequency analog characteristics show great progress. Figure 24 shows fr values of M O S F E T s with various gate lengths. More than 100 G H z is obtained in sub-0.1 llm gate length case. The trend of f'rvalue is now already better than that of Si bipolar transistors as shown in Fig. 25 [30]. Even, more

~'

10

OD 1

o

O

7s

80

'ss

2000

Year

Fig.25 iT trend for CMOS and bipolar than 150 GHz of fwvalues were observed with 1.5 nm gate oxide n-MOSFETs [25]. Also, high frequency noise at 2 GHz improves significantly with reduction in gate length as shown in Fig. 26. NFm= value of 0.6 dB at 2 GHz was obtained for n-MOSFET [31]. In order to reduce the noise, reduction of the gate and source resistance by salicide is very effective. Thus, front-end RF analog will become a very attractive application in near future. Not only for the small signal devices, but also for the large signal devices such as power amp, silicon MOSFET shows a good results as shown in Fig. 27 [32].

23

H. Iwai, H.S. Momose/Microelectronic Engineering 39 (1997) 7-30

2.5 20 ~" " _c 1.5 E1

m0

In the case of R F power M O S F E T s , the situation is different, and power efficiency degrades by reducing the supply voltage as shown in Fig. 29 [33]. However, the efficiency can be maintained by optimizing the device parameters as shown also in Fig. 29, and the same high efficiencies were obtained both in 3 and 1 V cases [33].

" "'" .... oLf=2.0GHz5 pm,Wg = 2 0 0 c p m /" no o../jl~/~j/ silicid -'~OEfJ M'

"0

05

8o NiSi .

.

.

.

.

.

i .

.

~-y_g = @~m,mx Lg = 0.09/.t m~ I Lf=5/Jm ~ I

.

_W I

,~

o.ls.ml

"~" t/../"

80 Lf=5Opm9OOMHzWg=800pm . . . . Vd=3Vll c "~

.=

~"

1.SGHz ~

,~ L ' b 40 ~g~d"w.F"~.~_ 2.0GHzfo ° ~ ~ [44%~ o o a o 20 " " o° ~ ; o (54%)

o

~ =

°o

20~

I

/ | / | ]

~

0.0

0.5

1 ~.0 1.5 Vd [ V ]

2.5

2.0

(a) Dependence of iT on Vd for various Lg MOSFETs

I

eo

~,~...., ........ . v,,-..-~ ,~vl

Vof@gm~

(dBm)

6(

Fig.27 Efficiency of RF power Si-MOSFETs 7.2 Possibility of low voltage operation for RF CMOS For the RF telecommunication devices, supply voltages of 6 - 3.6 V are used now. What would be RF characteristics of MOSFETs under low power supply. Figure 28(a) shows the dependence of fw value on supply voltage. It is fortunate that fwvalue does not degrade very much by lowering the supply voltage until Vd = 0.5 V [30]. As a results, DC power can be reduced significantly without degrading the RF performance by reducing the supply voltage as shown in Fig.28(b).

m

o

-30 -20 -10 0 10 20 30 Pin

o.2e ~, mt

U==~5 t i m w o = 200 ju m

toy. •

o.sv I , i /~

o~I ~/

~ (94(

. ~

~ = oi . , v /

t":>~.I

"

'

i.!

(

2(

4"/ C

lO-e

~

10-5

It

104

10-3

DC power [ W //~ m ]

(b)

Dependence of iT on consumption ( = Vd X Id)

DC

power

Fig.28 iT characteristics of n-MOSFETs under low voltage

24

H. Iwai, H.S. Momose/Microelectronic Engineering 39 (1997) 7-30

50

2V

o o

4o

z IV

10

"

0

- -

-30 -20

I

-10

10

I

0 lO Pin(dBm)

20

30

j

20 10

0 -30 -20

~

-3O -2O -10

o o o o O

30

Vd=2.0V

0 t

i

Wg--800Fm

40

o O O

30

20

60

6o, W ~ ) p ' m

[ Wg---800/~m~ o 3 V

lO 0 l~dBm)

20

30

Vd=I.0V -10

0 10 Pin(dBm)

20

Lg=0.2~

Lg=o.2~

Tox=lS~a N- 5.0E13¢m2 Co Salicidc

Tox=10nm N- 2.0E14cn/2

Tox=5nm N" 2.0E14cm"2

Co Salicidc

Co Salicidc

30

Fig. 29 Improvement of power added efficiency of Si RF power MOSFETs under low voltage by optimizing device parameters 8. LOAD MAP OF LOW VOLTAGE/LOW POWER What would be the load map of supply voltage for future 15 years? It depends on the application and difficult to comment in general. However, for high-speed logic devicess and battery operated devices, it has been proposed, as shown in Table 7 [13, 28, 34]. year

95

98

Ol

04

07

10

LB Qum)

0.35

0.25

0.18

0.13

0.10

0.07

I-fighend c~op

V(V) 3.3-2.5 2.5-1.8 1.8-1~ 1.5-1.2

Lowpower V(V)

e~y

2.5-1.5 1.5-1.2 1.8-0.cJ 0.9-0.8

1.2

0.9

1.2 -

supply voltage is different for each parts. The base band part (BB) is composed of digital circuits for computation, and is going down to below 1.8, 1.2 and sub IV as device dimension reduces to 0.18, 0.12 and 0.07 ~tm. The RF/IF part is composed of analog circuits such as LNA (Low noise amp.), mixer, VCO (voltage controlled oscillator). It is said to be difficult to reduce the supply voltage of the RF/IF part due to the decrease of the dynamic range of analog signal. However,

0.9

0.9

Switch .

Table

7 Load map of supply voltage

Regarding mobile devices such as RF handy phone, supply voltage cannot be decided by the transistor characteristics, but system architecture and battery nature will decide the supply voltage load map. Telecommunication chip set is composed of several parts as shown in Fig.30. The optimum

- * Antenne~" .

.mS

RF/IF ..~ a n a l o g

_.

medium voltage

L J-'I

digital lower voltage

r--~l -

,

" ' '

hlQ.h~r vomlge

Fig. 30 Mobile telecommunication chip set

H. Iwai, H.S. Momose/Microelectronic Engineering 39 (1997) 7-30 the required dynamic range depends on the system architecture. Lower supply voltage would be possible by designing the system architecture and specification taking account the low power/low voltage device characteristics. The power amp part (PA), or the RF output part is quite different from the above 2 parts. At first, the power consumption is basically determined by the AC output power defined by each telecommunication system specification. DC to AC power efficiency is already 50- 70 % and no drastic improvement can be expected by the device improvement. Secondly, it could be possible to reduce the supply voltage from 3 to 1 V without degrading the efficiency, as already described in the previous session. However, 3 times larger current is necessary in the 1 V case. For example, 3A is necessary for 3W GSM transmiter even if the efficiency is 100%. This would be a big problem, because the lifetime of the battery is reduced when the current is large. Thus, it would be difficult at this moment to reduce the supply voltage of PA unless a good battery with high lifetime for low voltage appears. Thus, suitable supply voltage is different depending on the parts. High efficiency DC to DC converters which give appropriate supply voltage to each part will become important. There is another category for low power/ low voltage technologies. If the. speed is not a concern, considerably low power should be accomplished by raising the threshold voltage under low supply and lowering the clock frequency, although the parameter variation should be considered. This category is out of the scope of this paper will not be described. 9. PROSPECTIVE ON THE DEVELOPMENT OF SILICON LSIS FOR FUTURE. WHAT IS BEYOND CMOS? 9.1 Limitation of LSI

The 40 nm gate-length MOSFET genera-

25

tion corresponds to 128 Gbit DRAMs. Thus, in terms of MOSFET transistors, those for 5.5 more generations of DRAMs - - or 16.5 years more miniaturization - - should be guaranteed by the experiments, assuming that 64 Mbit DRAMs are just entering mass production. Also, 20 nm MOSFETs corresponds to 512 Gbit DRAM which might be 22.5 years later. It should be remembered, though, that success at the single-transistor level is not per se sufficient for the realization of LSIs. There are also several reasons for pessimism regarding prospects for the realization of such ultra-high-density LSIs using ultra-small geometry MOSFETs.: variations in the characteristics of so many transistors, the high contact resistance of smallgeometry interconnects, huge power consumption, and huge production costs. Table 8 Limits for LSI Fundamental Limit (< 10 nm)

Atomic distance, Thermal noise Uncertainty principle, Speed of light Single Transistor level Leakage current Short-ch. effect, B to B tunneling Tunneling gate oxide Technological On resistance Velocity sat., Dopant solubility Limit LSI level (25 ~ 20 nm) Ultra-huge number of components Yield, uniformity, Reliability Power cousumption Inability to design with huge number Complexity Limit of components (? nm) Circuit / system Design time, Test time Cost increase Economical Sophisticated Limit (? nm) device structure / process / equipment

Now, we will discuss the limits of LSIs and try to provide an image of future silicon LSIs. When discussing the future of LSIs, it is necessary to consider four limits; fundamentals, technology, complexity and economic factors as shown in Table 8. The fundamental limit is that imposed by the laws of physics. For example, when the device size is extremely small, the signal from the device becomes less than the thermal noise at room temperature. The feature size of this limit is believed to around 0.01 ~m or 10 nm, which

26

H. Iwai, H.S. Momose/Microelectronic Engineering 39 (1997) 7-30

will not becomes the limiting factor on the LSI products in 25 years. The technological limit is that imposed by the difficulties of the technology required to fabricate such high-density LSIs capable of high-speed operation. The difficulties in realizing ultra-small-geometry MOSFETs as described in the previous sections are good examples. For instance as mentioned above, we estimated the practical limit of the silicon MOSFET gate length to be around 20 nm as described in the above. But, this limit might be circumvented and replaced by a less onerous limit by substituting other semiconductors for silicon, or by inventing new structures or changing the operating temperature. When considering the technological limit of the high-density integration, variation and yield of a huge number of the transistors, large signal delay of the long line interconnects, and the large amount of heat generated by the huge number of the transistors are the big concern. These problems would be solved to a certain degree by adopting a new concept for the system design of LSIs. Redundancy of the circuit and logical decision by majority rule will preclude the huge variation of the transistor characteristics. Hierarchical design and local transaction within regional system blocks such as that characterizing interplanetary long-distance communication as in the case of the Voyager mission would partially solve the signal delay problem. Huge power consumption will be solved by the development of power management and saving technique in the system and circuit design. Remember the "Off Crisis" period. Necessity is the mother of the invention. In addition, it should be noted that superhigh integration of the transistors is not the unique application of ultra-small-geometry MOSFETs. By taking advantage of high frequency and high speed operation of such a small gate-length MOSFETs, there should be large promising market for high frequency analog applications with smaller scale inte-

gration, such as chips for RF mobile telecommunication. It should be noted that fT value of 0.1 ~m CMOS is more than 100 GHz, which already higher than that of most advanced silicon bipolar transistors. The complexity limit is that imposed by human ability to design very large systems using a huge number of transistors. In the case of the memories, we can put as many transistors as possible, but in the case of microprocessors, it is said to be difficult to design a single microprocessor system using more than a 10 million transistors. Future CAD development might solve this problem and system shifts towards parallel multiprocessors that are easier to design. The economical limit is that imposed by the skyrocketing increase of the production cost of the LSI due to the sophisticated structure and process for the very high density LSIs. Now making a 64 Mbit d-RAM production line costs one billion dollars. There is a question whether it will be possible to secure a profit if the production cost continues to increase with each successive generation. Especially, at present, the question how to realize an economically feasible lithography stepper for the 0.1 ~m generation remains unanswered. Every effort should be made to ensure that the structure and process are as simple as possiblel Otherwise the evolution of the very sophisticated three-dimensional d-RAM cell will be similar as that of the very sophisticatedly evolved shell structures of fossil Ammonite, and might become extinct. Also, the economy size of the world cannot support the rapid growth of the development and production cost of LSIs. Considering the situation described above, it is clear that both technological and economic limits preclude the continuation of high growth rates like those we have seen so far. Figure 31 shows a road map of the future DRAM products made by the simple extrapolation of the past trend. Will this constant rate of rapid growth in the integration con-

H. IwaL H.S. Momose/Microelectronic Engineering 39 (1997) 7-30

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tinue until 2010's or for more than 40 years from the lk bit d-RAM generation? It is interesting to take a look at the trends of the tonnage of super oil tankers and the speed of the passenger airplane. The weight tonnage of the tanker increased with a rapid constant rate for 20 years and then suddenly stopped to increase at a half million weight ton as shown in Fig.32. The speed of the passenger airplane increased for 60 years and stopped at the velocity of the sound except in the case of Concorde as shown in Fig.33. These results suggest the growth of the integration of LSI will be suddenly stop in some future, which we are unable to predict at present. 9.2 Beyond CMOS? Simple extrapolation suggests that 128 Gbit DRAMs will be realized in 4 x 4 cm 2 dies and 25 G-gate MPUs will be made with 7 x 7 cm 2 dies in 2010's. (Real die .size will be larger, because the width of the interconnects cannot be decreased at the same rate as the gate length.) But 128 gigabits is a figure corresponding to the number of stars in our galaxy. Thus, making the 128 Gbit is a work similar to making a extremely fine miniature of the Galaxy in a disk with 4 cm radius. Is it realistic? As regards the memory, there is a strong demand in the image processing application. If we compare system LSIs such as microprocessors with living things, we see that life does very well indeed. The brain of a mosquito, with many

1950

~300

fewer cells in a compact space, has extremely good performance: the equivalent of artificial intelligence, real-time image processing and recognition, three-dimensional flight calculation. It should be noted that the power consumption of the mosquito brain is extremely small, and also it's cost is extremely cheap. The three-dimensional flexible layout and connection of an insect's brain is almost impossible to achieve with today's production methods, and this situation will continue for several tens of years. It is very useful to analyze the mechanism or algorithm of brain system and apply it to LSI in a part even by using today's multi-layer interconnects. As described in the previous section, progress of CMOS LSIs in a current style will reach the limitation in 30 years. What would come after the CMOS? Beyond the CMOS might be another CMOS or even bio system itself. It is hard to predict it now, From the system point of view, the system of life is very attractive in order to break though the limitation. For this purpose, it is impor. tant to start the analysis of the algorithm and architecture of the bio system. In this sense, 'beyond CMOS' could be said to be 'new system architecture' or 'new algorithm'. There is at least much more efficient system -- bio -than present CMOS LSI. The new system architecture and algorithm would determine 'beyond the CMOS' in device, circuit and system levels.

28

H. lwai, H.S. Momose /Microelectronic Engineering 39 (1997) 7-30

10. CONCLUSION

ll. REFERENCES

Device/process technologies for low power /low voltage high-end logic devices are not very different from the most advanced CMOS scaling technologies. For example, high drain current under low supply voltage is necessary in order to maintain the high speed operation of LSIs under low supply voltage. For this purpose, gate length should be smaller and oxide thickness should be thinner. Source/drain is desirable to be silicided in order to reduce the resistance. Threshold voltage variation should be smaller and subthreshold slope should be steeper to suppress the off-leakage current. Thus, the low power/low voltage technologies have been developed in an orthodox and steady approach from the device/process side. However, each technology used for low power/low voltage is often most advanced one such as ultra-thin gate oxide. On the other hand, there are variety of approach from the circuit and system side as briefly described in this paper. For other kinds of devices, such as mobile telecommunication chip set, the low power/low voltage depends much on the architecture of the system. As the device size reduces to deep sub-0.1 ~tm, some practical scaling limit would be expected. However, it would take more than 15 years for the LSI products to reach the limitation, and there are many process/device technology items to be developed u.ntil them. In order to break through the expected current CMOS limitation in the scaling and also in low power/low voltage operation, development of completely new system architecture and algorithm is inevitable. We know at least that system of life such as a brain works with extremely high performance and low power consumption compared with today's CMOS system. We hope a new system architecture and algorithm will break through the CMOS limitation in near future.

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