Threshold voltage of small-geometry Si MOSFETs

Sohc/-Slurc I~7ewo1rrc.s Vol. 29. No. 4. pp. 409-419. 1986 Printed in Great Britain.

THRESHOLD

0038-1101/86 $3.00 + .oO c6i1986 Pergamon Press Ltd.

VOLTAGE OF SMALL-GEOMETRY MOSFETS

Si

THOMAS A. DEMASA and Ho SHENG CIIIEN Department of Electrical Engineering, Arizona State University, Tempe, AZ 85287, U.S.A. 21 May 1984)

(Received

Abstract-This paper uses an accurate, three-dimensional geometrical model for calculation of the threshold voltage of short-channel and narrow-width (small-geometry) silicon MOSFETs. The model expresses the threshold voltage as a function of channel length, channel width, source- and drain-junction depth, backgate bias, drain voltage, gate-oxide thickness and substrate doping concentration. The model also predicts the backgate and drain voltages for punch-through to occur for small-geometry MOSFETs. NOTATION Description dielectric constant of oxide (3.45 X lo-r3 F/cm for SiO,) dielectric constant of semiconductor (1.045 x lo-‘* F/cm for Si) oxide capacitance per unit area (F/c&) charge sharing factor Boltxmann potential (25.86 mV at 300 K) channel length of MOSFET (cm) effective channel length of MOSFET (cm) narrower base of tra&zoid (cm) . ’ acceptor concentration (atoms/c&) donor concentration (atoms/&) intrinsic carrier concentration (atoms/c&) electronic charge bulk charge (coul) total bulk charge in the depletion region (coul) effective bulk charge in the depletion region (coul) charge on gate electrode (coul) channel depletion charge (coul) charge in the inversion region (coul) fixed charge in silicon oxide (coul) lateral charge (coul) junction depth of the drain and source (cm) gate oxide thickness (cm) thick oxide thickness (cm) built-in potential of a P-N junction (V) (kT/9)ln(&%/nf) backgate bias (v) drain voltage (V) flat-band voltage (V) gate voltage (V) voltage across the oxide (V) threshold voltage (V) depletion depth under gate oxide (cm) (triangular condition) depletion depth under drain region (cm)

depletion depth under source region (cm) width of drain depletion region at the surface (cm) width of source depletion region at the surface (cm) Fermi level potential of the substrate (V) metal-semiconductor work function difference (V) surface potential (V) channel width of MOSFET (cm) 1. INTRODUCTION Current progress in both electron-beam lithography and photolithography has led to the fabrication of MOSFETs with smaller and smaller channel dimen409

sions. However, as the device sire shrinks, two depar-

tures from long-channel behavior occur. These departures can be studied independently and are referred to as the short-channel and narrow-width effects. The behavior of short-channel MOSFETs has been investigated by several authors[l-lo]. Cheney and Kotch[l] were the first to consider the short-channel effects, but only for the case of a backgate bias high enough to obtain punch-through conditions. Their model included the effect of the junction depth of the source and drain diffusion. Lee[Z] used a charge-neutrality condition to derive an expression for the threshold voltage. His threshold-voltage expression included the effects of channel length, oxide thickness, junction depth and drain and backgate voltage. Varshney[3] extended the theory to low backgate bias by using two, simple, two-dimensional approximations in conjunction with a charge conservation analysis to explain the influence of the channel length. This analysis does not include drain voltage and junction depth. Yau[4] and Poon[5] correctly formulated a simple model of a short-channel MOSFET from a geometrical approximation of the charge sharing in the bulk with the source and drain islands. Their model describes a simple and accurate expression for the threshold voltage including the junction depth, but fails to include the drain voltage. Bandy and Kokalis[6] developed a shortchannel model using various approximations to obtain formulas for the threshold voltage. Coe[7] applied two-dimensional numerical calculations to improve the expression of threshold voltage by a fitting procedure. In this way, he obtained correction terms. Chatherjee[8] derived a simple model to predict the charge sharing factor when the drain voltage is applied. His model disobeys the fact that the bulk charge is decreasing as the drain voltage is increasing. Taylor[9, lo] has modified the trapezoidal approximation as proposed by Yau and Poon to model the dependence of threshold voltage on the drain voltage as well as the channel length. For the simplified case, he assumed the junction depth of the source and drain regions is much larger than the

410

T. A. DEMASSAand H. S. CHIEN

depletion depth under the gate electrode. All of these models assume no variation of parameters in the width direction. In contrast to the short-channel length, the narrow-width also has a significant effect on threshold voltage [ll-151. Jeppson [ll] used a simplified MOSFET cross-section without the thick oxide and developed an analytical threshold voltage expression for the narrow-width MOSFET. Kroell and Ackermann[12] gave a numerical treatment of the narrowwidth MOSFET. They solved Poisson’s equation numerically using a simplified set of boundary conditions to calculate the threshold voltage. Akers[l3] and Merckel[l4] have derived a simple closed form analytical expression of the threshold voltage for a narrow-width MOSFET. Their expressions were developed using a geometrical approximation of the charge that spreads under the thick oxide region. Recently, Akers[15] has further developed a closed form expression for the narrow width MOSFET which includes the effects of tapered oxide capacitance and field doping encroachment. For the small-channel MOSFET, neither the short-channel nor the narrow-width expression is sufficient to predict the threshold voltage. Therefore, the threshold voltage expression for the smallchannel MOSFET must be appropriately modified. Jeppson[ll] extended Lee’s model to include the narrow-width effect. His model requires two fitting parameters. Wang[l6] assumed the short-channel and the narrow-width effects are independent and formulated a simple algebraic equation to predict the threshold voltage for the small-channel MOSFET. Akers [17] and Merckel[15] have derived simple closed form solutions to predict the threshold voltage for the small-channel MOSFET. Their models include the short-channel, narrow-width and lengthwidth cross coupling effects. Both of these models assume that the drain voltage is very low and approximately zero. The purpose of this paper is to obtain an expression to predict the threshold voltage for small-channel MOSFETs. The model used is a three-dimensional geometrical approximation in conjunction with charge conservation. Theoretical curves are illustrated to show the threshold voltage of a small-channel MOSFET as a function of substrate doping concentration, channel length, channel width, junction depth, oxide thickness, drain voltage and backgate bias. Also, this model will be compared with models of Akers[17] and Merckel[l4].

2. SMALL GEOMETRY MOSFET MODEL FORMULATION

2.1 Assumptions Used in the Formulation There are three geometric effects on the threshold voltage of the MOSFET; these are 1) the short-channel effect, 2) the narrow-width effect and 3) the small geometry effect. In order to simplify the analysis, the

following assumptions

are made:

1. N-channel MOSFET with $J~= 2$F. 2. P-type substrate with uniform doping concentration. 3. Source region is comected to ground. 4. Transition between gate and thick oxide is abrupt at the edge of the channel width. 2.2 Long-channel MOSFET In the long-channel MOSFET, the threshold voltage is obtained simply by applying the charge conservation principle in the region bounded by the gate electrode and bulk of the semiconductor. The usual charge equation is simply e,+e,,+e,+e,=o

(1)

where Q, is the charge on the gate electrode, Q,, is the fixed surface charge in the silicon oxide, Q, is the charge due to the free carriers in the channel region and Q, is the bulk charge due to the ionized impurity atoms in the depletion region. The external gate voltage is distributed across the oxide and the surface layer, such that

where Vo is the gate voltage, V,, is the voltage across the oxide, J/, is the surface potential, (p,,,,is the work function difference between metal and semiconductor and Q,, is the interface charge. Under the assumption that all the charge in the semiconductor resides in the depletion region when the surface potential is equal to twice the bulk Fermi level potential (i.e. I/J,= 2+,, Q, = 0), the threshold voltage is obtained as the gate voltage required to achieve strong inversion with #, = 2+, (where $F = (kT/q)ln(N,/n,)). Combining eqns (1) and (2) yields an expression for the threshold voltage of the MOSFET as follows:

VT= vFE+ 2+F +

Q/3 Co,

ZL

where VFB is the flat-band voltage to include the effects of fixed surface charge and the work function difference between metal and semiconductor, C,, is the oxide capacitance per unit area, Z is the channel width and L is the channel length. Equation (3) is only valid as long as the channel length is much longer than the junction depth of the source and drain and the width is much wider than the depth of the depletion region. For short-channel, narrowwidth or small-geometry devices, these two conditions are not fully satisfied. Therefore, the equation of threshold voltage must be appropriately modified. 2.3 Short Channel MOSFET Figure 1 shows a sectional view of the short-channel MOSFET for the case of very small drain voltage

Threshold voltage of small-geometry Si MOSFETs

411

and XX= x, =

2E,( Vhi- 24,) 9&

1’2 (9)

I

Also, L,//= L - 2x*

(IO)

where ‘J is the junction depth of the source and drain, and VBGis the backgate bias. Hence, the resulting equation for threshold voltage for the short-channel MOSFET is modified as b "EIG Fig. 1. Short-channel model structure with VD = 0.

=&3+2+,-e (i.e. V. on the order of 10 mV). For this case, the model proposed by Yau[4] and Poon [5] provides a simple and reasonably accurate model of the dependence of threshold voltage on channel length. According to their model, a significant fraction of the electric-field lines associated with the gate charge is terminated on the source and drain depletion region charge. Hence, the full effect of the bulk charge is reduced. Referring to Fig. 1, the field lines originating from the charges inside the trapezoidal depletion region are terminated on the gate electrode, whereas the field lines from the charges outside the trapezoidal region are terminated at the source and drain junction. Based on this geometrical approximation, the effective bulk charge QElce,,, inside the trapezoidal area must replace the usual QB where

Q,,e//, = FQB

(4)

Q, = 6%W-K-,,

(5)

with

and F is the charge sharing factor defined as F = area( ABC’D’) area(ABCD)

x

l

1_

9%WL, c

L

KYw2]1/2-q-xs

[(q+

L-2X,

1.

(11) As a special case, if V,,i= 2+, and VBG= 0 (i.e. W = W, = W, , X, = X, = 0), then the charge sharing factor is identical to that of Yau[4] and the expression of the threshold voltage is[4]

(12) Note that as the backgate bias is increased the depth of the depletion region is also increased. Referring to Fig. 1, points C’ and D’ are pulled downward and move further toward the center of the gate depletion region. If the backgate bias is sufficiently large, the source and drain space charge regions finally begin to overlap, and then the surface of the depletion region under the gate electrode becomes triangular as shown in Fig. 2. The depth of

Referring to Fig. 1, by geometrical considerations (Appendix A)

F=l_

lb+M2- wy2-q-xs.

(6)

L-2X* Additionally, the depletion region width expressions (see Fig. 1) are each defined by the particular voltage across the particular depletion region as follows:

%(wJF+ VP,>1’2 9% ’

I

w, = w, =

(7)

1 ’ (8)

2<,( V-&+ I/Be) ‘I2 9%

Fig. 2. Gate depletion region under high backgate bias.

412

T. A. DEMASSAand H. S. CHIEN

the depletion region at the onset of this transition (defined as W’) between trapezoidal and triangular shapes (i.e. L’ = 0) is then _

where W, and X, were given in eqns (8) and (9),

w=((y-$)(~+$+q))“‘.

1 ’ (16)

2c,( V,, + V, + V,,)

w, =

1’2

4%

(13) and

By considering the geometry of Fig. 2 under this condition, the charge sharing factor becomes 0.5 (a triangle having half the rectangular area) and the threshold voltage is given by

qN,W’-L.// vT=

vF’B+2+F+

~c,,L

.

(14)

For the case of larger drain voltages (i.e. V, z+ 10 mv), the depletion region near the drain expands further than that at the source. Therefore, Yau and Poon’s model was modified as shown in Fig. 3 [9, lo]. The charge in the channel is assumed to be partitioned into three regions. The field lines in regions I and III terminate at the source and drain diffused regions, respectively. In region II, all electric field lines terminate on the gate electrode. Based on this geometrical configuration, the effective bulk charge in region II is further decreased when the drain voltage is increased. Referring to Fig. 3, the charge sharing factor F is defined as F = area( ABC’D’) area( ABCD) ’ Or by geometrical Appendix B)

considerations

F=l_

[(q+

.),-

(see Fig. 3 and

w2y2+[();+

2e,(Vbi+

Vo-2cP,) @A

1’2 I

(17)

Hence, the threshold voltage for the short-channel MOSFET is modified as q% W&n// vT=

vFB+2+F+

,&L

x(l-([(q+w,)2-wq1’2

+[(‘I+

,),-

wy2

-25-x,-X,)/2(L-X,-X,)).

(18)

Note that if V,,i= 2$, and VD = 0, the charge sharing factor is identical to that of Yau[4] and the expression of threshold voltage is equal to eqn (12). Also, in this analysis, if either the backgate bias or drain voltage is large enough, the source and drain depletion regions will merge together. The depletion region under the gate electrode becomes triangular and the depth of the depletion region at the onset of the transition between trapezoidal and triangular

,),-

wq’2-2q-xS-xd

2(L-X,-X,)

shapes is then given by (see Appendix B) W’=

1

[2(2’,+ -

[(

w,+ w,)]’

L+25)2-(5+

-(I;+

w,)’

w,)z]2}1’2,2(L+21;).

(19)

When this merging occurs, the charge sharing factor in this region is simply

F =

Fig. 3. Short-channel model structure with V, > 0.

Therefore,

area( ABE) area(ABCD)

the resulting

= OS’

(20)

threshold voltage is given

Threshold voltage of small-geometry Si MOSFETs

by VT’ &J + 2@f+ which is identical

NW&// 2C,,L

(21)

threshold voltage of the MOSFET. Therefore, the threshold voltage for a narrow-width MOSFET becomes[l3,17] vr=v,,+2+,+c

to eqn (14).

2.4 Narrow-width MOSFET In contrast to the threshold voltage decrease for short-channel MOSFETs, narrow-width MOSFETs exhibit an increase in threshold voltage. Figure 4 shows the device cross section in the width direction; the gate metal overlaps the thick oxide on both sides of the gate. At a certain gate voltage, the thick oxide depletion region is always shallower than the gate oxide depletion region because of the higher threshold voltage of the thick oxide region. With increasing gate voltage, the channel depletion region spreads into the substrate and under the thick oxide region. If a backgate bias is applied, the depletion region will spread further into the substrate, but not into the thick oxide region. Therefore, the lateral spreading width under the thick oxide region is the width at the condition of zero backgate bias[17]. Hence, it is assumed that the lateral spreading width is just dependent on gate voltage and independent of backgate bias and drain voltage. Referring to Fig. 4, the effective depletion charge is the sum of the lateral extra charge and the ideal bulk charge, and can be expressed as

Q,,e/,, = QB + Qw

in which the narrow-width the last term.

qN,W I+2 OX (

1

additional

component

(24) is

2.5 Small Geometry MOSFET The threshold voltage decreases as channel length decreases but increases as device width decreases. In order to accurately predict the threshold voltage of the small geometry MOSFET, the total bulk charge in the channel accounting for short-channel and narrow-width must be considered. Figure 5(a) illustrates the depletion region of the small geometry MOSFET under the condition of. applied drain voltage. The total bulk charge in the depletion region is the sum of the charge in the channel depletion region QL and the lateral charge Q,. Hence, the total charge in the depletion region of the device is

Q,=Q,+Qw.

(29

The channel depletion charge (Qt) is determined from Fig. 5(a) and geometrical considerations as follows:

(24

where Q, is the ideal bulk charge, and Q, is the lateral extra charge accounting for both regions under the thick oxide. Using a triangular geometrical approximation, the total lateral extra charge can be obtained as

Q, = dVW,L

413

where L e/f = L - x, - &

(27)

L’=L,//-L,-L,

(28)

and

(23)

where W, is the width of the depletion region spreading under the thick oxide W, = (2c(2+,)/qN,)1/2. The lateral extra charge on both sides of the gate contributes an added voltage component to the

and L, and L, are obtained from the following equations by consideration of the geometry: (r,+x,+LJ2+W2=(~+ws)2

(29)

(rj+xD+LJ2+wz=(~+w~)2.

(30)

and

By substitution

Q, = dYAW%.// IDEAL DEPLETION BOUNDARY

ACTUAL DEPLETION BOUNDARY

I

X(1-([((if

w,)‘-

0 "BG

+[(‘I+

Fig. 4. Depletion boundary of a narrow-width MOSFET.

-2r;-x,-X,)/2(L-X,-X,)).

SSE 29:4-c

wo),-

lVz]1’2 wz]1’2 (31)

414

T. A. DEMASSAand H. S. CHIEN

(4 I

Fig. 5. (a) Three-dimensional depletion region of a small-channel MOSFET at VD 7 0. (b) A right wedge.

Hence, the threshold voltage for the small geometry device is

The total lateral charge Q, is obtained from

4NA wL, vT=

vFB+

2+F+

C,,L

where V is the volume of the additional charge on the width edges. The geometry of each edge region is that of a “right wedge” given by [see Fig. 5(b)] V=@b(2a

+ a’).

+[(q+

For the geometry of Fig. 5(a), the constants for each and wedge are a = Lcff, a’=L’, h=w and b-w, thus by substitution the total volume (both edges) is

v=7(2L,//+

L’)

(32)

where L,, , L’, L, and L, are obtained from eqns (27)-(30). By substitution, Q, is obtained as

w,)‘-

w2]1’2-2Pj-xS-xd)/

(L-X-X,)]}.

(34)

For a certain drain voltage, if the backgate bias is very large, the depletion region under the gate electrode will again become triangular. At the onset of the transition between triangular and trapezoidal shapes, the channel depletion charge and the lateral charge are

Q, = d%ww,Le/J

+([(r,+

w,)‘-

(35)

w2y2 and

+[(‘;+ ,),-25-x,-X,)/(L-X,-X,)).

w2y2

Q:, = fqN,W,L,,,W’ (33)

(36)

where the value of W’ is equal to that of eqn (19).

Threshold voltage of small-geometry Si MOSFETs

415

Under this condition, the threshold voltage for the small geometry MOSFET is simply

vT=

vFB+2+F+

(j&L

(37)

’

: -

3. RESULTS AND DISCUSSION FOR THE SMALL GEOMIWRY MOSFET

Computer programs were written to obtain the variation of threshold voltage of the small geometry MOSFET with various device parameters. These parameters include the following: channel length, channel width, substrate doping concentration, backgate bias voltage, drain voltage, junction depth and gate oxide thickness. The fixed values used in the calculations were the following: intrinsic carrier concentration n, = 1.5 x 10” atoms/cm, drain/source doping concentration No = 1 X 1019 atoms/cm, substrate doping concentration NA = 1 x 1016 atoms/c&, flat-band voltage V,, = -0.35 V, backgate bias V,, = - 1 V, drain voltage V, = 1 V, 500 A gate oxide thickness, 3 pm channel width and 0.5 pm junction depth.

!2

0

2.10 i N,-1.5~10

I6

ATOMS/CM3

l.50-

8 # F

LIO-

0.30 0.00

, 0.04

I 0.06

CHANNEL

Fig. 3.1 Effect of Substrate Doping Concentration Figure 6 shows the effect of substrate doping concentration on the threshold voltage as the channel length is reduced. As the substrate doping concentration is increased, the threshold voltage will increase as shown in Fig. 6. Also, for a fixed substrate doping concentration, the threshold voltage decreases as the channel length decreases.

2.30 I

7.

I 0.12

LENGTH

(CM)

I 0. I6

I 0.20

* lo2

Threshold voltage versus channel length for various backgate biases.

3.2 Effect of Backgate Bias Figure 7 illustrates the threshold voltage versus channel length for various backgate biases with NA = 1016 atoms/cm. For a fixed backgate bias, the threshold voltage decreases for decreasing channel length. If the backgate bias is increasing, the threshold voltage also increases. If a certain drain voltage is applied and the backgate bias is large enough, the phenomena of punch-through will occur. Table 1 shows the computed values of punch-through backgate bias with various values of drain voltage, channel length and substrate doping concentration.

Table 1. Computed values of punch-through backgate bias

9x10'5

1

0.8

1x10'6

1

2.1

16

1.5x10

0.60

o.ooL 0.00

I

0.04

CHANNEL

I

0.06

LENGTH

I

0.12

(CM)

I

0. I6

I

0.20

* lo2

1

4.2

9x10'5

1

0.7

1x10'6

1

1.1

1.5x1016

1

9x10'5

2.

23.6

1X1016

2

26.7

2

42.0

2

21.4

2

24.4

2

39.7

1.5x10

9x10'* 1x10

Fig. 6. Threshold voltage versus channel length for various substrate doping concentrations.

16

16

1.5x10'6

3.1

T. A. DEMASA and H. S. CHIEN

416

It can be seen that the punch-through backgate bias is higher for low drain voltage and long channellength devices and lower for high drain voltage and short channel-length devices. Furthermore, the punch-through backgate bias is increased as the substrate doping concentration is increased.

3.3 Effect of Drain Voltage The effect of drain voltage on the threshold voltage for a fixed backgate bias is shown in Fig. 8. The threshold voltage is reduced for higher drain voltages in the short channel length region. Also, for a fixed drain voltage, the threshold voltage is reduced as the channel length is decreased and if the drain voltage is continuously increased, the device will enter the punch-through situation. As expected, at the onset of punch-through, the drain voltage values in Table 2 are higher for low backgate bias and long channellength devices and lower for high backgate bias and short channel-length devices. Additionally, increasing the substrate doping concentration causes the punch-through drain voltage to increase. Comparing Table 1 and Table 2, it can also be observed that the required drain voltage values for punch-through are larger than the required backgate bias values. 3.4 Effect of Junction Depth The calculations showed very little effect of junction depth on the threshold voltage for ‘J values from 1 to 8 pm. Generally, the depletion depth under the source and drain region is greater than the junction depth. Hence, the small variation of threshold voltage with junction depth was expected.

s

PBGl (“1

L(w)

V,(V)

1

9x10'5

1

1.7

1x10'6

1

3.0

1

1.5x10 16

1

4.5

2

9x10'5

1

0.7

2

1x10'6

1

2.0

2

1.5x10'6

1

3.2

1

9x10'5

2

17.3

1

'Xl016

2

19.7

1

1.5x1016

2

32.0

2

9x10'5

2

15.6

2

1x10 16

2

17.9

2

1.5x1016

2

29.6

3.5 Effect of Gate Oxide Thickness The effect of gate oxide thickness on the smallchannel threshold voltage characteristics is shown in Fig. 9. Referring to the equation of the threshold voltage [i.e. eqn (34)], the threshold voltage is inversely proportional to the gate oxide capacitance. Hence, the threshold voltage increases as the gate oxide thickness increases as shown in Fig. 9. 3.6 Effect of Channel Width Figure 10 illustrates the variation of threshold voltage versus channel length for various channel widths.

2.80-

l.SO-

2.40-

1.25-

NA(cm-3)

1

1.?5-

2

Y z

Table 2. Computed values of punch-through drain voltage

2.00-

% IOO-

2

$

1.60-

e

0.25-

0.001 0.00

I

I

8

I

1

0.04

0.08

0.12

0.16

0.20

CHANNEL LENGTH

(CM)

-2 * IO

Fig. 8. Threshold voltage versus channel length for various . . . ctram voltage.

0.00

0.04

0.08

CHANNEL LENGTH

0.12

(CM)

0.16

0.20

*lCf2

Fig. 9. Threshold voltage versus channel length for various nate oxide thicknesses.

Threshold voltage of small-geometry Si MOSFETs 2.40-

417

2.10-

AKERS

l.60-

s

MERCKEL

l.50-

ii 2

p*

l.20-

MODEL

MODEL

G 9

(vD=Iv) o.so-

P ti Q F

0.60

-

0.30-

1

0.00 0.00

0.04

CHANNEL

0.06

0.12

LENGTH (CM)

0.16

0.20

* lO-2

The threshold voltage increases as the channel width decreases. For a fixed channel width, the threshold voltage is reduced as the channel length is reduced. Figure 11 illustrates the threshold voltage versus channel width for various channel lengths. The threshold voltage is observed to increase as the channel length increases and for a fixed channel length,

2.40-

2.10-

1.60-

: 2

1.50-

@ 9 8

1.x)-

Y

‘L96,m L.6pm

0.90-

I

0.04

0.06

CHANNEL

Fig. 10. Threshold voltage versus channel length for various channel widths.

s

0.00

the threshold

I 0.04

I 0.06

CHANNEL WIDTH

0.12

(CM)

1 0.16

1 0.20

* lCf2

Fig. 11. Threshold voltage versus channel width for channel lengths.

various

0.20

* lc2

voltage

increases

as the channel width

reduces. 3.1 Comparison with Previous Results For the small-channel MOSFET, neither the short-channel nor the narrow-width expression is sufficient to predict the threshold voltage. The threshold voltage for the narrow-width MOSFET overestimates the threshold voltage for the small geometry device. Furthermore, the short-channel expression underestimates the threshold voltage for the small geometry MOSFET. This indicates that there is a degree of “compensation” when the narrow-width or short-channel models are used. However, both of the expressions should be properly modified to predict the threshold voltage for the small geometry device. Figure 12 shows a comparison of three small geometry models. Curve 1 is the Akers[17] model, curve 2 is the Merckel[l4] model, curve 3 is the present model with VD= 0, curve 4 is the present model with VD= 1 V. These curves show a very close comparison with the result that the threshold voltage decreases when both narrow-width and shortchannel effects are considered simultaneously.

4.

’ 0.00

KM)

0.16

Fig. 12. Threshold voltage versus channel length for three models. Curve 1, Akers’ model. Curve 2, Merckel’s model. Curve 3, present model with VD = 0. Curve 4, present model with VD = 1 V.

0.60-

0.30

LENGTH

I

0. I2

CONCLUSIONS

Based on the three-dimensional geometrical approximation and the charge conservation principle, a simple expression to predict the threshold voltage of small geometry MOSFETs was obtained. This expression takes into account the source and drain junction depth, substrate doping concentration,

T. A. DEMASSA and H. S. CHIEN

418

backgate bias, drain voltage, gate oxide thickness, channel width and channel length. The calculated results can be summarized as follows: 1. For the short-channel MOSFETs, the threshold voltage decreases as channel length decreases. 2. For the narrow-width MOSFETs, the threshold voltage increases as channel width decreases. 3. For the small-channel MOSFETs, the threshold voltage decreases as substrate doping concentration, channel length, gate oxide thickness and backgate bias decreases, but increases as channel width, drain voltage and junction depth decreases. 4. The threshold voltage for the short-channel MOSFET underestimates the threshold voltage for the small-channel MOSFET, but the threshold voltage for the narrow-width MOSFET overestimates the threshold voltage for the small-channel MOSFET. 5. The required drain voltage values for punchthrough are larger than the required backgate bias values. 6. For the small-channel MOSFET, punch-through occurs more easily as the substrate doping concentration and channel length decrease, or the backgate bias and dram voltage increase. Additionally, a comparison of the present model with Akers’ [17] and Merckel’s[14] models for various MOSFET channel lengths shows close agreement. The assumptions of uniform substrate doping concentration and abrupt transition of oxide allow a simple geometrical calculation of the threshold voltage for small geometry MOSFETs. For cases in which nonuniform substrate doping concentration and/or tapered oxides are used, the expression for threshold voltage has to be further modified to predict accurate threshold voltages.

REFERENCES

1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16 17

G. T. Chenev and R. A. Ketch. Proc. IEEE 887-888 (1968). ’ H. S. Lee, Solid-St. Electron. 16, 1407-1417 (1973). R. C. Varshnev. Electron. Left. 600-602 (1973). L. D. Yau, Soiih-St. Electron. 17, 1059-1063 (1974). H. C. Poon, L. D. Yau, R. L. Johnson and D. Beecham, IEDM Tech. Dig. 156-159 (1973). W. R. Bandy and D. P. Kokalis, Solid-St. Electron. 20, 675-680 (1977). J. D. Coe, H. E. Brockman and K. H. Nicholas, Solid-St. Electron. 20, 993-998 (1977). P. K. Chatterjee and J. E. Leiss, IEDM Tech. Dig. 28-33 (1980). G. W. Taylor, IEEE Trans. Electron Dev. 337-350 (1978). G. W. Taylor, Solid-St. Electron. 22, 701-717 (1979). K. 0. Jeppson, Elecrron. L&f. 297-298 (1975). K. E. Kroell and G. K. Ackermann, Solid-St. Electron. 19, 77-81 (1976). L. A. Akers, Electron. Left. 49-51 (1981). G. Merckel, Solid-Sr. Eiecfron. 23, 1207-1213 (1980). L. A. Akers, M. BeguwaIa and F. 2. Custode, IEEE Trans. Electron Dev. 1490-1494 (1981). P. P. Wang, IEEE Trans. Electron Dev. 779-786 (1978). L. A. Akers, Solid-St. Electron. 24, 621-627 (1981).

APPENDIX SHARING

Referring

A-CALCULATION FACTOR UNDER

to Fig. 1, the charge

OF THE CHARGE V, = 0 CONDITION

sharing

factor

is defined

as

F = area(ABC’D’) area(ABCD)

=p

L,// + E’

WI

2&f From geometrical can be written:

considerations,

the following

(r,+X,+L$+w=(q+

equation

q2.

(2A)

- ‘r - X,

(3A)

Hence, L, = [(‘I

+ w,)’ - wy2

since L’ = L,,,-

2L,

=L e/f-2([(5+

ws)‘-

w2]“2-5-Xp).

Substituting eqn (4A) into eqn (lA), factor is given as ,

F=l_

[(q+

K)‘-

(4A)

the charge

sharing

w2]1’2-5-K

(5A)

L-2X, If V,,, = 2+, is assumed, i.e. X, = X, = 0, W, = Wo = W, then the charge sharing factor becomes

E=l-;([l+~~‘2-lj.

(6A)

The above equation is identical to that of Yau’s model. If the backgate bias is large enough, the surface of the depletion region under the gate electrode becomes triangular. The depth of depletion region at the onset of this transition (i.e. L’ = 0) can be determined by

Le,,=2([(r,+ and substituting

wt=

APPENDIX SHARING

Referring given as

back

WS)‘-

W2]1’2-r/-

XS)

(7A)

L,,, = L - 2 X, yields

[( K-4)(

w,+4+2r,)]1’2.

B-CALCULATION FACTOR UNDER

OF THE CHARGE Vr, > 0 CONDITION

to Fig. 3, the charge

F=

(8A)

sharing

factor

F is

area(ABC’D’) area(ABCD) Ll

=l-

+ L3

2L,f,

P)

Threshold voltage of small-geometry Si MOSFETs From geometrical considerations, one obtains

If the depletion lar. The transition

(xs+q+L$+ w*=(r;+ w,)’ (x,+‘i+L$+

w*=(q+

wo)‘.

419

backgate bias is high enough, the surface of the region under the gate electrode becomes triangudepth of depletion region at the onset of this (i.e. L’ = 0) can be determined by

(2’3)

L,+L,=L,,,.

(W

Solving eqn (2B), L, and L, are obtained as L,=

[(!j+

lQ*-

w*]1’2-rj-xS

I,,=

[(q+

wn)‘-

w2]t’*-5-Xd

Substituting eqn (3B) into 3qn (5B) and solving for W yields

[@+

w,)‘-

wy*+ [(5+ wD)*- wq’*=L+q

(3B)

(6B) Substituting eqn (3B) into eqn (lB), the charge sharing factor is obtained as

F=l_

and

[(5+ ,>*- wq’*+[(q+ I%)*- wq’*-q-x-& 2(L-X,-X,)

w=([2(25+

w,+ wo)]‘-

[( ~+2~)*-(~+

K)‘-(r,+

W,)2]2)1’2/2(L+25).

(7B)