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A fast and low cost pulsed data A–D acquisition system
NUCLEAR I N S T R U M E N T S AND METHODS
158 ( 1 9 7 9 )
551-561
; ©
N O R T H - H O L L A N D P U B L I S H I N G CO.
A FAST AND LOW C O S T P U L S E D DATA A - D A C Q U I S I T I O N S Y S T E M M. BOCCIOLINI, G. DI CAPORIACCO and C. RJCCI lstituto di Fisk'a dell'Universita. Firenze. Italy and INFN Sezione di Firenze, Italy
Received 28 February 1978 and in revised form 19 July 1978 A system is presented for data acquisition from a set-up of detectors submitted to high counting rates in pulsed regime during a short period of the cycle. The acquisition concerns analog charge signals that produce corresponding voltage levels on capacitive memories. In the time elapsing between two successive phases, the levels exceeding a prefixed bias are digitized .and transferred to a computer. The structure we propose is modular, and allows expansion up to several hundreds of channels. The basic module includes 16 channels, each disposing of 32 capacitive memories. Of particular interest are the ease of construction and the low cost, mainly due to the use of recently introduced integrated analog memories. 1. Introduction
The plan we present was suggested by the performance required by the acquisition o f data from the vertex detector o f the F G D j) project, and it was developed on the basis of some encouraging experimental tests performed on integrated circuits of capacitive memories (SAM 64 by Reticon Corp.). In order to give an idea we shall list below some of the requirements related to the m e n t i o n e d project: 1) Possibility o f acquisition without distortion o f signals with a m i n i m u m time separation o f about 200 ns. 2) An accuracy in amplitude determination of the signals which remains within 5% of the m a x i m u m value. 3) A read-out time o f less than 40 ms. CLOCK IN 01 START tN
4) A n u m b e r of channels around 400. 5) A n u m b e r o f analog memories associated with each channel greater than 10. An advanced or simultaneous trigger signal is supposed to be available for each analog signal to be analysed. In order to complete the read-out operations in less than 40 ms, we assume that less than 50% of the detectors is interested by the same trigger. As we have mentioned above, we based our project on the use of integrated circuits of capacitive memories (SAM 64 by Reticon Corp.), each one including 64 m e m o r y cells, which are serially accessible both in reading and in writing. T h e access to these cells is controlled by two dynamic shift registers which independently regulate the addressing in reading and writing. T h e addressing in writing (reading) is performed R'' CLOC'V V - - t 7 1 J - - F - - t / - - ~ 2 V U - - y y q y T
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by MOS switches connecting the data-input (output) line with the capacity of the addressed cell. Fig. 1 schematically shows the logic structure and control modes of these components. The start-in and start-out signals clear the corresponding registers. The addressing is not cyclic, and the read-in (read-out) phase stops after completion of the writing (reading) operation on the 64th cell; no further perturbation affects the cells' contents. The minimum clock frequency (5 kHz) is sufficiently low not to create problems during the conversion and transfer phases. The switching time is 50ns and the level decrease in 40 ms is less than 1 °/G. In the test of two samples of SAM 64, we observed that the difference in the output from two different cells, on which equal signals had been memorized, was less than 1% of the maximum allowed amplitude. In fig. 2 we show the response curves obtained. As one can see, the two curves have the same trend and we verified that a small quadratic correction was sufficient to keep the integral linearity within 1%. These characteristics show that the SAM 64 (at least if the average production behaves as the two samples we had at our disposal), is more than adequate to fulfill the requirements listed above.
2. Structure of the system The tbllowing description refers to a system based on 16-channel modules. Besides the modular unit we also designed a control unit with the following functions:
1) control of the modules in the acquisition phase; 2) control of the data-transfer operation to the computer. The latter operation is more complex and includes: (a) the analog-to-digital conversion of data (8 bits); (b) the corresponding transfer of data, limited to those exceeding a presettable minimum level; (c) the transfer to the computer of the address pertinent to the datum (a second word). The registers of this unit were suitably dimensioned to-allow the control of 22 basic modules, which implies the availability of 352 channels. These dimensions correspond to the use, tbr instance, of one CAMAC crate, since it is supposed that the various units may be cabled in singlewidth modules (22) and the control unit in a double-width module. The C A M A C is referenced because it is a.suitable frame, commercially available, for logic signals exchange, power supply. Be-
PULSED DATA A - D A C Q U I S I T I O N
sides, its modular character allows one to match the system to specific requirements. When the crate is filled, corresponding to the maximum system expansion, the system interacts directly with the computer via the control unit described in the following. Nevertheless when a reduced number of channels is needed, the system may be operated in a standard CAMAC set-up by addressing the station where the control unit is located. This performance requires a proper "'patch wiring" on the crate back plane.
SYSTEM
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of the first module to be read; a pair of start-out and clock-out signals are sent to the SAM, lbllowed by an advancement signal that connects with the first odd cell which then transfers its level over the output line. The cells are cleared by means of a unique resistance for each SAM, chosen in such a way as to give a cut-off constant of - 2 ps, thus avoiding the need of reset "'switches". The SAMs' output lines are all connected by an amplifier (and an analog multiplexer) to an analog bus which takes the signals coming from the various cells. The number of signals per channel, counted by a register, equals the number of triggers. After completion of the operation on a SAM, the next SAM is selected and similarly operated. The output line of each module is sent to a buffer amplifier on the control unit, to whose inputs the levels from the cells are serially fed. From this amplifier which constitutes a part of a sampleand-hold circuit, the signals are finally fed to the AD converter (e.g. ADC 1103-001 by Analog Devices, whose conversion time is lps).
3. Description of the acquisition modules (fig. 4) Each module accepts data through 16 connectors placed on the front panel and exchanges logical signals through connections on the dataway of the CAMAC module; the logical signals may be classified into the following groups, the first two of which are concerned with the acquisition phase and the others with the readout phase (see fig. 3). 1) a trigger signal, synchronous with the current signals from the detectors; 2) two signals (start-in and clock-in), simultaneously controlling the acquisition registers of 4. Control unit all the units; The control unit, which is contained in a dou-. 3) two signals (start-out and clock-out) serially ble-width module, executes the following funccontrolling the reading registers, module by tions (see fig. 3): module; I) Acquisition control. 4) a signal which identifies the module (Mod. II) Reading control. n); I11) Sample-and-hold and A - D conversion of 5) four signals ( A D R 0 - A D R 3 ) for channel sesignals from the SAMs' cells. lection (1 of 16), used in the reading phase; IV) Coupling to the computer and module se6) an analog output signal, available on the lection. front panel, which successively coincides As to the order of memory, it should be pointed with the analog level of each cell. out that it is associated to the order number ot" the The acquisition phase begins with a start-in sig- trigger signal, and that more than one channel nal, fed in parallel to all the SAMs; if combined may be interested by a given event (but in the with a clock-in signal, it sets the read-in shift re- same order of memory). A block diagram of the cortrol unit is shown in gister to the starting position. This position is maintained until a trigger signal, by means of a fig. 3. The logic blocks labelled 1, 11, 111, 1V corresuitable monostable, brings the SAMs to the first spond resp. to figs. 5, 6, 7, 8. What follows is a brief discus sio n of its opercell for a time interval equal to the acquisition time ( ~ 150 ns). Immediately afterwards, they are ation, in the above mentioned numerical order. switched to the second cell and remain in this configuration until a new trigger is fed. Thus pro- 4.1. ACQUISITIONCONTROL(fig. 5) The group of I.C. (MI-M5, F2 and 01), execeeding, the analog levels are memorized on the odd cells. The numbers of the cells are recorded cutes the following functions: (a) at the beginning by a suitable register. The even cells will then be of the acquisition time BT becomes true; this proignored in the read-out phase. Thirty-two analog duces two suitably temporized clock-in and startin signals, which set the acquisition registers of all buffers are thus associated to a given channel. The "read-out" phase starts from the first SAM the SAMs to the starting position; (b) every time
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a trigger signal arrives, unless a switching cycle is being performed (El), two suitably delayed clockin signals are produced: the first switches all the SAMs to an odd (acquisition)cell; after N 150 ns, the second again switches them to an even (standby) cell. The reason why only alternating cells have been used, is that the even cells behave differently to the odd ones if the symmetry of the phase .signals piloting the registers is not perfect. Since an adjustment would have been critical and should have been done separately on each module, and since, on the other hand, the number of orders of memory was more than enough, we simply preferred to use only half of the available memory. F7 serves to indicate whether or not at least a trigger signal has been produced during a measurement interval, which constitutes a condition to perform any reading. In the same figure, register A serves to store the number of triggers that have occurred during the measurement interval (BT). This information is then used in the reading phase, during which a number of readings equal to the content of A will be executed on each channel, using the register B as a counter and the comparator FBC. 4.2. CONTROL OF THE SCANNING PROCEDURE OF THE S A M s IN THE READING PHASE (fig. 6)
When the measurement time has elapsed (BT becomes false), if the computer is ready (ENCODE true) and at least one trigger signal has arrived (DATA true), a reading procedure (controlled by E2) begins; this procedure terminates only after the last involved cell of the last channel has been read, ~,'hat causes OVERFLOW to become true. Reaoing is accomplished as follows: two combined signals (START-OUT, CLOCK-OUT) set on the first cell the reading register of the channel corresponding to the content of register ADR (ADR0-ADRS). These signals are induced by the activation of the "channel" constituted by circuits E2, E4, M7, M8, 03, F4. At the end of this operation the "channel" E3, E5, M9, M10, O3, F4 is opened, and produces a couple of clock-out signals and the sampling and conversion signals, correlated to the first one by M12 and MI3. The SAM's reading register is kept to select the even cells for N5 ~s, in order to allow the signal output line to unload (MI0). An advancement signal (RC) for the B register is then supplied by the
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above mentioned logic line. Once this has been done, a new enabling signal ENCODE is fed via E2 and the operation starts again; the cycle is repeated until a number of readings equal to the content of register A has been performed. When this happens, signal EQB comes true (fig. 5), which produces a channel-advancement signal on ADR. Moreover, the operation in course is terminated by causing the SAM's reading register to overflow during the last unloading time, and this is accomplished by means of the piloted oscillator constituted by the coupling E 6 - M l l . We should like to recall that in the overflow condition only the stray capacitance remains connected to the output line. The change of sign of EQB, when a new operation is induced by E2, will again activate via E4 the chain M7, M8, 03, F4, which will initialize a new channel. 4.3. DIGITIZATIONCIRCUITS (fig. 7) The control unit includes a single 8-bit, fastconversion-time ADC. An analog bus is fed from the controlled units to the input. The analog signals, successively arriving from the various units, have a cut-off constant of 2/~s, so that a sampleand-hold operation is needed; this operation is controlled by the SAMP signal supplied by the logic circuits described in the preceding section. The same circuits provide the conversion commands. After a maximum l ~ s delay, an output signal from the converter (ADC Ready) indicates that a conversion has occurred and that the result is available at the logic outputs (ADC0-ADC7). Finally, a built-in comparator (FBC) indicates whether or not the converted signal exceeds a hand-presettable minimum (ADC>PRESET). 4.4. ADDRESSING OF THE UNITS AND COUPLING TO THE COMPUTER (fig. 8)
As seen in sect. 4.2, the ADR register, together with the B register, gives the address of the converted cell. In particular, the first four bits of ADR are used to count the channel order number (1-16) within the modules. The next five bits, after a decoding operation, give the module number. The logic of coupling to the computer, based on the two levels FLAG and ENCODE, is reported high in fig. 8 (circuits M15, 04, F5, M14, F6, 05). This logic performs the consecutive transfer of
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two 16-bit words, selected by the status of F6 (signal S). The selection signal acts on the selectors drawn in the lower part of fig. 8 and the word's content is alternatively: (a) the address of the cell, which includes both the channel identification (ADR register) and the order of memory (B register); (b) the digitized cell content. 5. S o m e general remarks 1) The time resolution in acquisition is only limited by the SAMs' switching times (50 ns), so that even in the use with the fast nuclear detectors the first distortions due to the counting rate are those, unavoidably, which derive from pile-up on the detectors themselves. 2) The difference in classification of equal signals, to be ascribed to differences among various cells, is less than 1% of the maxim u m amplitude; it is however due mostly tothe presence of residual levels of this order of magnitude and seems therefore the most
serious restriction in the use of the SAMs when high relative precisions are required for signals of small amplitude too. 3) The system modularity may suggest the absence of a limit to the possibility of expansion of the number of channels. One has, however, to take into account that the decrease in the memorized level of a cell is 1 °/6 in 5 0 m s ; since the reading time is - 5 ~ s per cell (we assume that the computer is equipped with a DMA), one may consider an overall number of 5 0 × 1 0 - 3 / 5 × 10 -6 = 104 cells as the largest acceptable. Since the number of cells per channel is 32, in order to keep the distortions due to level decrease to less than 1%, one must not exceed a number of 300 channels, which is approxi: mately that adopted in our model. Obviously if less than 32 cells are needed, the number of channels can be proportionally increased. 4) It is to be pointed out that the number of readifig cycles executed in every measurement always equals the product of the number of channels times the number of order of memory involved, but that only the "signi-
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ficantly" non-zero data are transferred to the computer. 5) Should a measurement hypothetically fill all the cells, considering the dimensions of our system, 352 x 32 x 4 = 45 056 bytes would be transferred to the computer. In general, however, one should expect a drastically smaller number, due both to the fact that the number of triggers associated with the measurement (and therefore the largest order of memory involved) will be less than 32, and to the fact that there will be a great percentage of " e m p t y " cells. 6) The realisation of a system such as the one
ACQUISITION
SYSTEM
561
we have described is clearly much simpler and less expensive than any other involving the use of discrete components, even if the number of memory levels available per channel could be considerably reduced. It is our opinion that the only possible reserve to keep in mind is connected with the limitations we mentioned in item (2). It is however apparent in this respect that an improvement in the hardware or in the software would lead to a better performance of the system. Reference I) A. Bettini et al., CERN/SPSC/75-24, p. 45.
158 ( 1 9 7 9 )
551-561
; ©
N O R T H - H O L L A N D P U B L I S H I N G CO.
A FAST AND LOW C O S T P U L S E D DATA A - D A C Q U I S I T I O N S Y S T E M M. BOCCIOLINI, G. DI CAPORIACCO and C. RJCCI lstituto di Fisk'a dell'Universita. Firenze. Italy and INFN Sezione di Firenze, Italy
Received 28 February 1978 and in revised form 19 July 1978 A system is presented for data acquisition from a set-up of detectors submitted to high counting rates in pulsed regime during a short period of the cycle. The acquisition concerns analog charge signals that produce corresponding voltage levels on capacitive memories. In the time elapsing between two successive phases, the levels exceeding a prefixed bias are digitized .and transferred to a computer. The structure we propose is modular, and allows expansion up to several hundreds of channels. The basic module includes 16 channels, each disposing of 32 capacitive memories. Of particular interest are the ease of construction and the low cost, mainly due to the use of recently introduced integrated analog memories. 1. Introduction
The plan we present was suggested by the performance required by the acquisition o f data from the vertex detector o f the F G D j) project, and it was developed on the basis of some encouraging experimental tests performed on integrated circuits of capacitive memories (SAM 64 by Reticon Corp.). In order to give an idea we shall list below some of the requirements related to the m e n t i o n e d project: 1) Possibility o f acquisition without distortion o f signals with a m i n i m u m time separation o f about 200 ns. 2) An accuracy in amplitude determination of the signals which remains within 5% of the m a x i m u m value. 3) A read-out time o f less than 40 ms. CLOCK IN 01 START tN
4) A n u m b e r of channels around 400. 5) A n u m b e r o f analog memories associated with each channel greater than 10. An advanced or simultaneous trigger signal is supposed to be available for each analog signal to be analysed. In order to complete the read-out operations in less than 40 ms, we assume that less than 50% of the detectors is interested by the same trigger. As we have mentioned above, we based our project on the use of integrated circuits of capacitive memories (SAM 64 by Reticon Corp.), each one including 64 m e m o r y cells, which are serially accessible both in reading and in writing. T h e access to these cells is controlled by two dynamic shift registers which independently regulate the addressing in reading and writing. T h e addressing in writing (reading) is performed R'' CLOC'V V - - t 7 1 J - - F - - t / - - ~ 2 V U - - y y q y T
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by MOS switches connecting the data-input (output) line with the capacity of the addressed cell. Fig. 1 schematically shows the logic structure and control modes of these components. The start-in and start-out signals clear the corresponding registers. The addressing is not cyclic, and the read-in (read-out) phase stops after completion of the writing (reading) operation on the 64th cell; no further perturbation affects the cells' contents. The minimum clock frequency (5 kHz) is sufficiently low not to create problems during the conversion and transfer phases. The switching time is 50ns and the level decrease in 40 ms is less than 1 °/G. In the test of two samples of SAM 64, we observed that the difference in the output from two different cells, on which equal signals had been memorized, was less than 1% of the maximum allowed amplitude. In fig. 2 we show the response curves obtained. As one can see, the two curves have the same trend and we verified that a small quadratic correction was sufficient to keep the integral linearity within 1%. These characteristics show that the SAM 64 (at least if the average production behaves as the two samples we had at our disposal), is more than adequate to fulfill the requirements listed above.
2. Structure of the system The tbllowing description refers to a system based on 16-channel modules. Besides the modular unit we also designed a control unit with the following functions:
1) control of the modules in the acquisition phase; 2) control of the data-transfer operation to the computer. The latter operation is more complex and includes: (a) the analog-to-digital conversion of data (8 bits); (b) the corresponding transfer of data, limited to those exceeding a presettable minimum level; (c) the transfer to the computer of the address pertinent to the datum (a second word). The registers of this unit were suitably dimensioned to-allow the control of 22 basic modules, which implies the availability of 352 channels. These dimensions correspond to the use, tbr instance, of one CAMAC crate, since it is supposed that the various units may be cabled in singlewidth modules (22) and the control unit in a double-width module. The C A M A C is referenced because it is a.suitable frame, commercially available, for logic signals exchange, power supply. Be-
PULSED DATA A - D A C Q U I S I T I O N
sides, its modular character allows one to match the system to specific requirements. When the crate is filled, corresponding to the maximum system expansion, the system interacts directly with the computer via the control unit described in the following. Nevertheless when a reduced number of channels is needed, the system may be operated in a standard CAMAC set-up by addressing the station where the control unit is located. This performance requires a proper "'patch wiring" on the crate back plane.
SYSTEM
553
of the first module to be read; a pair of start-out and clock-out signals are sent to the SAM, lbllowed by an advancement signal that connects with the first odd cell which then transfers its level over the output line. The cells are cleared by means of a unique resistance for each SAM, chosen in such a way as to give a cut-off constant of - 2 ps, thus avoiding the need of reset "'switches". The SAMs' output lines are all connected by an amplifier (and an analog multiplexer) to an analog bus which takes the signals coming from the various cells. The number of signals per channel, counted by a register, equals the number of triggers. After completion of the operation on a SAM, the next SAM is selected and similarly operated. The output line of each module is sent to a buffer amplifier on the control unit, to whose inputs the levels from the cells are serially fed. From this amplifier which constitutes a part of a sampleand-hold circuit, the signals are finally fed to the AD converter (e.g. ADC 1103-001 by Analog Devices, whose conversion time is lps).
3. Description of the acquisition modules (fig. 4) Each module accepts data through 16 connectors placed on the front panel and exchanges logical signals through connections on the dataway of the CAMAC module; the logical signals may be classified into the following groups, the first two of which are concerned with the acquisition phase and the others with the readout phase (see fig. 3). 1) a trigger signal, synchronous with the current signals from the detectors; 2) two signals (start-in and clock-in), simultaneously controlling the acquisition registers of 4. Control unit all the units; The control unit, which is contained in a dou-. 3) two signals (start-out and clock-out) serially ble-width module, executes the following funccontrolling the reading registers, module by tions (see fig. 3): module; I) Acquisition control. 4) a signal which identifies the module (Mod. II) Reading control. n); I11) Sample-and-hold and A - D conversion of 5) four signals ( A D R 0 - A D R 3 ) for channel sesignals from the SAMs' cells. lection (1 of 16), used in the reading phase; IV) Coupling to the computer and module se6) an analog output signal, available on the lection. front panel, which successively coincides As to the order of memory, it should be pointed with the analog level of each cell. out that it is associated to the order number ot" the The acquisition phase begins with a start-in sig- trigger signal, and that more than one channel nal, fed in parallel to all the SAMs; if combined may be interested by a given event (but in the with a clock-in signal, it sets the read-in shift re- same order of memory). A block diagram of the cortrol unit is shown in gister to the starting position. This position is maintained until a trigger signal, by means of a fig. 3. The logic blocks labelled 1, 11, 111, 1V corresuitable monostable, brings the SAMs to the first spond resp. to figs. 5, 6, 7, 8. What follows is a brief discus sio n of its opercell for a time interval equal to the acquisition time ( ~ 150 ns). Immediately afterwards, they are ation, in the above mentioned numerical order. switched to the second cell and remain in this configuration until a new trigger is fed. Thus pro- 4.1. ACQUISITIONCONTROL(fig. 5) The group of I.C. (MI-M5, F2 and 01), execeeding, the analog levels are memorized on the odd cells. The numbers of the cells are recorded cutes the following functions: (a) at the beginning by a suitable register. The even cells will then be of the acquisition time BT becomes true; this proignored in the read-out phase. Thirty-two analog duces two suitably temporized clock-in and startin signals, which set the acquisition registers of all buffers are thus associated to a given channel. The "read-out" phase starts from the first SAM the SAMs to the starting position; (b) every time
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a trigger signal arrives, unless a switching cycle is being performed (El), two suitably delayed clockin signals are produced: the first switches all the SAMs to an odd (acquisition)cell; after N 150 ns, the second again switches them to an even (standby) cell. The reason why only alternating cells have been used, is that the even cells behave differently to the odd ones if the symmetry of the phase .signals piloting the registers is not perfect. Since an adjustment would have been critical and should have been done separately on each module, and since, on the other hand, the number of orders of memory was more than enough, we simply preferred to use only half of the available memory. F7 serves to indicate whether or not at least a trigger signal has been produced during a measurement interval, which constitutes a condition to perform any reading. In the same figure, register A serves to store the number of triggers that have occurred during the measurement interval (BT). This information is then used in the reading phase, during which a number of readings equal to the content of A will be executed on each channel, using the register B as a counter and the comparator FBC. 4.2. CONTROL OF THE SCANNING PROCEDURE OF THE S A M s IN THE READING PHASE (fig. 6)
When the measurement time has elapsed (BT becomes false), if the computer is ready (ENCODE true) and at least one trigger signal has arrived (DATA true), a reading procedure (controlled by E2) begins; this procedure terminates only after the last involved cell of the last channel has been read, ~,'hat causes OVERFLOW to become true. Reaoing is accomplished as follows: two combined signals (START-OUT, CLOCK-OUT) set on the first cell the reading register of the channel corresponding to the content of register ADR (ADR0-ADRS). These signals are induced by the activation of the "channel" constituted by circuits E2, E4, M7, M8, 03, F4. At the end of this operation the "channel" E3, E5, M9, M10, O3, F4 is opened, and produces a couple of clock-out signals and the sampling and conversion signals, correlated to the first one by M12 and MI3. The SAM's reading register is kept to select the even cells for N5 ~s, in order to allow the signal output line to unload (MI0). An advancement signal (RC) for the B register is then supplied by the
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above mentioned logic line. Once this has been done, a new enabling signal ENCODE is fed via E2 and the operation starts again; the cycle is repeated until a number of readings equal to the content of register A has been performed. When this happens, signal EQB comes true (fig. 5), which produces a channel-advancement signal on ADR. Moreover, the operation in course is terminated by causing the SAM's reading register to overflow during the last unloading time, and this is accomplished by means of the piloted oscillator constituted by the coupling E 6 - M l l . We should like to recall that in the overflow condition only the stray capacitance remains connected to the output line. The change of sign of EQB, when a new operation is induced by E2, will again activate via E4 the chain M7, M8, 03, F4, which will initialize a new channel. 4.3. DIGITIZATIONCIRCUITS (fig. 7) The control unit includes a single 8-bit, fastconversion-time ADC. An analog bus is fed from the controlled units to the input. The analog signals, successively arriving from the various units, have a cut-off constant of 2/~s, so that a sampleand-hold operation is needed; this operation is controlled by the SAMP signal supplied by the logic circuits described in the preceding section. The same circuits provide the conversion commands. After a maximum l ~ s delay, an output signal from the converter (ADC Ready) indicates that a conversion has occurred and that the result is available at the logic outputs (ADC0-ADC7). Finally, a built-in comparator (FBC) indicates whether or not the converted signal exceeds a hand-presettable minimum (ADC>PRESET). 4.4. ADDRESSING OF THE UNITS AND COUPLING TO THE COMPUTER (fig. 8)
As seen in sect. 4.2, the ADR register, together with the B register, gives the address of the converted cell. In particular, the first four bits of ADR are used to count the channel order number (1-16) within the modules. The next five bits, after a decoding operation, give the module number. The logic of coupling to the computer, based on the two levels FLAG and ENCODE, is reported high in fig. 8 (circuits M15, 04, F5, M14, F6, 05). This logic performs the consecutive transfer of
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two 16-bit words, selected by the status of F6 (signal S). The selection signal acts on the selectors drawn in the lower part of fig. 8 and the word's content is alternatively: (a) the address of the cell, which includes both the channel identification (ADR register) and the order of memory (B register); (b) the digitized cell content. 5. S o m e general remarks 1) The time resolution in acquisition is only limited by the SAMs' switching times (50 ns), so that even in the use with the fast nuclear detectors the first distortions due to the counting rate are those, unavoidably, which derive from pile-up on the detectors themselves. 2) The difference in classification of equal signals, to be ascribed to differences among various cells, is less than 1% of the maxim u m amplitude; it is however due mostly tothe presence of residual levels of this order of magnitude and seems therefore the most
serious restriction in the use of the SAMs when high relative precisions are required for signals of small amplitude too. 3) The system modularity may suggest the absence of a limit to the possibility of expansion of the number of channels. One has, however, to take into account that the decrease in the memorized level of a cell is 1 °/6 in 5 0 m s ; since the reading time is - 5 ~ s per cell (we assume that the computer is equipped with a DMA), one may consider an overall number of 5 0 × 1 0 - 3 / 5 × 10 -6 = 104 cells as the largest acceptable. Since the number of cells per channel is 32, in order to keep the distortions due to level decrease to less than 1%, one must not exceed a number of 300 channels, which is approxi: mately that adopted in our model. Obviously if less than 32 cells are needed, the number of channels can be proportionally increased. 4) It is to be pointed out that the number of readifig cycles executed in every measurement always equals the product of the number of channels times the number of order of memory involved, but that only the "signi-
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we have described is clearly much simpler and less expensive than any other involving the use of discrete components, even if the number of memory levels available per channel could be considerably reduced. It is our opinion that the only possible reserve to keep in mind is connected with the limitations we mentioned in item (2). It is however apparent in this respect that an improvement in the hardware or in the software would lead to a better performance of the system. Reference I) A. Bettini et al., CERN/SPSC/75-24, p. 45.