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Digital System for Low Cost Fast Data Acquisition And Processing
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DIGITAL SYSTEM FOR LOW COST FAST DATA ACQUISITION AND PROCESSING P. Garcia de Madinabeitia and J. M. Perez Toca Centro de Estudi os e Investigaciones Tecnicas de Guiptizcoa, Sa n Sebastian, Spain
Abstract. A low cost system for analog signal acquisition and processing is presented. The 8-bit microprocessor based system uses a video monitor to display the processed si2 nals. This paper describes the architecture and the performance of this system, in special its behaviour on the treatment of non- repetitive signa l s. It uses Direct Access Memory techniques to transfer the digitised signals to the memory . By employing a circular storage strategy, the data is saved continuously. The t r igger point and the amount of stored pre-trigger data to be displayed are user se l ected . The system possesses also several g r aphic and printing facilities to examine in detail the waveforms stored . It can also be connected to external equ ipment that can take the cont r ol of the apparatus . Keywords. Data acquisition , Data handl ing , Data processing , signal processing , Transient analysis , Microprocessors.
INTRODUCTION
A/ D Conversion Subsystem
Very often Physical research involves phenomena cha racterised by analog electrica l non- repetitive sig~ nals i . e . Geophysics, Material Testing, Ballistics , Non-destructive Testing, Impact Measurement, etc.
The conversion suhsyster schematics are shown in Figure 2. The amplifier has the purpose to adapt the input impedance to the next element and adequate the range of the input signal to the A/D converter range. The amplifier is l inea r i n s i de the A/D converter working range , and con fines t h e analog signa l inside t h e allowed limits protec t i n g the A/D converter from damages and optimising its reso lution by wo r king in the highest span va l ues .
On e method to capture single- shot sig n als is by using memory oscilloscopes. If the scope is not di gital , the i nformation about the phenomen a , prior that it occurs is not feasible, but using r etard lines. Employing digital scopes it is possible to have the observation of the wave prior to the trigger point. There exist also transient recorders with ch~ racteristics of sampling speed and storage facili ties such as digital oscilloscopes, with analog OU! puts to analog oscilloscopes or pe n recorders or di gital outputs to computers, calcu l ator s, etc.
The low- pass filter takes care of the high frequen cy components of the signal input that can give misleading results. This occurs mainly wh en the waveform input frequency is greater than a ha l f of the sampling frequency . This filter is also used to cance l induced n o i ses on the input sign al.
The equipment discussed in this paper presents a low cost alternative to the equipment previously menti~ ned . By emp l oying a low-cost video moni t or as peripheral device, it provides many of the features avai lable in the digital oscilloscopes and recorders.
The A/D conve r ter selection is a determi n i ng f acto r for the cost a n d basic performance o f th e system. I t determines the filte r characte r istics o n establishing the wavefo r m f r equen cy, the h ighest to be sampled . It also determines the accuracy of the in formation of the sampled signals. The AID conve r~ ter chosen has been and 8 - bit one with 2 , 5 Mffimp l es/ sec samp l ing speed and TTL compatible TRW TDC lOOlJ .
For the sake of cheapness, the system bandwidth is limited to 2 Msamples/ sec , being therefore easy to built it using low cost components.
Acquisition and signal t r eatment subsyste m SYSTEM STRUCTURE
This subsystem collects the data coming from t h e conversion subsystem and saves them in the memory in an order l y way. This subsystem a l so coo r dinates and controls the system globa l ope r ation. Its structure is digital , built around the f o ll ow ing main un i ts:
The system can be splited in three parts . The description of the power supply section has not been considered. - A/D Conversion subsystem. - Acquisition and signal t reatment subsystem - Display subsystem
- Z80A CPU - Z80A DMA - RAM memory for data storage and c a lculation. - EPROM that co n tains the system p r ogram. - Se r ial I / O port.
The system schematics are presented in Figure I.
39
-10
P. Garcia de Madinabeitia, J . M. Perez Toca
The RAM memory module is 17 Kbytes long. 16 Kbytes are assigned to save data acquired and 1 Kbyte is utilised to store the system parameters and as a safeguard area. This area is used at the conclusion of data conversion-acquisition to rearrange it. The
RAM memory module is expandable to 55 Kbytes, either s~
to analyse longer waveforms incoming or to store
veral different signals for comparison purposes. A 16 Kbytes segment allows the storage of data collec ted during more than 8 milliseconds. The program is contained in an 8 Kbytes long area. At present only 3 Kbytes are used. The program cooE dinates and controls the operations of conversion
and display subsystems and sets the DMA device parameters to reach the maximum throughput of the con verter.
Display subsystem The display subsystem is built around the NEC's UPD 7220 Graphics Display Controller (GDC) chip. It consists of 128 Kbytes of graphics memory . This memory amount allows the management of 262144x4 pixels (640x400 displays and 4 bit planes of color or gray scale). The GDC generates the basic video raster timing including the SYNC and BLANKING signals. Depending on the video monitor used it may be necessary to change the crystal quartz of this subsystem. The System has output signa l s RGB type with separate vertical and horizontal SYNC outputs and a sepa rate composite block SYNC output. All video parameters are program controlled and in the case of using a monochrome monitor , the user can manage
One of the main problems associated with this subsystem is the synchronization between the A/D conveE ter and the DMA device. Provided that the maximum transfer speed of the DMA is 2 Mbytes/sec and the converter goes at up to 2 , 5 Mconv/sec , it is necess~ ry to synchronize both subsystems. This problem has been solved, forcing the relative situation between both subsystems in the critical moments,
to 16 gray levels on the green output by programming accordingly the Write Colour Look-up Table of the GDC. The graphics subsystem takes 8 I /O locations in the Z80 I/O space.
such as,
the start of conversion or the data transfer, to be the same for each conversion cycle performed. The converter needs a minimum number of 9 clock
pu~
ses for each conversion. Since the restricting fre-
quency is given by the DMA device, it is reasonable to fix this frequency and then find a multiple of it to clock the converter. A 20 MHz quartz crystal results adequate for the converter and by means of a divide-by- five circuit issues a synchronous clock for the microprocessor system.
Thus, when the DMA in his first working cycle sends to the converter a signal, each time that begins a cyc le, the converter response will be the same due to synchronization. This status will remain, until
the DMA concludes the operation and returns the con trol to the CPU that can then continue with other tasks. Depending on the DMA programming, the data transfer speed varies remarkably. To achieve the maximum speed for the write operation in memory for data incoming from the converter, the DMA deviceis pro-
grammed in search mode. The RD signal of this circuit is used like write signal, so that though the~ rycally it reads data from memory, really it writes into it. Also it has been chosen the 'search nothing' option to non stop the process in the presence of a particular data. On the other hand, when the DMA performs the search, RD anj BUSACK are simultaneously active and the data coming from the A/ D converter is directly written in the memory.
Once finishing the data acquisition, the DMA releases the system bus control back to the CPU and the write and read signals become as the original. In this way it has been possible to reach the transfer of 2 millions data / sec. from the conversion subsystem to the memory. Inside the acquisition and signal treatment subsystem the user can access to the system using conven-
tional peripherals either to manage it (keyboards , terminals) or the output data to external equipment (i .e. printers, microcomputers). These facilities
SYSTEM OPERATION AND PERFORMANCE When the CPU receives the acquiring request, before to pass the control to the DMA, it analyses the ON/OFF settings of a 4 switch set.This set controls the pretrigger amount of data. The DMA takes control of the buses and generates the start of conversion signal and repeats the operation until it fills the storage memory with new data. In t hi s manner it ensures the observation of the analog s ignal prior to the trigger point. In accordance with the pretrigger setting, that establishes the acquisition cycles number, when the trigger occurs and the number of cycles stored coincides with the number of cycles set , the acquisition is interrupted. The DMA stops and releases the buses. The acquisition is made in a cyclic manner: the storage starts at the begining of the memory area until it reaches the upper bound and then it links back with the begining address. Once the DMA is disabled, the CPU reads from the DMA the last address loaded during the acqu i sition time . Then ,
it rearranges the data in memory to ma
ke clearer its graphic representation. This rearrangement allocates the last data acquired at the last address position of the storage area, allocating the least recent at the first address . Then, the system disp lays the data acquired o n the screen. The operation can be summed up in this way: it draws a reticle and then it draws 500 data from the acquisiting memory. The reticle consists on 10 vertical lines and 16 horizontal l~ nes equally spaced. Between two consecutive vert~ cal lines there are 50 points drawed. In horizonta~ between two consecutive horizontal lines there are
16 values . There are two basic modes of data representation: the normal mode and the expanded mode. In the normal mode , the waveform drawing consists of 500 dots. Each dot represents the value of a sampled data. The system enters in this mode automatically next to the triggering operation. The user can look over all the acquisition memory in 50 sample steps. Each step represents 25 microseconds acquisition time.
are accomplished by means of RS-232C and 20 mA current loop interfaces.
The expanded mode permits the displayed wavefo r m to be analysed in detail. The disp lay shows 50 sam
Fast Data Acquisition pies. Thus it has a horizontal expansion x 10 time& Two consecutive dots corresponding to two consecuti ve samples are joined by a solid line. In both cases, the program takes account of the acquisition memory bounds to restrict the d rawing on ly to the stored data.
APPLICATION RESULTS The system was tested in three specific cases: - Periodic signals - Transient signals started by a triggering signal. - Microfuses tests. The first case merely served as an example of basic system operation. Figure 3 s hows a 75 KHz sinusoid al signal sampled and displayed in the expanded mo de. The transient analysis of signals under trigger con trol showed the good performance characteristics of the system. Thi s analysis was made using a function generator with its output enabled by a trigger. Figure 4 shows a transient captured.
41 CONCLUSIONS
Although nowadays there are many systems that are capable to capture and display single-shot analog signals they have in many cases the inconvenience o f being too expensive. This problem has been tack led with the system described in this paper. The system presents good performance characteristics. Compared to the conventiona l o n es has the advantage of being low-priced. I t can be easily built an d cou l d be useful in many applications where the sam pling rate has not the need to be too fast « 2 Msamples/second) . Further development is now intended to increase the system capabilities on the treatment of the signals captured, i.e. better graphics display , filtering algorithms, etc. that could be implemented without incurring substantial equipment expenditure. REFERENCES Yuen, C.K. , Beauchamp, K.G. and Robinson, G.P.S. (1982), Microprocessor Systems and Their Application to Signal Processing, Academic Press, London, 1982. Z80 DMA Technical Man ual , Zilog, Inc. Graphics Display Controller UPD7220. Product Description. NEC Electronics (Europe) GmbH.
Figure 5 shows the circuit used for microfuse tests The test circuit issues to the acquisition system the analogue tension corresponding to overcurrent that circulates through the fuse. The overcurrent corresponds to a current pulse that sets the fuse under extreme conditions. The user issues the current pulse and the trigger simultaneously. Figures 6 and 7 shows some typical transients reco rded . The graphics obtained during the test- correspond to the variation of fuse resistance under the current passing through it.
. -_ _ _ _L -_ _ _- , _ _ _ _
,
I
I
I
GDC
A I D CONVERTER
I
I I I
Fig .l System structure
42
P. Garcia de Madinabeitia. 1. M. Perez Toca
------------------------------------------" ~------------------------------------- r
l " A
$ 'A1 DG NO
22t
11 .\
D ,
)
T R W el f(.
se
TDC 100 1J
v,"
EL
U'
f-------------.---.
1
E5 ICl 8 0 eg
6Kn 1\
J
'4Kn 1\
Dig ita l Gr ound
~ Ana log Grou nd
- Sv
1',10"' F ig_ 2 A! D Conve r s i o n subsystem
Fig. 3
~5 KHz si~usoidal signa l. Expanded mode
Fig . 4 Transients . An
e x a~p l e
.. Tr igg er
Milc rof~l .VN ~OO1T N
Tes t Sig n al 0-5v
F i g.
Circuit
~or
~~cro ~ ~se
tes t s .
::::,~
43
Fast Data Acquisition
100
75
50
25
50
100
150
200
250
200
250
Fig. 6 Microfuse behaviour. Case 1
100
75
50
25
50
100
150
Fig. 7 Microfuse behaviour. Case 2.
DIGITAL SYSTEM FOR LOW COST FAST DATA ACQUISITION AND PROCESSING P. Garcia de Madinabeitia and J. M. Perez Toca Centro de Estudi os e Investigaciones Tecnicas de Guiptizcoa, Sa n Sebastian, Spain
Abstract. A low cost system for analog signal acquisition and processing is presented. The 8-bit microprocessor based system uses a video monitor to display the processed si2 nals. This paper describes the architecture and the performance of this system, in special its behaviour on the treatment of non- repetitive signa l s. It uses Direct Access Memory techniques to transfer the digitised signals to the memory . By employing a circular storage strategy, the data is saved continuously. The t r igger point and the amount of stored pre-trigger data to be displayed are user se l ected . The system possesses also several g r aphic and printing facilities to examine in detail the waveforms stored . It can also be connected to external equ ipment that can take the cont r ol of the apparatus . Keywords. Data acquisition , Data handl ing , Data processing , signal processing , Transient analysis , Microprocessors.
INTRODUCTION
A/ D Conversion Subsystem
Very often Physical research involves phenomena cha racterised by analog electrica l non- repetitive sig~ nals i . e . Geophysics, Material Testing, Ballistics , Non-destructive Testing, Impact Measurement, etc.
The conversion suhsyster schematics are shown in Figure 2. The amplifier has the purpose to adapt the input impedance to the next element and adequate the range of the input signal to the A/D converter range. The amplifier is l inea r i n s i de the A/D converter working range , and con fines t h e analog signa l inside t h e allowed limits protec t i n g the A/D converter from damages and optimising its reso lution by wo r king in the highest span va l ues .
On e method to capture single- shot sig n als is by using memory oscilloscopes. If the scope is not di gital , the i nformation about the phenomen a , prior that it occurs is not feasible, but using r etard lines. Employing digital scopes it is possible to have the observation of the wave prior to the trigger point. There exist also transient recorders with ch~ racteristics of sampling speed and storage facili ties such as digital oscilloscopes, with analog OU! puts to analog oscilloscopes or pe n recorders or di gital outputs to computers, calcu l ator s, etc.
The low- pass filter takes care of the high frequen cy components of the signal input that can give misleading results. This occurs mainly wh en the waveform input frequency is greater than a ha l f of the sampling frequency . This filter is also used to cance l induced n o i ses on the input sign al.
The equipment discussed in this paper presents a low cost alternative to the equipment previously menti~ ned . By emp l oying a low-cost video moni t or as peripheral device, it provides many of the features avai lable in the digital oscilloscopes and recorders.
The A/D conve r ter selection is a determi n i ng f acto r for the cost a n d basic performance o f th e system. I t determines the filte r characte r istics o n establishing the wavefo r m f r equen cy, the h ighest to be sampled . It also determines the accuracy of the in formation of the sampled signals. The AID conve r~ ter chosen has been and 8 - bit one with 2 , 5 Mffimp l es/ sec samp l ing speed and TTL compatible TRW TDC lOOlJ .
For the sake of cheapness, the system bandwidth is limited to 2 Msamples/ sec , being therefore easy to built it using low cost components.
Acquisition and signal t r eatment subsyste m SYSTEM STRUCTURE
This subsystem collects the data coming from t h e conversion subsystem and saves them in the memory in an order l y way. This subsystem a l so coo r dinates and controls the system globa l ope r ation. Its structure is digital , built around the f o ll ow ing main un i ts:
The system can be splited in three parts . The description of the power supply section has not been considered. - A/D Conversion subsystem. - Acquisition and signal t reatment subsystem - Display subsystem
- Z80A CPU - Z80A DMA - RAM memory for data storage and c a lculation. - EPROM that co n tains the system p r ogram. - Se r ial I / O port.
The system schematics are presented in Figure I.
39
-10
P. Garcia de Madinabeitia, J . M. Perez Toca
The RAM memory module is 17 Kbytes long. 16 Kbytes are assigned to save data acquired and 1 Kbyte is utilised to store the system parameters and as a safeguard area. This area is used at the conclusion of data conversion-acquisition to rearrange it. The
RAM memory module is expandable to 55 Kbytes, either s~
to analyse longer waveforms incoming or to store
veral different signals for comparison purposes. A 16 Kbytes segment allows the storage of data collec ted during more than 8 milliseconds. The program is contained in an 8 Kbytes long area. At present only 3 Kbytes are used. The program cooE dinates and controls the operations of conversion
and display subsystems and sets the DMA device parameters to reach the maximum throughput of the con verter.
Display subsystem The display subsystem is built around the NEC's UPD 7220 Graphics Display Controller (GDC) chip. It consists of 128 Kbytes of graphics memory . This memory amount allows the management of 262144x4 pixels (640x400 displays and 4 bit planes of color or gray scale). The GDC generates the basic video raster timing including the SYNC and BLANKING signals. Depending on the video monitor used it may be necessary to change the crystal quartz of this subsystem. The System has output signa l s RGB type with separate vertical and horizontal SYNC outputs and a sepa rate composite block SYNC output. All video parameters are program controlled and in the case of using a monochrome monitor , the user can manage
One of the main problems associated with this subsystem is the synchronization between the A/D conveE ter and the DMA device. Provided that the maximum transfer speed of the DMA is 2 Mbytes/sec and the converter goes at up to 2 , 5 Mconv/sec , it is necess~ ry to synchronize both subsystems. This problem has been solved, forcing the relative situation between both subsystems in the critical moments,
to 16 gray levels on the green output by programming accordingly the Write Colour Look-up Table of the GDC. The graphics subsystem takes 8 I /O locations in the Z80 I/O space.
such as,
the start of conversion or the data transfer, to be the same for each conversion cycle performed. The converter needs a minimum number of 9 clock
pu~
ses for each conversion. Since the restricting fre-
quency is given by the DMA device, it is reasonable to fix this frequency and then find a multiple of it to clock the converter. A 20 MHz quartz crystal results adequate for the converter and by means of a divide-by- five circuit issues a synchronous clock for the microprocessor system.
Thus, when the DMA in his first working cycle sends to the converter a signal, each time that begins a cyc le, the converter response will be the same due to synchronization. This status will remain, until
the DMA concludes the operation and returns the con trol to the CPU that can then continue with other tasks. Depending on the DMA programming, the data transfer speed varies remarkably. To achieve the maximum speed for the write operation in memory for data incoming from the converter, the DMA deviceis pro-
grammed in search mode. The RD signal of this circuit is used like write signal, so that though the~ rycally it reads data from memory, really it writes into it. Also it has been chosen the 'search nothing' option to non stop the process in the presence of a particular data. On the other hand, when the DMA performs the search, RD anj BUSACK are simultaneously active and the data coming from the A/ D converter is directly written in the memory.
Once finishing the data acquisition, the DMA releases the system bus control back to the CPU and the write and read signals become as the original. In this way it has been possible to reach the transfer of 2 millions data / sec. from the conversion subsystem to the memory. Inside the acquisition and signal treatment subsystem the user can access to the system using conven-
tional peripherals either to manage it (keyboards , terminals) or the output data to external equipment (i .e. printers, microcomputers). These facilities
SYSTEM OPERATION AND PERFORMANCE When the CPU receives the acquiring request, before to pass the control to the DMA, it analyses the ON/OFF settings of a 4 switch set.This set controls the pretrigger amount of data. The DMA takes control of the buses and generates the start of conversion signal and repeats the operation until it fills the storage memory with new data. In t hi s manner it ensures the observation of the analog s ignal prior to the trigger point. In accordance with the pretrigger setting, that establishes the acquisition cycles number, when the trigger occurs and the number of cycles stored coincides with the number of cycles set , the acquisition is interrupted. The DMA stops and releases the buses. The acquisition is made in a cyclic manner: the storage starts at the begining of the memory area until it reaches the upper bound and then it links back with the begining address. Once the DMA is disabled, the CPU reads from the DMA the last address loaded during the acqu i sition time . Then ,
it rearranges the data in memory to ma
ke clearer its graphic representation. This rearrangement allocates the last data acquired at the last address position of the storage area, allocating the least recent at the first address . Then, the system disp lays the data acquired o n the screen. The operation can be summed up in this way: it draws a reticle and then it draws 500 data from the acquisiting memory. The reticle consists on 10 vertical lines and 16 horizontal l~ nes equally spaced. Between two consecutive vert~ cal lines there are 50 points drawed. In horizonta~ between two consecutive horizontal lines there are
16 values . There are two basic modes of data representation: the normal mode and the expanded mode. In the normal mode , the waveform drawing consists of 500 dots. Each dot represents the value of a sampled data. The system enters in this mode automatically next to the triggering operation. The user can look over all the acquisition memory in 50 sample steps. Each step represents 25 microseconds acquisition time.
are accomplished by means of RS-232C and 20 mA current loop interfaces.
The expanded mode permits the displayed wavefo r m to be analysed in detail. The disp lay shows 50 sam
Fast Data Acquisition pies. Thus it has a horizontal expansion x 10 time& Two consecutive dots corresponding to two consecuti ve samples are joined by a solid line. In both cases, the program takes account of the acquisition memory bounds to restrict the d rawing on ly to the stored data.
APPLICATION RESULTS The system was tested in three specific cases: - Periodic signals - Transient signals started by a triggering signal. - Microfuses tests. The first case merely served as an example of basic system operation. Figure 3 s hows a 75 KHz sinusoid al signal sampled and displayed in the expanded mo de. The transient analysis of signals under trigger con trol showed the good performance characteristics of the system. Thi s analysis was made using a function generator with its output enabled by a trigger. Figure 4 shows a transient captured.
41 CONCLUSIONS
Although nowadays there are many systems that are capable to capture and display single-shot analog signals they have in many cases the inconvenience o f being too expensive. This problem has been tack led with the system described in this paper. The system presents good performance characteristics. Compared to the conventiona l o n es has the advantage of being low-priced. I t can be easily built an d cou l d be useful in many applications where the sam pling rate has not the need to be too fast « 2 Msamples/second) . Further development is now intended to increase the system capabilities on the treatment of the signals captured, i.e. better graphics display , filtering algorithms, etc. that could be implemented without incurring substantial equipment expenditure. REFERENCES Yuen, C.K. , Beauchamp, K.G. and Robinson, G.P.S. (1982), Microprocessor Systems and Their Application to Signal Processing, Academic Press, London, 1982. Z80 DMA Technical Man ual , Zilog, Inc. Graphics Display Controller UPD7220. Product Description. NEC Electronics (Europe) GmbH.
Figure 5 shows the circuit used for microfuse tests The test circuit issues to the acquisition system the analogue tension corresponding to overcurrent that circulates through the fuse. The overcurrent corresponds to a current pulse that sets the fuse under extreme conditions. The user issues the current pulse and the trigger simultaneously. Figures 6 and 7 shows some typical transients reco rded . The graphics obtained during the test- correspond to the variation of fuse resistance under the current passing through it.
. -_ _ _ _L -_ _ _- , _ _ _ _
,
I
I
I
GDC
A I D CONVERTER
I
I I I
Fig .l System structure
42
P. Garcia de Madinabeitia. 1. M. Perez Toca
------------------------------------------" ~------------------------------------- r
l " A
$ 'A1 DG NO
22t
11 .\
D ,
)
T R W el f(.
se
TDC 100 1J
v,"
EL
U'
f-------------.---.
1
E5 ICl 8 0 eg
6Kn 1\
J
'4Kn 1\
Dig ita l Gr ound
~ Ana log Grou nd
- Sv
1',10"' F ig_ 2 A! D Conve r s i o n subsystem
Fig. 3
~5 KHz si~usoidal signa l. Expanded mode
Fig . 4 Transients . An
e x a~p l e
.. Tr igg er
Milc rof~l .VN ~OO1T N
Tes t Sig n al 0-5v
F i g.
Circuit
~or
~~cro ~ ~se
tes t s .
::::,~
43
Fast Data Acquisition
100
75
50
25
50
100
150
200
250
200
250
Fig. 6 Microfuse behaviour. Case 1
100
75
50
25
50
100
150
Fig. 7 Microfuse behaviour. Case 2.