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A layer damage model for calculating thermal fatigue lifetime of power devices
584
World Abstracts on Microelectronics and Reliability
experiments and theoretical calculations revealed that the moisture-induced conductance variation is 10 to 400% whereas the moisture-induced capacitance variation is 0 to 20%. Hence, even though capacitance and conductance values were measured, only conductance variations are reported. A circuit model has been developed to explain the observed experimental behavior. This technique is thus superior to capacitance technique in deterining the low levels of moisture ( < 5000 ppmu) in IC packages. The selective condensation problem experienced in the Harris or AI20 3 sensors is non existent in the conductance technique. Since the applied voltage in the conductance method is ~ 100 mV, there is no dissociation of water into hydrogen and oxygen, as is possible in the case of Harris sensors. Further, the moisture content determined by this non-destructive technique correlates well with the residual gas analysis (RGA) by the mass spectrometer. This technique is non-destructive, reliable, rapid and suitable for in-line testing. Effects of reverse bias failure on surface mounted tantalum capacitors. STEPHEN D. LINAM. Microelectron. J. 17 (4), 49 (1986).The consequences of reverse bias failure of tantalum capacitors are well-known in the electronics industry. For pinned component technologies effective strategies have been adopted which ensure correct polarization of the device. However, with adoption of surface mount technologies these polarization strategies are no longer useful. The IBM Austin System Technology Division's thermal laboratory performed failure testing of surface mounted tantalum decoupling capacitors on a vertically oriented circuit card. This testing was performed to answer the following questions. How likely is a failure of a reverse-biased capacitor at normal operating voltage? What temperatures will be caused by this failure, and how will the circuit card be affected by this temperature? How will the capacitor and card behave during failure? The purpose of this study is not to provide an evaluation of a statistically significant sample of capacitors, nor to evaluate a wide range of capacitors by varying capacitance, physical dimensions, or manufacturers. Rather, it is to provide a qualitative demonstration of the possible failure mechanisms and to demonstrate the need for specific testing of products to insure that no products will be shipped with reverse biased capacitors. The effect of long-term stress on filler-induced failure in high density RAMs. KAZUTOSHI M1YAMOTO,OSAMUNAKAGAWA, JUNICHI MITSUHASHIand HEIHACHI MATSUMOTO.24 a. Proc. IEEE Reliab. Phys. Syrup., 51 (1986). The effect of long-term high temperature stress on the filler-induced failure in high density MOS RAMs was investigated. High temperature storage causes volume reduction in some plastic resins which enhances the local strong stress to RAM chip resulting in the filler-induced failure. This phenomenon is well explained by the increase of leakage current in p - n junction under local strong stress. Gradual degradation of GaAs FETs under normal operation. MICHAEL F. MILLEA. 24 a. Proc. IEEE Reliab. Phys. Syrup., 125 (1986). The gradual degradation of low-noise and power GaAs FETs under normal operating conditions has been investigated. The degradation of the drain current under both low and normal biasing was monitored for low-noise devices, but only the degradation of the drain resistance was monitored for power GaAs FETs. Using elevated temperatures to stabilize devices and assuming a single monotonically decreasing failure mode, it is relatively simple to determine the device's long-term reliability within several days of operating at normal temperatures of 100°C or lower. This is accomplished by observing a sufficiently low degradation rate, which, when extrapolated to the desired end-oflife, yields an acceptable low long-term degradation esti-
marion. To minimize the risk associated with the possible existence of compensating gradual degradation mode,,;, the gradual degradation of devices is examined against a second gradual degradation failure criterion, which is based on the device having a sufficient low-degradation second derivative. Fulfilling the second-order failure criterion is more difficult to demonstrate and is the main focus of this investigation. Failure analysis and failure mechanisms of high voltage (530V) gated diode crosspoint arrays. P. K. TSE, J. C. GAMMEL, D. G. SCHIMMEL,W. H. BECKER,J. P. BALLANTYNE and T. J. RILEY. 24 a. Proc. IEEE Reliab. Phys. Syrup., 120 (1986). We analyzed the failure modes and failure mechanisms of high voltage (530V) Grated Diode Crosspoint arrays used in the 5ESS TM switching system. Electrical measurements and defect etching results defined the failure patterns of field returns. Laboratory stimulations were developed to reproduce each type of failure. The theory of the underlying mechanisms will be presented. Radial dependency of reliability defects on silicon wafers. HENRY A. BONGES.24 a. Proc. IEEE Reliab. Phys. Syrup., 172 (1986). A study analyzing reliability defects with respect to their original wafer location has recently been completed at IBM Burlington. The results of this study, which showed such defects to have a high radial dependency, are discussed herein. Equally important to these results is the process by which the results were obtained, a process termed Laser Chip ID. This process of permanently identifying chips by using a laser was found to be extremely useful and is also discussed in this paper. Subsurface structural defects in GaAs wafers. ROBERT M. SILVA, FRED D. ORAZIO JR and JEAN M. BENNETT. Semiconductor int., 81 (July 1986). The correlation found between measured photon backscattering levels and lattice damage in silicon wafers has been extended to gallium arsenide (GaAs). A layer damage model for calculating thermal fatigue lifetime of power devices. GAO GUANG-Bo, CHEN AN and Gu! XIANG. 24 a. Proc. IEEE Reliab. Phys. Syrup., 79 (1986). Based on the experimental data during device power cycling, the mechanical behavior of solder material, and by introducing a new concept "layer damage factor fl", the authors have proposed a layer damage model for calculating thermal fatigue lifetime of power devices. The model can be used in estimating fatigue lifetime, evaluating soldering quality, obtaining accelerated lifetime plot, designing chip backside metallizations, etc. Experimental results have been shown to support the theory. Reliability investigation of 1 micron depletion mode IC MESFETS. DOMINIC OGBONNAHand ARTHUR FRASER.24 a. Proc. IEEE Reliab. Phys. Syrup., 132 (1986). A 1.6eV activation energy has been observed for gate degradation of GaAs MESFETs fabricated with a commercially available 1 micron depletion mode IC process. Data from deep level transient spectroscopy (DLTS) and capacitance-voltage (CV) measurements are consistent with a failure mechanism of gate metal interdiffusion into GaAs resulting in a decrease of channel thickness. The median life at 290°C channel temperature (Ten) was 80 hours, with a lognormal sigma of 0.7. Using these values, the projected FET failure rate is less than 0.01%/1000 hours (100 FIT) during the first million hours of life at Ten = 150*C. High power pulse reliability of GaAs Power FETs. W. T. ANDERSON, F. A. BUOT, A. CHRISTOU and Y. ANAND. 24 a. Proc. IEEE Reliab. Phys. Syrup., 144 (1986). A study was made of degradation and burnout of GaAs power FETs resulting from high power RF pulses on the gate while operating at X-band. Burnout power per unit gate width
World Abstracts on Microelectronics and Reliability
experiments and theoretical calculations revealed that the moisture-induced conductance variation is 10 to 400% whereas the moisture-induced capacitance variation is 0 to 20%. Hence, even though capacitance and conductance values were measured, only conductance variations are reported. A circuit model has been developed to explain the observed experimental behavior. This technique is thus superior to capacitance technique in deterining the low levels of moisture ( < 5000 ppmu) in IC packages. The selective condensation problem experienced in the Harris or AI20 3 sensors is non existent in the conductance technique. Since the applied voltage in the conductance method is ~ 100 mV, there is no dissociation of water into hydrogen and oxygen, as is possible in the case of Harris sensors. Further, the moisture content determined by this non-destructive technique correlates well with the residual gas analysis (RGA) by the mass spectrometer. This technique is non-destructive, reliable, rapid and suitable for in-line testing. Effects of reverse bias failure on surface mounted tantalum capacitors. STEPHEN D. LINAM. Microelectron. J. 17 (4), 49 (1986).The consequences of reverse bias failure of tantalum capacitors are well-known in the electronics industry. For pinned component technologies effective strategies have been adopted which ensure correct polarization of the device. However, with adoption of surface mount technologies these polarization strategies are no longer useful. The IBM Austin System Technology Division's thermal laboratory performed failure testing of surface mounted tantalum decoupling capacitors on a vertically oriented circuit card. This testing was performed to answer the following questions. How likely is a failure of a reverse-biased capacitor at normal operating voltage? What temperatures will be caused by this failure, and how will the circuit card be affected by this temperature? How will the capacitor and card behave during failure? The purpose of this study is not to provide an evaluation of a statistically significant sample of capacitors, nor to evaluate a wide range of capacitors by varying capacitance, physical dimensions, or manufacturers. Rather, it is to provide a qualitative demonstration of the possible failure mechanisms and to demonstrate the need for specific testing of products to insure that no products will be shipped with reverse biased capacitors. The effect of long-term stress on filler-induced failure in high density RAMs. KAZUTOSHI M1YAMOTO,OSAMUNAKAGAWA, JUNICHI MITSUHASHIand HEIHACHI MATSUMOTO.24 a. Proc. IEEE Reliab. Phys. Syrup., 51 (1986). The effect of long-term high temperature stress on the filler-induced failure in high density MOS RAMs was investigated. High temperature storage causes volume reduction in some plastic resins which enhances the local strong stress to RAM chip resulting in the filler-induced failure. This phenomenon is well explained by the increase of leakage current in p - n junction under local strong stress. Gradual degradation of GaAs FETs under normal operation. MICHAEL F. MILLEA. 24 a. Proc. IEEE Reliab. Phys. Syrup., 125 (1986). The gradual degradation of low-noise and power GaAs FETs under normal operating conditions has been investigated. The degradation of the drain current under both low and normal biasing was monitored for low-noise devices, but only the degradation of the drain resistance was monitored for power GaAs FETs. Using elevated temperatures to stabilize devices and assuming a single monotonically decreasing failure mode, it is relatively simple to determine the device's long-term reliability within several days of operating at normal temperatures of 100°C or lower. This is accomplished by observing a sufficiently low degradation rate, which, when extrapolated to the desired end-oflife, yields an acceptable low long-term degradation esti-
marion. To minimize the risk associated with the possible existence of compensating gradual degradation mode,,;, the gradual degradation of devices is examined against a second gradual degradation failure criterion, which is based on the device having a sufficient low-degradation second derivative. Fulfilling the second-order failure criterion is more difficult to demonstrate and is the main focus of this investigation. Failure analysis and failure mechanisms of high voltage (530V) gated diode crosspoint arrays. P. K. TSE, J. C. GAMMEL, D. G. SCHIMMEL,W. H. BECKER,J. P. BALLANTYNE and T. J. RILEY. 24 a. Proc. IEEE Reliab. Phys. Syrup., 120 (1986). We analyzed the failure modes and failure mechanisms of high voltage (530V) Grated Diode Crosspoint arrays used in the 5ESS TM switching system. Electrical measurements and defect etching results defined the failure patterns of field returns. Laboratory stimulations were developed to reproduce each type of failure. The theory of the underlying mechanisms will be presented. Radial dependency of reliability defects on silicon wafers. HENRY A. BONGES.24 a. Proc. IEEE Reliab. Phys. Syrup., 172 (1986). A study analyzing reliability defects with respect to their original wafer location has recently been completed at IBM Burlington. The results of this study, which showed such defects to have a high radial dependency, are discussed herein. Equally important to these results is the process by which the results were obtained, a process termed Laser Chip ID. This process of permanently identifying chips by using a laser was found to be extremely useful and is also discussed in this paper. Subsurface structural defects in GaAs wafers. ROBERT M. SILVA, FRED D. ORAZIO JR and JEAN M. BENNETT. Semiconductor int., 81 (July 1986). The correlation found between measured photon backscattering levels and lattice damage in silicon wafers has been extended to gallium arsenide (GaAs). A layer damage model for calculating thermal fatigue lifetime of power devices. GAO GUANG-Bo, CHEN AN and Gu! XIANG. 24 a. Proc. IEEE Reliab. Phys. Syrup., 79 (1986). Based on the experimental data during device power cycling, the mechanical behavior of solder material, and by introducing a new concept "layer damage factor fl", the authors have proposed a layer damage model for calculating thermal fatigue lifetime of power devices. The model can be used in estimating fatigue lifetime, evaluating soldering quality, obtaining accelerated lifetime plot, designing chip backside metallizations, etc. Experimental results have been shown to support the theory. Reliability investigation of 1 micron depletion mode IC MESFETS. DOMINIC OGBONNAHand ARTHUR FRASER.24 a. Proc. IEEE Reliab. Phys. Syrup., 132 (1986). A 1.6eV activation energy has been observed for gate degradation of GaAs MESFETs fabricated with a commercially available 1 micron depletion mode IC process. Data from deep level transient spectroscopy (DLTS) and capacitance-voltage (CV) measurements are consistent with a failure mechanism of gate metal interdiffusion into GaAs resulting in a decrease of channel thickness. The median life at 290°C channel temperature (Ten) was 80 hours, with a lognormal sigma of 0.7. Using these values, the projected FET failure rate is less than 0.01%/1000 hours (100 FIT) during the first million hours of life at Ten = 150*C. High power pulse reliability of GaAs Power FETs. W. T. ANDERSON, F. A. BUOT, A. CHRISTOU and Y. ANAND. 24 a. Proc. IEEE Reliab. Phys. Syrup., 144 (1986). A study was made of degradation and burnout of GaAs power FETs resulting from high power RF pulses on the gate while operating at X-band. Burnout power per unit gate width