Innovative Methodology for Predictive Reliability of Intelligent Power Devices Using Extreme Electro-thermal Fatigue

Microelectronics Reliability 45 (2005) 1717–1722 www.elsevier.com/locate/microrel

Innovative Methodology for Predictive Reliability of Intelligent Power Devices Using Extreme Electro-thermal Fatigue B. Khonga, P. Tounsib, Ph. Dupuyc, X. Chauffleurd, M Legrosa, A. Deramc, C. Levadea, G. Vanderschaevea , J-M. Dorkelb, J-P. Fradind a.

CEMES-CNRS, 29 rue Jeanne Marvig, 31055 Toulouse LAAS-CNRS, 7 avenue du Colonel Roche - 31077 Toulouse c. Freescale Semiconductor, avenue du Général Eisenhower, 31023 Toulouse d. Epsilon Ingénierie, 10 rue Jean Bart - BP 97431- 31674 Labège b.

Abstract In this paper, an innovative methodology for predictive reliability of intelligent power devices used in automotive applications is considered. Reliability management is done at all levels of the technological process. This method is based on the failure analysis along with electro-thermo- mechanical modeling and on extreme fatigue testing. A new power MOS device has been electrically fatigued in order to evaluate its failure modes. Using a thermally regulated test bench, electrical pulses were applied to the device until failure. This failure is associated to several structural changes that have been investigated through acoustic and electron microscopy. Delamination was observed preferentially at the solder between the copper heat sink and the die. Ó 2005 Elsevier Ltd. All rights reserved.

1. Introduction Over the last years, designers of automotive systems have increasingly been focusing on Intelligent Power Switches (IPS’s) rather than electromechanical relays to control automotive loads. This has been mainly driven by the need to benefit commercially from more functionalities and improved performance [1,2], while taking into account application environment considerations. Thus, the assembly technology switch devices become ever more complex and often the thermomechanical stresses which result from self-heating become critical. Also, reliability requirements coupled with costs that have to be kept firmly under control have been imposed by the onboard systems device market. As a result, managing the reliability of the new generation of devices has become

highly strategic. As a matter of fact, two goals are sought simultaneously: - reduce product development costs as well as the time needed for evaluation and qualification. - create a well documented guide about the product trends and the design of more efficient products. To meet part of these requests, a new approach turned out to be essential to predict the reliability of the new assemblies. The method proposed is both generic since it draws up the rules for the analysis and modeling of the phenomena involved, and specific since it enables us to build up a data and knowledge bank for designers of a family of devices. The main challenge is to develop a methodology of accelerated reliability tests in order to predict the lifetime of the electronic devices, based on micro structural characterizations, physical characterizations

0026-2714/$ - see front matter Ó 2005 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2005.07.104

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and new complex simulation techniques. The innovative approach should simulate the complete fatigue tests from the oven to the device itself, so as to be able to predict the lifetime of the device in its real application. To do so, electrothermal modeling is associated with thermo-mechanical modeling to predict the most common failure modes. Through this approach, one intends to define and validate the physical models and methods leading to an evaluation of the lifetime of these devices. Due to a large mismatch between the coefficients of thermal expansion of copper and silicon, the solder between the heat sink and the die (die attach) is exposed to fatigue strains and is often a critical location for delamination and cracking [3]. Other interfaces such as metallization/silicon or wirebonding/metallization are also potentially vulnerable sites. Because these components consist of different materials and have different length scales, several tools are necessary to analyze their structure. Scanning acoustic microscopy (SAM) was mainly used to measure the amount of delamination occurring at the die attach. In areas where delamination was revealed, cross-sectional polishing and subsequent scanning electron microscopy (SEM) was performed. Finally, to investigate microstructural evolution in the Al metallization and at the Al/Si interface, transmission electron microscopy (TEM) was applied. The aim of this work is to define a design methodology for this type of product by taking into account predictively the thermal fatigue effects. 2. General Methodology The proposed approach consists in implementing a methodology to evaluate the reliability of the electronic assembly under real operating conditions. So far, the reliability of mass produced structures has been assessed by statistical testing that yields a Mean Time Before Failure. However, with the new technological developments the MTBF assessment tools must be constantly reviewed [4]. The original feature of our approach lies in taking advantage of the latest developments related to a better physical knowledge of failure mechanisms. Thus, the number of validation tests can be reduced and we can take advantage of the predictive nature of a physical characterization. Because careful attention has been paid to the control of the electrical and thermal environment of the DUT (Device Under Test), we can

extrapolate results of accelerated failure tests that were conducted in the real application. The main steps in the extrapolation and use of these results are based on: ¾ The IOL (Intermittent Operating Life) : this test forces the device to switch on and off a 120 Amps current with a variable duty cycle. The latter will be optimized to enable a larger temperature range between the ON state of the MOS transistor device and its blocked state (optimum stress). This is the most stringent fatigue test. It can reach a few million cycles in less than 60 days, thereby allowing for accelerated ageing. ¾ The electrothermal simulation is used to realistically take into account the temperature drift of power dissipated by the devices when they operate under real conditions. Thus one can compute more realistically the temperature distribution in the active zone and in those areas likely to withstand high mechanical stress. ¾ Thermo-mechanical simulation is used to determine the displacements, distortions and stresses of the structure and especially in the various layers of the device. ¾ An accurate analysis of the defects found using SAM, SEM and TEM exploration and observation of interfaces affected by delaminations or other defects. The impacts of defects on the electrical functions of the devices are monitored during the test and are then modelled with the ultimate goal of arriving at a self-check of the devices during operation. ¾ Given the lack of accuracy governing the Coffin-Manson fatigue laws associated with the application conditions, an adequate generic fatigue model has been implemented. Figure 1 summarizes the overall methodology followed for the optimization of the structures based on the application sought and its environment. 3. General setup The principle of the chosen method relies on the same complete management of the devices’ environment under electrothermal stress. Hence, the installation of a thermal cycling bench and the need to interpolate results with reliable models has urged us to characterize and to model as accurately as possible the thermal oven used. In addition, for all DUTs

B. Khong et al. / Microelectronics Reliability 45 (2005) 1717–1722

undergoing the same temperature and flow temperatures, an optimization study has been carried out. Application

Data collection : Electrical specifications Component description (geometry, structure,…)

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DT (°C)

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20 Experiments hard ware: - Test bench development - Mother board + PCB design - Soft definition

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10 Electro-thermal modeling

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Physical Analysis

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Thermo-mechanical modeling Constraints identification (?)

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Number of cycles before failure Technology / Package optimization

Fig. 1. General flowchart of the predictive reliability 3.1. Oven characterization and optimization Characterization has been performed using the CFD FLOTHERM simulation tool. First, a fluidic model has been devised to grasp the flow inside the oven. Air flow velocity measurements were conducted with anemometers to derive a relationship between self heat and air velocity (see Fig 2). Then, a simplified thermal model has been drawn up to model the oven’s thermal behaviour. The aim is to apply the convection coefficients to the detailed device model on the PCB depicted and simulated with the REBECA-3D software. Also the aim of optimization is to make sure all DUTs are undergoing the same conditions so that the static scattering of fatigue tests can only be assigned to the possible initial defects of devices and not to the external stimuli. By tracing the cause and effect tree (failures, thermo-mechanical, thermal defects, dissipated power) one can see that thermal exchange coefficients (and therefore air velocity) are identical on all components and PCBs. Following the study, improvement has taken the form of a standardization of the thermal stress withstood by PCBs, with the placement of spoilers (see Figs 2 and 3). 3.2. Models setup Self-heating effects are most often enhanced by electrothermal couplings in the chip and in the connections. Therefore, accurate modeling of the electrothermal coupling effects becomes essential for the design of reliable power converters.

0

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Fig. 2. Temperature scattering on DUTs according to the air flow velocity New generation of low voltage power MOS devices have surprisingly good on-state performances (RDSon is close to 1 m:), so that the power dissipation in the connecting elements (wire-bonding and electrical contacts) will have an increased importance compared to the old power MOS generations. In addition, the thermal conductivity and most of the main electrical parameters (especially the carrier mobility) are locally temperature-dependent.

(a)

(b)

(c) (a) air circulation principle (b) modeling the oven with spoilers (c) fabrication Fig. 3. Leveling temperature with spoilers The dissipated power is distributed in the various zones (epitaxied layer, bulk, bonding wires and metallization). For each zone, the temperature dependence of the electrical and thermal characteristics is taken into account. As a 3-D thermal model is used [5], one gets a 3D electrothermal modeling.

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Figure 4 shows the temperature trend in the areas considered following IOL test pulses (120 Amps for 820ms).

include part of the Si substrate and most of the metallization, but the contact between the Al wire and the Al metallization was also seldom observed. In the present paper, we will not compare the results from the different tests. Only the qualitative effects of the electrical cycling will be presented. 4. Results 4.1. Thermomechanical modeling

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Fig. 4. Electrothermal modeling results 3.3. Defect analysis procedure In order to electrically test the power device, a thermally regulated electrical bench was set up. Batches of coupons, each containing one power MOS were cycled simultaneously. One cycle consists of a 120 Amps square electrical pulse followed by a 9 s pause. To date, five tests have been performed with pulse duration ranging from 0.5 to 1 second. The drainsource resistance was monitored until it exits the range of acceptable specifications by 10%. In parallel, calculations of temperature gradient and stresses were computed using REBECA-3D, finite element software. Failed devices are then inspected by SAM to determine the amount of delamination surface under the die. Cross-sections were polished using a tripod grinder and diamond lapping films. For each device, cross sections were made both parallel and perpendicular to the top bonding wires following the same polishing procedure. Attention was taken to inspect die attach delaminated areas (as shown by SAM) in priority, but Al wires, silicon substrate and the solder between PCB and heat sink were also inspected by SEM. Finally, TEM crosssections were prepared with the aim of detecting microstructural changes in the Al metallization down to the Si die. Electron transparent thin foils usually

Simulations take into account the materials nonlinearities (plasticity, viscoelasticity, viscoplasticity, and temperature-dependence). Two types of simulations are conducted: • Simulation of the device fabrication process: chips are welded on a leadframe and resin is injected and reticulated. • Simulation of IOL tests stress based on the temperature curve obtained from the electrothermal simulations. As the device is transferred onto the PCB by means of a very thin brazing layer, the mechanical behaviour is very much dependent on that of the PCB. Particular attention has been paid to PCB modeling with the implementation of a method for determining the complete anisotropic behavioural matrix of PCB based on each prepreg. Figure 5 shows the details of the PCB model, the surrounding epoxy is hidden to show warp and fill fibre bundles.

(a) (b) (a) prepreg 2216, (b) prepreg 106 Fig. 5. FEM unit cell of two types of prepregs The simulations of stresses and strains in the device as tested in the bench (that is with its mold compound and attached to the PCB) give information on the origin of the delaminations. Figure 6a shows the equivalent stress in the mold compound at the end of the back end process. One can clearly see important stresses around the power chip at the mold-leadframe interface what corroborates the observations in SAM which show delamination in this area.

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(a) Process impact (stress)

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examinations have been performed. Figure 8 presents two cross sections cut along the most external Al wire. In the case of the stressed sample, this location corresponds to a supposed delaminated area As seen in figure 8c, if an extensive delamination is revealed by SAM, this is also observed in SEM. In rare cases, SAM indicates large delamination area that reveals only partial in SEM. In average, the devices that display large delamination areas with SAM are those whose drain-source resistance rise above the accepted specifications. Both observation are thus needed to estimate the proportion of failed solder. In a first approximation, SAM gives a correct image of failed devices. Aw Pd Cc

(b) Power pulse impact (displacement) Fig. 6. Thermo-mechanical simulations Figure 6b shows the displacements along the Z axis (normal to the PCB) in the complete device. One can notice in this figure that the edges of the lead frame and the mold undergo most of the load. Moreover, the top of the die, where the wires are attached, is mostly in compression. This is expected because the Cu heat sink beneath tends to expand more than the Si substrate when the system is heated by Joule effect. As a result, the delamination under the power die is expected to initiate at the edges where the shear stress is higher and subsequently propagate towards the center. 4.2. Physical analysis 4.2.1 Delamination at the die attach After each test, the die attach was systematically inspected using SAM. Figure 7 presents an example of SAM images taken on an untested device (Fig. 7a) and on another one after several 10 000 cycles (Fig. 7b). In figure 7b, the delaminated area corresponds to the total area of the die, which should mean that the Si substrate is not attached anymore to the heat sink. However, because of the poor spatial resolution of the SAM, further

(a) Aw: Al wire, Pd: Power die, Cc: Control chip

(b) (a) Unstressed sample, (b) After electrical cycling Fig. 7. SAM images of delamination at the die attach 4.2.2 Microstructural changes in the Al metallization Because the Al metallization is also subjected to both stress and temperature gradients, its microstructure is prone to evolve along cycling. In the case of the unstressed component (Fig. 9a), the grains are much smaller than the metallization thickness and are thus able to grow. This is what happened in the stressed component (Fig. 9b) where an Al grain has noticeably grown.

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POWER DIE POWER DIE

DIE ATTA

Al WIRE

estimate and warrant the lifetime of devices undergoing development, through extreme fatigue testing, physical analysis and related models. In addition, the knowledge base which is derived from the methodology proposed brings a valuable help in the design of the next generation of sturdier power devices.

LEADFRAME LEADFRAME

(a) (b) (a and b) Unstressed specimen LEADFRAME

(a) POWER DIE

(c) Major cracks in the die attach and in the die in the stressed specimen Fig. 8. Cross section SEM pictures of the die attach In the region in contact with the Si substrate grain, growth is also very significant although less pronounced because of the topological constraint imposed by the substrate. One can note the high dislocation density in the large grain of figure 9b, which is an indication of a plastic deformation of the metallization. 5. Conclusion Today, power switches are increasingly used to carry out functions in onboard systems. Generally, these functions are designed to provide for the safety and security of systems and humans. The reliability of electronic systems depends on the reliability of all electronic devices. Power devices raise specific selfheat issues. In addition, there is a commercial need for power devices (MOS, IGBT…) to be both efficient and cost effective. As a result, manufacturers keep looking for ways of developing new generations of devices while cutting down evaluation and qualification costs. On the other hand, to ensure continuous operation (and to lower the systems failure rates), the lifetime of devices has to be assessed. This can only be done if one takes into account the real environment and the application considered. With this in mind, we have developed a full range of procedures designed to

(b) Fig. 9. Cross section TEM images of Al metallization Acknowledgements The authors would like to thank the Regional Council of Région Midi-Pyrénées for its financial support. References [1] Kassakian, J.G. ‘Automotive electrical systems-the power electronics market of the future.’ in Applied Power Electronics Conference and Exposition (APEC 2000), 15th annual IEEE. 2000. New Orleans, LA, USA. [2] Perreault, D.J. and V. Caliskan, ‘Automotive Power Generation and Control’. IEEE Transactions on Power Electronics, 2004. 19(3). [3] Liu and Plumbridge, ‘Thermomechanical fatigue of Sn– 37 wt.% Pb model solder joints.’ Materials Science and Engineering A, 2003. 362: p. 309-321. [4] J. M. Bosc, P. Dupuy, J. Gill, J. M. Dorkel, G. Sarrabayrouse ‘Thermal Characterization: A Key Element for Accelerating Stress Testing’, 5th THERMINIC Workshop, 3-9 October 1999, Rome, Italy. pp299-304. [5] J.P. Fradin, B. Desaunettes, ‘REBECA-3D: the thermal conductive solver for microelectronics’, Microelectronics Journal, Vol 29, Num 9, September 1998, pp651-656.