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Characterization of alterations on power MOSFET devices under extreme electro-thermal fatigue
Microelectronics Reliability 50 (2010) 1768–1772
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Characterization of alterations on power MOSFET devices under extreme electro-thermal fatigue D. Martineau a,*, T. Mazeaud b, M. Legros a, Ph. Dupuy b, C. Levade a,c a
CEMES-CNRS, 29 rue Jeanne Marvig, 31055 Toulouse Cedex 4, France Freescale Semiconductors, Inc., avenue du Général Eisenhower, 31023 Toulouse, France c Université de Toulouse, INSA, 31077 Toulouse Cedex, France b
a r t i c l e
i n f o
Article history: Received 30 June 2010 Accepted 19 July 2010 Available online 8 August 2010
a b s t r a c t Extreme electro-thermal fatigue tests on power MOSFET-based switches for automotive applications have been performed in order to pinpoint their failure mechanisms. Contrary to devices from the former technology generation, the most important failure mode concentrates in the source metallization zone and consists in the degradation of the metallic layer. Intense intergranular and surface diffusion triggered by the thermal stresses between the Si substrate and the Al layer leads to intergranular crack formation. Around the ultimate life time (ULT) of the device, these intergranular cracks burrow almost down to the active transistor region and their density on the source surface is high enough to cause a loss of contact between the metal grains. The observed increase of the drain-source resistance could be attributed to this degradation that have qualitatively modeled. Observed melt down of the Al layer revealed by the formation of Al/Si eutectic could be the result of hot spots due to spikes in source resistance. Ó 2010 Elsevier Ltd. All rights reserved.
1. Introduction Because on-board electrical functions are multiplying in modern automobiles the number of integrated silicon switches and the electrical load they are submitted to keep increasing too. Some electrical functions (external lighting, ABS . . . ) are critical for safety and therefore demand a perfect reliability. Implementing new switches implies to acquire a good knowledge of their reliability as well as their mode of ageing [1]. Many different processes can cause power device ageing because there are many different types of components with various specifications [2–5]. The most important failure mode in the previous generation devices was related to the drain of the power chip. Delamination appeared at the die attach solder between the silicon substrate and the copper heatsink and isolated the drain from the source [6]. This delamination was triggered by the large mismatch between the thermal expansion coefficients of copper and silicon and the propagation of fatigue cracks in the solder [7]. In this work, we have studied several Freescale Semiconductor components based on the most recent technology [2]. The component structure was optimized by a new design on the leadframe in order to decrease the die attach delamination. These so-called ‘‘smart power” switches are composed of a MOSFET power device associated with a control chip both mounted on a single frame. The control die is able to detect errors and monitor the electric fluctuations of the
* Corresponding author. Tel.: +33 562257831; fax: +33 562257999. E-mail address: [email protected] (D. Martineau). 0026-2714/$ - see front matter Ó 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2010.07.065
power unit. They are used to command the on/off states of light bulbs for automobiles. The MOSFET power device contains four areas with 15 mX drain-source resistance (Rdson) at 25 °C driven independently by the control chip [8]. Accelerated electrical fatigue tests were performed to assess the devices robustness beyond the operating limits: cyclic electrical pulses with loads of about twice the nominal value were injected in the power die. The ultimate lifetime in extreme conditions is then determined and followed by a multi-scale structural analysis of the devices at various ageing states. In this new generation of device, the most significant failures occur in the source region of the MOS that is the top metal and the wire bondings [9–11]. This paper provides detailed evidences of the ageing modes of this region and proposes a sequence of physical processes that may lead to the structural changes observed in the source metal and the subsequent increase in the switch resistance. 2. Experimental procedure Devices to be tested are first inspected by X-ray analysis to observe potential voids. Transmitted (SAT) and regular (SAM) acoustic microscopy were also performed to evaluate potential defects and initial delamination on the top and beneath the power die. Batches of 10 coupons carrying these devices were then electrically tested in two similar and thermally regulated electrical benches. One of the most harmful tests consisted in trains of 90 A square electrical pulses of 200 ms followed by 9.8 s pause in
D. Martineau et al. / Microelectronics Reliability 50 (2010) 1768–1772
Fig. 1. Acoustic microscopy and X-ray images of an aged device. Delaminations are observed by SAM at the mold (a) and by SAT at the die attach (b). The control and power die are indicated by doted lines in (b). Red zones in (a) correspond to delamination area between the mold and the power die and black zones in (b) correspond to delaminated area between the power die and the leadframe. In the Xray image (c) the white arrow points to a void in the solder between the power die and the leadframe. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)
a 85 °C atmosphere. The current surge triggered an overload protection in the control chip that turned off the MOS after about 6 ms. Devices were tested by batches of 10. The condition of five broken down components was chosen as the device lifetime for this electrical test. A second batch of 10 devices was then tested in the same condition and five devices were stopped at one third of the lifetime while the five others were run up to 2/3rd of the lifetime. In some tests (see Fig. 2 for instance), tests were carried out much further than the determined lifetime to explore the evolution of the device resistivity. The Rdson was measured by the control die and four-probe resistance measurements of the metal source were performed after the device mold compound was removed. Stressed devices were re-examined by X-ray, SAM and SAT to check for a potential evolution of the component structures. We mainly focused on the active MOS area: Al wires and metallization, silicon substrate and polysilicon spacers. Scanning Electron Microscopy (SEM) and Focused Ion Beam (FIB) observations were also carried out on the metallization and Al wires after the removal of the mold compound by chemical etching. The final step was to inspect the active MOS area using Transmission Electron Microscopy (TEM). In parallel, finite element (FE) calculations using COMSOLÒ Multiphysics software were run to simulate and map the temperature increases inside the device during an electrical pulse. 3. Results SAM, SAT and X-ray results were compared before and after electrical ageing. SAM allowed us to investigate both the mold compound/die and the leadframe delamination. SAT addressed the die attach delamination while the solder voids between the leadframe and the power die were inspected with X-rays. Contrary to the previous generation of this kind of component, no significant delamination was observed (Fig. 1a and b) [6]. This shows a better ability of this new generation to maintain a constant evacuation of
Fig. 2. Rdson measurements of different aged devices. A 20% increase was observed after 250 kcycles.
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Fig. 3. Probe needles resistance measurements on different aged metallizations. The initial resistance of the source metal was multiplied by a factor of 10 for the most aged devices.
Fig. 4. SEM images of Al metallization. Before tests (a) and after a 90 A square electrical pulse during 250,000 cycles at 85 °C (b). White arrows show some emerging cracks in the metallization layer.
heat between the silicon and the copper leadframe or a better ability to the solder to resist crack propagation. As in the previous generation, the initial voids at the interface between the power die and the leadframe did not show significant growth (Fig. 1c). An increase of Rdson resistance by about 20% was observed on the most aged devices (Fig. 2). As illustrated in Fig. 1, this increase was not a result of the delamination in the drain region and we focused our study on the source region: Al metallization and Al wires. Electrical measurements were realized by probe needles on the metallization and an increase of the resistance of this Al metallization was identified (Fig. 3). These observations confirmed that the ageing of the metallization is important in the Rdson increase. SEM observations of the Al metallization revealed an important degradation. Fig. 4a represents the surface of the metallization before testing and (b) after 250 kcycles. In (a) square structures correspond to the initial transistor cells viewed from above. The bumped aspect is due to the conformation of the deposited Al layer to the polysilicon and oxide motive (visible in Fig. 5). In (b) the metallization underwent a complete degradation with a large number of surface cracks. The reason for the generation of these cracks will be discussed later. To further analyze these surface cracks, we also performed ion milling of the metallization with a Focused Ion Beam (FIB). Ionic images were taken across the thickness of the metallization to observe the Al layer microstructure. Channeling contrast renders possible the identification of single Al grains with different crystallographic orientations (Fig. 5). The initial metallization is composed of columnar Al grains. Their shape roughly consisted in 10 lm high cylinders with about 3 lm of diameter (Fig. 5a). Nanometer-size black dots are probably Si precipitates (the Al metallization contains 1% Si in weight that is not soluble at RT). Fig. 5b–d correspond to devices that underwent 45,000, 90,000 and 250,000 cycles. Two phenomena are happening in parallel. First, the initial columnar grains transform into smaller grains after 45 kcycles (Fig. 5b) and 90 kcycles (Fig 5c). Grain sizes varied from
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Fig. 5. Ionic images taken through the metallization thickness. The Al columnar grains in (a) correspond to a device before test. The smaller grains in (b)–(d) correspond to a stressed device after 45,000, 90,000 and 250,000 cycles of 90 A electrical pulses, respectively. White arrows point to intergranular cracks in the metallization layer.
1 lm to 4 lm. A complete statistical analysis of grain sizes would require observations of larger areas and should be performed in the near future. On the other hand, intergranular cracks (white arrows) have clearly developed in this structure (Fig. 5b–d). These cracks propagated between the grains (Fig. 5b) parallel to the surface or from the surface down to the active area of the MOS (Fig. 5c), at the interface between Si and Al. These cracks cause a decohesion between the Al grains and if their electrical conductivity is low, their density is sufficiently high to explain the increase in metallization resistance (Fig. 2). Although not easily measurable, the local Rdson value of a transistor cell could be considerably increased because of these cracks and ultimately create a hot spot responsible for a local melting of the Al layer and a failure of the MOS, as observed in a previous study [10]. To confirm these observations, TEM preparations were also done by FIB in the aluminum metallization of different components (Fig. 6). As revealed by ionic microscopy, the initial structure of Al metallization is made of grains with a columnar shape (Fig. 6a). The diameter is about 3 lm and the height corresponds to the layer thickness. In a device stressed to 250 kcycles of 90 A electrical pulses at 85 °C, the structure of the Al metallization has changed (Fig. 6b). The columnar structure has disappeared and grains have now smaller sizes, between 1 lm and 4 lm. Some intergranular cracks appear between Al grains. Their discontinuous aspect compared to the FIB images of Fig. 5 is due to the limited foil thickness in TEM and to the fact that the TEM image is a projection of the volume. The multiplication of grains boundaries is also a potential source of resistance increase [12], but could not explain the factor 10 observed in Fig. 3. Diffusion of Al in the silicon wafer was not observed but remains highly unrealistic as no contact modification in the active area was observed in Fig. 5b–d. A decrease in the density of Si precipitates can however be noticed from Fig. 5a–d, suggesting that Si atoms may have diffused in the metallization.
Fig. 6. TEM images of the Al metallization structure. Before tests (a) and after 250 kcycles at 85 °C (b). In (a) Al grains have a columnar shape (height equivalent to the layer thickness) while they are much smaller in (b) (about 3–4 grains in the layer thickness. White arrows show some intergranular cracks.
The degradation of the Al layer is therefore characterized by two phenomena: – Intergranular cracking. – Grain size reduction. A qualitative model for the development of intergranular cracks during thermal cycling of a polycrystalline Al film can be extended from the Gao model that was initially developed to explain the stress relaxation by diffusion of ultra thin metallic films like gold and copper that do not form adhesive native oxide [13]. In this model, the stress in tension can be relieved by incorporating the surface atoms into perpendicular grain boundaries that act as fast diffusion wedges. The model was not developed for compression, but several examples show, however that diffusion along GBs is active in Al films undergoing thermal cycles despite the presence of a native oxide [14–16]. In compression (that is during heating phases), Al atoms oxidize rapidly when they emerge from the inner film through GB (Fig. 7b) they form hillocks that will not annihilate by surface diffusion. When reversing the temperature gradient (cooling), the Al layer turns tensile and this causes grain boundary grooving, that is again stabilized by oxidation of bared Al surfaces. Repeating this grooving process leads to the decohesion of grains whose boundaries have been oxidized (Fig. 7c). This qualitative model explains well the degradation of the Al surface combined with cracks propagation along the grain boundaries. On the other hand, the division of initially large columnar grains may be attributed to regular dislocation processes. In situ thermal heating experiments in the TEM on cross sectional samples [17] have demonstrated that dislocation-based plasticity operate in a range of 200–450 °C during heating and down to a few tens of °C when cooling down from 450 °C (not shown). Both experiments
D. Martineau et al. / Microelectronics Reliability 50 (2010) 1768–1772
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Fig. 7. Qualitative model for the development of intergranular cracks during thermal cycling of a polycrystalline Al film. (a) Initial state: grains are in a columnar state and the grain boundaries (GB) are perpendicular to the free surface that is covered with the Al native oxide (red layer). (b) Heating phase: Al film in compression, formation of hillocks. (c) Cooling phase: Al film in tension, cracks open (see text for details). (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)
are very different as the temperature range is much larger and the temperature gradient much lower during in situ TEM when compared to real electro-thermal fatigue (see Fig. 8). It shows, however that dislocations move easily at relatively low temperature in the Al metallization. Repeated cycles are then prone to accumulate dislocations in the Al grains and therefore create cells that will transform into grains when the added misorientations are sufficient. This classic recovery process is helped by mixed dislocation and diffusion processes such as dislocation climb. The degradation of the Al layer is thus a combined effect of accelerated diffusion at grain boundaries and division of initially large grains by dislocation-based plasticity. To have a more acute estimation of the temperature gradient and the potential hot spots inside the power die, we performed finite elements calculations with the COMSOLÒ Multiphysics software. The objective was to simulate and map the temperature increase inside the device during an electrical pulse based on previous electrical simulations [18]. For a 90 A electrical pulse lasting 5.7 ms with a metallization in its initial state, a maximum temperature of 172 °C was attained in the middle of the Al layer (Fig. 6a). As expected from the structural observations, the metallization is the hottest zone of the component, before the wire bondings and the Si substrate. The temperature gradient over the Al layer did not exceed 60 °C in the initial configuration (Fig. 8a) but reached more than 140 °C in the aged state (that is with a metallization resistance multiplied by a factor 10 – Fig. 8b). In this later case, the maximum temperature was 256 °C (Fig. 8b). The increase in metallization resistance cannot be simulated so far and was based on actual probe-needle measurements. The temperature gradient also increases between the Al layer and the Si substrate, and this promotes a stronger delamination caused by the mismatch between the thermal expansion coefficients of Al and Si. The increase in temperature of the Al layer accelerates the diffusion between aluminum grains and therefore the increase of the resistance metallization and finally an accelerated ageing of the component. A few point remain partially unclear: – The degradation seems very uniform on the surface while simulations tend to show that, when the resistance increases, the temperature rises mainly in the middle of the Al layer.
Fig. 8. Map of the temperature in one cell of the power device following a 5.7 ms and 90 A electrical pulse in a 25 °C atmosphere. The lower pads represent the Cu lead frame while the long rectangles stand for the wire bondings. The hottest zone (red) corresponds to the Al metallization located above the Si substrate. An increase in the maximum temperature going from 172 °C in (a) to 256 °C in (b) is caused by a multiplication of the Al layer resistance by 10. This resistance increase corresponds to an aged device (b) compared to an as-processed one (a). (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)
– Several cracks are observed in the vicinity of the wire bondings and their configuration remains difficult to acquire. It is for instance hard to evaluate the extension of cracks under the wire. In conclusion, simulations and experiments do converge to pinpoint the Al degradation as the main source of ageing for these components. A qualitative model for this degradation, consisting of grain refinement and intragranular diffusion of matter has been proposed. Further work is needed to quantify the physical mechanisms at work (grain boundary diffusion, dislocation-based plasticity, recovery). Acknowledgement The authors would like to thank the Regional Council of Région Midi-Pyrénées for its financial support. References [1] Muller-Friedler R, Knoblauch V. Reliability aspects of microsensors and micromechatronic actuators for automotive applications. Microelectron Reliab 2003;43(7):1085.
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[2] Khong B et al. Innovative methodology for predictive reliability of intelligent power devices using extreme electro-thermal fatigue. Microelectron Reliab 2005;45(9–11):1717. [3] Lefebvre S, Khatir Z, Saint-Eve F. Experimental behaviour of single-chip IGBT and COOLMOS devices under repetitive short-circuit conditions. IEE Trans Electron Dev 2005;52:276. [4] Lutz J, et al. Power cycling induced failure mechanisms in the viewpoint of rough temperature environment. In: Proceedings of the 5th international conference of integrated power electronic systems; 2008. p. 55–8. [5] Belaid MA et al. Reliability study of power RF LDMOS device under thermal stress. Microelectron J 2007;38(2):164. [6] Khong B et al. Alterations induced in the structure of intelligent power devices by extreme electro-thermal fatigue. Physica Status Solidi (c) 2007;4:2997. [7] Ciappa M. Selected failure mechanisms of modern power modules. Microelectron Reliab 2002;42:653. [8] Freescale data sheet MC15XS3400.. [9] Arab M, Lefebvre S, Khatir Z, Bontemps S. Experimental investigations of trench field stop IGBT under repetitive short-circuits operations. In: Power electron specialists conf; 2008. p. 4355. [10] Martineau D et al. Characterization of ageing failures on power MOSFET devices by electron and ion microscopies. Microelectron Reliab 2009;49(9–11):1330.
[11] Bernoux B, Escoffier R, Jalbaud P, Dorkel JM. Source electrode evolution of a low voltage power MOSFET under avalanche cycling. Microelectron Reliab 2009;49(9–11):1341. [12] Carreau V. Contrôle microstructural du cuivre aux dimensions nanométriques: application à la maîtrise de la résistivité des interconnexions en microélectronique. Institut Polytechnique de Grenoble; 2008. [13] Gao H et al. Crack-like grain-boundary diffusion wedges in thin metal films. Acta Mater 1999;47(10):2865. [14] Legros M, et al. Plasticity-related phenomena in metallic films on substrates. Multiscale phenomena in materials experiments and modelling related to mechanical behaviour, San Francisco; 2003. [15] Legros M, Dehm G, Balk TJ. In-Situ TEM study of plastic stress relaxation mechanisms and interface effects in metallic films. In: Thin films: stress and mechanical properties XI. San Francisco: Materials Research Society; 2005 [16] Eiper E, Keckes J, Martinschitz KJ, Zizak I, Cabié M, Dehm G. Size-independent stresses in Al thin films thermally strained down to 100 °C. Acta Mater 2007; 55(6):1941–6. [17] Legros M, Cabie M, Gianola DS. In situ deformation of thin films on substrates. Micros Res Tech 2009;72(3):270. [18] Sauveplane JB, Tounsi P, Scheid E, Deram A. 3D electro-thermal investigations for reliability of ultra low ON state resistance power MOSFET. Microelectron Reliab 2008;48:1464.
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Characterization of alterations on power MOSFET devices under extreme electro-thermal fatigue D. Martineau a,*, T. Mazeaud b, M. Legros a, Ph. Dupuy b, C. Levade a,c a
CEMES-CNRS, 29 rue Jeanne Marvig, 31055 Toulouse Cedex 4, France Freescale Semiconductors, Inc., avenue du Général Eisenhower, 31023 Toulouse, France c Université de Toulouse, INSA, 31077 Toulouse Cedex, France b
a r t i c l e
i n f o
Article history: Received 30 June 2010 Accepted 19 July 2010 Available online 8 August 2010
a b s t r a c t Extreme electro-thermal fatigue tests on power MOSFET-based switches for automotive applications have been performed in order to pinpoint their failure mechanisms. Contrary to devices from the former technology generation, the most important failure mode concentrates in the source metallization zone and consists in the degradation of the metallic layer. Intense intergranular and surface diffusion triggered by the thermal stresses between the Si substrate and the Al layer leads to intergranular crack formation. Around the ultimate life time (ULT) of the device, these intergranular cracks burrow almost down to the active transistor region and their density on the source surface is high enough to cause a loss of contact between the metal grains. The observed increase of the drain-source resistance could be attributed to this degradation that have qualitatively modeled. Observed melt down of the Al layer revealed by the formation of Al/Si eutectic could be the result of hot spots due to spikes in source resistance. Ó 2010 Elsevier Ltd. All rights reserved.
1. Introduction Because on-board electrical functions are multiplying in modern automobiles the number of integrated silicon switches and the electrical load they are submitted to keep increasing too. Some electrical functions (external lighting, ABS . . . ) are critical for safety and therefore demand a perfect reliability. Implementing new switches implies to acquire a good knowledge of their reliability as well as their mode of ageing [1]. Many different processes can cause power device ageing because there are many different types of components with various specifications [2–5]. The most important failure mode in the previous generation devices was related to the drain of the power chip. Delamination appeared at the die attach solder between the silicon substrate and the copper heatsink and isolated the drain from the source [6]. This delamination was triggered by the large mismatch between the thermal expansion coefficients of copper and silicon and the propagation of fatigue cracks in the solder [7]. In this work, we have studied several Freescale Semiconductor components based on the most recent technology [2]. The component structure was optimized by a new design on the leadframe in order to decrease the die attach delamination. These so-called ‘‘smart power” switches are composed of a MOSFET power device associated with a control chip both mounted on a single frame. The control die is able to detect errors and monitor the electric fluctuations of the
* Corresponding author. Tel.: +33 562257831; fax: +33 562257999. E-mail address: [email protected] (D. Martineau). 0026-2714/$ - see front matter Ó 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2010.07.065
power unit. They are used to command the on/off states of light bulbs for automobiles. The MOSFET power device contains four areas with 15 mX drain-source resistance (Rdson) at 25 °C driven independently by the control chip [8]. Accelerated electrical fatigue tests were performed to assess the devices robustness beyond the operating limits: cyclic electrical pulses with loads of about twice the nominal value were injected in the power die. The ultimate lifetime in extreme conditions is then determined and followed by a multi-scale structural analysis of the devices at various ageing states. In this new generation of device, the most significant failures occur in the source region of the MOS that is the top metal and the wire bondings [9–11]. This paper provides detailed evidences of the ageing modes of this region and proposes a sequence of physical processes that may lead to the structural changes observed in the source metal and the subsequent increase in the switch resistance. 2. Experimental procedure Devices to be tested are first inspected by X-ray analysis to observe potential voids. Transmitted (SAT) and regular (SAM) acoustic microscopy were also performed to evaluate potential defects and initial delamination on the top and beneath the power die. Batches of 10 coupons carrying these devices were then electrically tested in two similar and thermally regulated electrical benches. One of the most harmful tests consisted in trains of 90 A square electrical pulses of 200 ms followed by 9.8 s pause in
D. Martineau et al. / Microelectronics Reliability 50 (2010) 1768–1772
Fig. 1. Acoustic microscopy and X-ray images of an aged device. Delaminations are observed by SAM at the mold (a) and by SAT at the die attach (b). The control and power die are indicated by doted lines in (b). Red zones in (a) correspond to delamination area between the mold and the power die and black zones in (b) correspond to delaminated area between the power die and the leadframe. In the Xray image (c) the white arrow points to a void in the solder between the power die and the leadframe. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)
a 85 °C atmosphere. The current surge triggered an overload protection in the control chip that turned off the MOS after about 6 ms. Devices were tested by batches of 10. The condition of five broken down components was chosen as the device lifetime for this electrical test. A second batch of 10 devices was then tested in the same condition and five devices were stopped at one third of the lifetime while the five others were run up to 2/3rd of the lifetime. In some tests (see Fig. 2 for instance), tests were carried out much further than the determined lifetime to explore the evolution of the device resistivity. The Rdson was measured by the control die and four-probe resistance measurements of the metal source were performed after the device mold compound was removed. Stressed devices were re-examined by X-ray, SAM and SAT to check for a potential evolution of the component structures. We mainly focused on the active MOS area: Al wires and metallization, silicon substrate and polysilicon spacers. Scanning Electron Microscopy (SEM) and Focused Ion Beam (FIB) observations were also carried out on the metallization and Al wires after the removal of the mold compound by chemical etching. The final step was to inspect the active MOS area using Transmission Electron Microscopy (TEM). In parallel, finite element (FE) calculations using COMSOLÒ Multiphysics software were run to simulate and map the temperature increases inside the device during an electrical pulse. 3. Results SAM, SAT and X-ray results were compared before and after electrical ageing. SAM allowed us to investigate both the mold compound/die and the leadframe delamination. SAT addressed the die attach delamination while the solder voids between the leadframe and the power die were inspected with X-rays. Contrary to the previous generation of this kind of component, no significant delamination was observed (Fig. 1a and b) [6]. This shows a better ability of this new generation to maintain a constant evacuation of
Fig. 2. Rdson measurements of different aged devices. A 20% increase was observed after 250 kcycles.
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Fig. 3. Probe needles resistance measurements on different aged metallizations. The initial resistance of the source metal was multiplied by a factor of 10 for the most aged devices.
Fig. 4. SEM images of Al metallization. Before tests (a) and after a 90 A square electrical pulse during 250,000 cycles at 85 °C (b). White arrows show some emerging cracks in the metallization layer.
heat between the silicon and the copper leadframe or a better ability to the solder to resist crack propagation. As in the previous generation, the initial voids at the interface between the power die and the leadframe did not show significant growth (Fig. 1c). An increase of Rdson resistance by about 20% was observed on the most aged devices (Fig. 2). As illustrated in Fig. 1, this increase was not a result of the delamination in the drain region and we focused our study on the source region: Al metallization and Al wires. Electrical measurements were realized by probe needles on the metallization and an increase of the resistance of this Al metallization was identified (Fig. 3). These observations confirmed that the ageing of the metallization is important in the Rdson increase. SEM observations of the Al metallization revealed an important degradation. Fig. 4a represents the surface of the metallization before testing and (b) after 250 kcycles. In (a) square structures correspond to the initial transistor cells viewed from above. The bumped aspect is due to the conformation of the deposited Al layer to the polysilicon and oxide motive (visible in Fig. 5). In (b) the metallization underwent a complete degradation with a large number of surface cracks. The reason for the generation of these cracks will be discussed later. To further analyze these surface cracks, we also performed ion milling of the metallization with a Focused Ion Beam (FIB). Ionic images were taken across the thickness of the metallization to observe the Al layer microstructure. Channeling contrast renders possible the identification of single Al grains with different crystallographic orientations (Fig. 5). The initial metallization is composed of columnar Al grains. Their shape roughly consisted in 10 lm high cylinders with about 3 lm of diameter (Fig. 5a). Nanometer-size black dots are probably Si precipitates (the Al metallization contains 1% Si in weight that is not soluble at RT). Fig. 5b–d correspond to devices that underwent 45,000, 90,000 and 250,000 cycles. Two phenomena are happening in parallel. First, the initial columnar grains transform into smaller grains after 45 kcycles (Fig. 5b) and 90 kcycles (Fig 5c). Grain sizes varied from
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Fig. 5. Ionic images taken through the metallization thickness. The Al columnar grains in (a) correspond to a device before test. The smaller grains in (b)–(d) correspond to a stressed device after 45,000, 90,000 and 250,000 cycles of 90 A electrical pulses, respectively. White arrows point to intergranular cracks in the metallization layer.
1 lm to 4 lm. A complete statistical analysis of grain sizes would require observations of larger areas and should be performed in the near future. On the other hand, intergranular cracks (white arrows) have clearly developed in this structure (Fig. 5b–d). These cracks propagated between the grains (Fig. 5b) parallel to the surface or from the surface down to the active area of the MOS (Fig. 5c), at the interface between Si and Al. These cracks cause a decohesion between the Al grains and if their electrical conductivity is low, their density is sufficiently high to explain the increase in metallization resistance (Fig. 2). Although not easily measurable, the local Rdson value of a transistor cell could be considerably increased because of these cracks and ultimately create a hot spot responsible for a local melting of the Al layer and a failure of the MOS, as observed in a previous study [10]. To confirm these observations, TEM preparations were also done by FIB in the aluminum metallization of different components (Fig. 6). As revealed by ionic microscopy, the initial structure of Al metallization is made of grains with a columnar shape (Fig. 6a). The diameter is about 3 lm and the height corresponds to the layer thickness. In a device stressed to 250 kcycles of 90 A electrical pulses at 85 °C, the structure of the Al metallization has changed (Fig. 6b). The columnar structure has disappeared and grains have now smaller sizes, between 1 lm and 4 lm. Some intergranular cracks appear between Al grains. Their discontinuous aspect compared to the FIB images of Fig. 5 is due to the limited foil thickness in TEM and to the fact that the TEM image is a projection of the volume. The multiplication of grains boundaries is also a potential source of resistance increase [12], but could not explain the factor 10 observed in Fig. 3. Diffusion of Al in the silicon wafer was not observed but remains highly unrealistic as no contact modification in the active area was observed in Fig. 5b–d. A decrease in the density of Si precipitates can however be noticed from Fig. 5a–d, suggesting that Si atoms may have diffused in the metallization.
Fig. 6. TEM images of the Al metallization structure. Before tests (a) and after 250 kcycles at 85 °C (b). In (a) Al grains have a columnar shape (height equivalent to the layer thickness) while they are much smaller in (b) (about 3–4 grains in the layer thickness. White arrows show some intergranular cracks.
The degradation of the Al layer is therefore characterized by two phenomena: – Intergranular cracking. – Grain size reduction. A qualitative model for the development of intergranular cracks during thermal cycling of a polycrystalline Al film can be extended from the Gao model that was initially developed to explain the stress relaxation by diffusion of ultra thin metallic films like gold and copper that do not form adhesive native oxide [13]. In this model, the stress in tension can be relieved by incorporating the surface atoms into perpendicular grain boundaries that act as fast diffusion wedges. The model was not developed for compression, but several examples show, however that diffusion along GBs is active in Al films undergoing thermal cycles despite the presence of a native oxide [14–16]. In compression (that is during heating phases), Al atoms oxidize rapidly when they emerge from the inner film through GB (Fig. 7b) they form hillocks that will not annihilate by surface diffusion. When reversing the temperature gradient (cooling), the Al layer turns tensile and this causes grain boundary grooving, that is again stabilized by oxidation of bared Al surfaces. Repeating this grooving process leads to the decohesion of grains whose boundaries have been oxidized (Fig. 7c). This qualitative model explains well the degradation of the Al surface combined with cracks propagation along the grain boundaries. On the other hand, the division of initially large columnar grains may be attributed to regular dislocation processes. In situ thermal heating experiments in the TEM on cross sectional samples [17] have demonstrated that dislocation-based plasticity operate in a range of 200–450 °C during heating and down to a few tens of °C when cooling down from 450 °C (not shown). Both experiments
D. Martineau et al. / Microelectronics Reliability 50 (2010) 1768–1772
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Fig. 7. Qualitative model for the development of intergranular cracks during thermal cycling of a polycrystalline Al film. (a) Initial state: grains are in a columnar state and the grain boundaries (GB) are perpendicular to the free surface that is covered with the Al native oxide (red layer). (b) Heating phase: Al film in compression, formation of hillocks. (c) Cooling phase: Al film in tension, cracks open (see text for details). (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)
are very different as the temperature range is much larger and the temperature gradient much lower during in situ TEM when compared to real electro-thermal fatigue (see Fig. 8). It shows, however that dislocations move easily at relatively low temperature in the Al metallization. Repeated cycles are then prone to accumulate dislocations in the Al grains and therefore create cells that will transform into grains when the added misorientations are sufficient. This classic recovery process is helped by mixed dislocation and diffusion processes such as dislocation climb. The degradation of the Al layer is thus a combined effect of accelerated diffusion at grain boundaries and division of initially large grains by dislocation-based plasticity. To have a more acute estimation of the temperature gradient and the potential hot spots inside the power die, we performed finite elements calculations with the COMSOLÒ Multiphysics software. The objective was to simulate and map the temperature increase inside the device during an electrical pulse based on previous electrical simulations [18]. For a 90 A electrical pulse lasting 5.7 ms with a metallization in its initial state, a maximum temperature of 172 °C was attained in the middle of the Al layer (Fig. 6a). As expected from the structural observations, the metallization is the hottest zone of the component, before the wire bondings and the Si substrate. The temperature gradient over the Al layer did not exceed 60 °C in the initial configuration (Fig. 8a) but reached more than 140 °C in the aged state (that is with a metallization resistance multiplied by a factor 10 – Fig. 8b). In this later case, the maximum temperature was 256 °C (Fig. 8b). The increase in metallization resistance cannot be simulated so far and was based on actual probe-needle measurements. The temperature gradient also increases between the Al layer and the Si substrate, and this promotes a stronger delamination caused by the mismatch between the thermal expansion coefficients of Al and Si. The increase in temperature of the Al layer accelerates the diffusion between aluminum grains and therefore the increase of the resistance metallization and finally an accelerated ageing of the component. A few point remain partially unclear: – The degradation seems very uniform on the surface while simulations tend to show that, when the resistance increases, the temperature rises mainly in the middle of the Al layer.
Fig. 8. Map of the temperature in one cell of the power device following a 5.7 ms and 90 A electrical pulse in a 25 °C atmosphere. The lower pads represent the Cu lead frame while the long rectangles stand for the wire bondings. The hottest zone (red) corresponds to the Al metallization located above the Si substrate. An increase in the maximum temperature going from 172 °C in (a) to 256 °C in (b) is caused by a multiplication of the Al layer resistance by 10. This resistance increase corresponds to an aged device (b) compared to an as-processed one (a). (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)
– Several cracks are observed in the vicinity of the wire bondings and their configuration remains difficult to acquire. It is for instance hard to evaluate the extension of cracks under the wire. In conclusion, simulations and experiments do converge to pinpoint the Al degradation as the main source of ageing for these components. A qualitative model for this degradation, consisting of grain refinement and intragranular diffusion of matter has been proposed. Further work is needed to quantify the physical mechanisms at work (grain boundary diffusion, dislocation-based plasticity, recovery). Acknowledgement The authors would like to thank the Regional Council of Région Midi-Pyrénées for its financial support. References [1] Muller-Friedler R, Knoblauch V. Reliability aspects of microsensors and micromechatronic actuators for automotive applications. Microelectron Reliab 2003;43(7):1085.
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