Geometry effects of small MOSFET devices

Mi.CROELECTROHICS World Abstracts Papers published in 1975-1980 which are considered to be of technical merit will be abstracted by Charles E. Jowett and published in this, and subsequent issues of MicroelectronicsJournal. Abstracts in this issue comprise papers published in 1979. They are classified under the following headings: Integrated Circuit Technology Memories Microprocessors Optoelectronics Hybrids Discrete Devices Charged Coupled Devices Materials Production and Processing Testing Applications It is the intention, in successive issues of the Journal, to bring the paper abstracts up-to-date, presenting the reader with an easy reference to many of the important papers which have been published in journals throughout the world.

1.

Integrated Circuit Technology 1.1 MOS

CMOS, present and future TOSHIO A B E Microelectron. J., 10, (4) 31, (1979). Today, Complementary Metal-Oxide-Semiconductor (CMOS) technology is recognised as one of the more important semiconductor technologies, a suituation which was not envisaged when it was first introduced. In this article, the present status and future trend of the technology and applications of CMOS LSI, will be surveyed, referring mainly to the situation in Japan. Geometry effects of small MOSFET devices E H. GAENSSLEN IBM J. Res. Develop., 23, (6) 682 (1979). The effects of diminishing MOS inversion channel length or width on device characteristics are discussed. As opposed to the geometric device size, an "electric device size" is established by normalising all dimensions on an appropriately chosen depletion layer width. It is shown how this "electric size" governs the intensity of geometry effects. DC device modeling methods are reviewed with respect to their ease of application to electrically small devices. Finally, means for reduction of geometry effects are considered.

J-K flip-flop for C-MOS integrated circuits J. L. HUERTAS, J. I. ACHA, and J. M. CARMONA Int. J. Electronics, 47, (4) p. 381 (1979). A J-K flip-flop circuit for integrated C-MOS family is described. The new device employs a simple excitation circuitry which improves the speed-power product. Results of a comparison with the conventional flip-flop are also given. 36

C-MOS picks up ground B. LEBOSS Electronics, p. 80 (20 December 1979). Low power, high noise immunity, thermal advantages draw attention as n-MOS becomes more expensive.

1.2

LSI

LSI ready to make a mark on packet-switching networks G. L. L E G E R Electronics, p. 89 (20 December 1979). New chip's link-control capabilities ease connection to terminals: Part I. Part If: LSI circuit simplifies packet-network connection G. L. L E G E R Electronics, p. 95 (20 December 1979). 48-pin chip replaces entire board and thousands of lines of software.

Drawing the lines for VLSI D. M O R A L E E

Electron. Pwr., p. 607 (September 1979). As the integrated-circuit industry enters its third decade, and the scale of integration changes from large (LSI) to very large (VLSI), the manufacturing techniques used since the ICs invention in 1959 are beginning to be replaced by more complex and very much more costly alternatives. Will this greater complexity and higher cost slow down the development of IC technology? Limit values an properties of bipolar and MOS transistors for highest integrated (VLSI) switching circuits A. M O S C H W I T Z E R Nachrichtentechnik Elektronik., 29, (10) 403 (1979) (in German) After a representation of the development of the degree of integration

MICROELECTRONICS JOURNAL Vol. 12 No. 2 © 1981 Mackintosh Publications Ltd., Luton.