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Design considerations for 25 nm MOSFET devices
Solid-State Electronics 45 (2001) 1851±1857
Technical Note
Design considerations for 25 nm MOSFET devices Samar Saha *,1 Technology Development, Philips Semiconductors, 1109 McKay Drive, San Jose, CA 95131, USA Received 7 February 2000; received in revised form 27 April 2001
Abstract This paper presents the results of a systematic theoretical investigation on scaling gate oxide thickness and the source-drain extension (SDE) junction depth to design high performance MOSFET devices with eective channel lengths near 25 nm. In order to obtain 25 nm MOSFETs, CMOS technologies with 40, 50, and 60 nm gate lengths were designed by scaling SDE junction depth to 14, 20, and 26 nm, respectively. Each technology with the target gate oxide thickness was optimized for an o-state leakage current 10 nA/lm for 25 nm devices and the device characteristics were obtained for an equivalent gate oxide thickness of 1, 1.5, and 2 nm. The results show that for a target o-state leakage current of 25 nm devices the magnitude of threshold voltage, sub-threshold slope, and drain-induced barrier lowering increases while the magnitude of drive current decreases with the increase of gate oxide thickness. On the other hand, the variation in the magnitude of threshold voltage, sub-threshold slope, drain-induced barrier lowering, and the drive current for the similar devices is insigni®cant within the range of SDE junction depth 14±26 nm. It is, also, found that the gate delay for 25 nm devices increases with the increase of SDE junction depth. This study, clearly, demonstrates the importance of scaling gate oxide thickness and the SDE junction depth below the presently reported limits to design high performance 25 nm MOSFET devices for low voltage application. Ó 2001 Elsevier Science Ltd. All rights reserved. Keywords: Sub-100 nm CMOS; MOSFET scaling; Double-halo MOSFETs; 25 nm MOSFETs; Device simulation
1. Introduction The continuous scaling of MOSFET gate dimension has generated much interest to understand the design and performance of these devices at the outer limits of presently understood scaling [1,2]. The reported simulation based studies show the feasibility of MOSFETs with eective channel lengths (Leff ) near 25 nm [1]. In the reported studies, the value of gate length, Lg was scaled without a proportionate scaling of gate oxide thickness (TOX ) due to the constraints imposed by direct tunneling gate leakage current (Ig ) for silicon-dioxide (SiO2 ) di-
*
Corresponding address: 286 Aspenridge Drive, Milpitas, CA 95035, USA. Tel.: +1-408-474-5648; fax: +1-408-922-5393. E-mail address: [email protected] (S. Saha). 1 Present address: Silicon Storage Technology Inc., 1171 Sonora Court, Sunnyvale, CA 94086, USA.
electric. In order to design 25 nm MOSFETs with a tolerable limit of Ig 1 A/cm2 , the scaling limit for TOX is P 1:5 nm, or, the equivalent TOX including the quantum mechanical (QM) and polysilicon gate depletion eects, TOX eff is P 2 nm [3,4]. On the other hand, the conventional scaling of MOSFET devices requires a reduction in TOX nearly in proportion to the reduction in Lg to improve device performance. The required value of TOX below the presently reported constraint is achievable due to the progress in the development of high-K dielectric material and gate engineering [5]. A high-K material as a gate oxide oers a feasibility to use thicker TOX 2 nm while maintaining a higher gate capacitance equivalent to that of an ultra-thin SiO2 material with TOX eff 2 nm. Therefore, it is important to assess the performance of 25 nm MOSFETs with TOX eff 6 2 nm. Again, the reported studies [6,7] predict the limit of source-drain extension (SDE) junction depth, Xj P 30 nm and consequently the value of gate length, Lg P 60 nm
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to achieve the ultimate 25 nm MOSFETs. Since the capacitance of MOSFETs decreases as Lg and the gate area decrease, the speed of the devices increases with decreasing Xj . Therefore, it is, also, critical to evaluate the device performance for Lg 6 60 nm technologies with Leff 25 nm obtained by scaling Xj below the presently understood limit. The objective of this study is to assess the performance of 25 nm MOSFET devices operating at a supply voltage, jVDD j 6 1 V and establish the requirements for scaling TOX and Xj . In order to achieve this goal, we have designed CMOS technologies with Lg 40, 50, and 60 nm using Xj 14, 20, and 26 nm, respectively. Each technology was optimized to oer the same target ostate leakage current (Ioff ) for each value of TOX eff 1, 1.5, and 2 nm. For each technology, the device characteristics were simulated to show the importance of an appropriate scaling of TOX , Xj , and hence Lg to achieve high performance 25 nm MOSFETs for low power application. The results are obtained based on device simulation using a hydrodynamic model for semiconductors and an analytical QM model [8].
2. Device architecture The idealized bulk MOSFET test structure for device simulation consists of an n+/p+ polysilicon gate, a gate oxide, a vertically and laterally non-uniform channel doping pro®le [1], shallow n+/p+ SDE, deep n+/p+ source-drain (DSD) regions, and halo doping pro®les around SDE regions as shown in Fig. 1. A super-steep retrograde (SSR) doping pro®le with a low impurity concentration at the silicon (Si)/SiO2 interface and a higher peak concentration at a ®nite depth below the interface was used to provide the non-uniform vertical channel pro®le [9]. The SSR pro®le was optimized to achieve a target threshold voltage (Vth ) for the long channel devices. SSR pro®les, also, provide superior Vth control due to dopant ¯uctuation [9]. The non-uniform lateral channel doping pro®le was formed by halo implants during drain-pro®le engineer-
Fig. 1. An idealized MOSFET device structure showing the basic technology elements for device design.
ing [7]. A heavily doped shallow implant and a lightly doped deep implant were used to form the halo regions and the peak doping concentrations were optimized to control SCE due to SDE and DSD regions, respectively. The shallow halo doping pro®le was implanted after the gate de®nition [6] with the peak concentration immediately below Xj . Then about a 2 nm wide oset spacer was used to implant the deep halo and the SDE pro®les. Since the depth of the shallow halo is Xj , SDE regions are encroached by about 2 nm with the halo doping near the Si/SiO2 interface within the channel. Thus, the shallow doping pro®les only enhances the channel doping by about 4 nm of Leff 25 nm near the Si/SiO2 interface. On the other hand, the deep halo doping pro®les with depth DSD junction depth diuses laterally into the channel region to enhance the channel doping at a ®nite depth below the Si/SiO2 interface. Thus, the combination of double-halo pro®les provides the non-uniform lateral channel doping while maintaining a lower channel doping concentration near the surface due to SSR channel doping pro®le. The halo doping pro®les were optimized to achieve a target value of Ioff for the nominal devices of the target technology. The source-drain regions were optimized to achieve an improved device behavior and the peak impurity concentrations for SDE and DSD pro®les were 2:5 1020 cm 3 and 3:7 1020 cm 3 , respectively [7]. The applied voltages to the source, drain, gate, and the body are VS , VD , VG , and VB , respectively. In order to study the performance of 25 nm MOSFETs, CMOS technologies with Lg 40, 50, and 60 nm were designed using Xj 14, 20, and 26 nm, respectively. For each technology, MOSFET device structures were generated with TOX eff 1, 1.5, and 2 nm and SSR channel pro®les were optimized to achieve Vth 0:23 V for long channel devices. For each target TOX eff, each technology was optimized to achieve Ioff 10 nA/lm at jVDD j 1 V for the nominal 25 nm devices.
3. Simulation procedure In deep sub-micron devices, the local carrier heating and the non-local transport phenomena in¯uence the modeling of spatial carrier distributions and hence the terminal currents. Therefore, a predictive modeling of the DC terminal behavior of deep sub-micron devices must include balance equations for electron density, momentum, and energy. Again, the reported data show that the inversion layer quantization causes an increase of Vth by about 100 mV for a channel doping concentration of about 1 1018 cm 3 [9]. Therefore, it is, also, crucial to use QM model for an accurate modeling of deep sub-100 nm MOSFETs. In this study, the full energy balance solution [8] with an analytical QM model
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[10] was used for device simulation. For the simplicity of theoretical analysis, it is assumed that the average channel doping concentration in the depletion region of the non-uniform channel pro®le models the eective potential for QM calculation [9]. The energy relaxation time used for hydrodynamic simulation was 0.2 ps. The Fermi±Dirac statistics with incomplete ionization of dopant atoms were used to determine the active carrier density within the simulation structures. A combination of uncoupled and coupled solution technique was used for simulation of devices at T 300°K, and the temperature to compute the carrier concentration was obtained by using the carrier temperature calculated by hydrodynamic solution (T Telectron ). In order to perform an accurate device analysis, the material parameters for numerical device simulation were extracted from the measured data [7,9,11]. The bias condition for device simulation was VS 0 VB . First of all, the basic technology elements for each technology with each TOX eff were optimized to achieve Vth 0:23 V for long channel devices, and Ioff 10 nA/lm at VDD 1 V for 25 nm devices. For each technology, the device characteristics were simulated as a function of TOX eff. From the simulation data the magnitude of Vth , sub-threshold slope (S), draininduced barrier lowering (DIBL), drive current (IDSAT ), and gate delay (s) were extracted for each technology as a function of TOX eff. Finally, the simulation results were compared to show the importance of scaling TOX , Xj , and hence Lg below the presently reported limits in achieving high performance 25 nm MOSFETs.
4. Results and discussions The procedure outlined in Sections 2 and 3 was used to simulate the device characteristics for 40, 50, and 60 nm CMOS technologies with corresponding Xj 14, 20, and 26 nm, respectively as a function of TOX eff. The device characteristics such as (i) IDS vs VGS at jVDS j 0:05 and 1 V, (ii) IDS vs VDS at jVGS j 0:4, 0.6, 0.8, and 1 V, and (iii) capacitance vs voltage were simulated for each technology as a function TOX eff. The simulation data show the importance of scaling TOX and Xj for high performance 25 nm devices. 4.1. Importance of scaling TOX for device performance Fig. 2(a)±(c) shows Vth vs Leff plots as a function of TOX eff for both nMOSFET and pMOSFET devices of 40, 50, and 60 nm technologies optimized to provide jIoff j 10 nA/lm at jVDD j 1 V for 25 nm devices. Here, jVth j VGS at IDS 0:1 lA) (W =Leff ). It is seen from Fig. 2 that for TOX eff 2 nm, all the devices of 40, 50, and 60 nm technologies show a strong increase in
Fig. 2. Vth vs Leff as a function of TOX eff for the optimized technologies with (a) Lg 40 nm, (b) 50 nm, and (c) 60 nm.
jVth j with decreasing Leff , referred to as the reverse short channel eect (RSCE). However, the strength of RSCE decreases as TOX eff decreases and for TOX eff 1 nm
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all the technologies in Fig. 2 show an excellent short channel eect (SCE), that is, jVth j constant for 15 nm 6 Leff 6 40 nm. Fig. 2(a)±(c), also, shows that the magnitude of Vth increases with the increase of TOX eff and for the devices with Leff 25 nm, jVth j P 0:4 V at TOX eff 2 nm. Thus, scaling TOX eff < 2 nm is critical to maintain low jVth j 0:25 V and operate 25 nm MOSFETs at VDD 6 1 V. Fig. 3(a)±(c) shows jIoff j vs jIDSAT j plots as a function of TOX eff for both nMOSFET and pMOSFET devices of the optimized 40, 50, and 60 nm technologies. In Fig. 3(a)±(c), the value of jIoff j 10 nA/lm corresponds to Leff 25 nm devices. Fig. 3(a)±(c) shows that for a target value of jIoff j P 2 nA/lm, a thinner TOX (thinner) device oers a higher value of jIDSAT j compared to a thicker TOX (thicker) device. The higher current driving capability of a thinner device is due to its lower value of jVth j compared to a thicker device as shown in Fig. 2(a)± (c). Thus, scaling TOX eff < 2 nm is critical to improve the current drivability of 25 nm MOSFETs. The simulation results show a superb device characteristics for the optimized 40, 50, and 60 nm technologies. Figs. 4±6 show the device characteristics for 25 nm MOSFETs of the optimized 50 nm technology. Figs. 4(a)±6(a) show jIDS j vs VGS characteristics at jVDS j 0:05 and 1 V for 25 nm devices of the optimized 50 nm technology while Figs. 4(b)±6(b) show the family of curves. It is obvious from Figs. 4(a)±6(a) that for a certain value of IDS in the sub-threshold region, the magnitude of DIBL VGS at VDS 0:05 V VGS at VDS 1 V increases with the increase of TOX eff for both nMOSFET and pMOSFET devices. The increase in DIBL with the increase in TOX eff is due to the fact that to maintain a constant value of Ioff , the value of eective channel doping concentration (NSUB ) for the thicker devices is less than that of the thinner devices of the same technology. It is, also, seen from Figs. 4(a)±6(a) that the value of S increases with the increase in the value of TOX eff for both nMOSFET and pMOSFET devices. Similar characteristics are, also, observed for 25 nm devices of 40 and 60 nm technologies. This behavior of S can be quantitatively described using the simpli®ed expression [9]: S 60 mV=decade 1 CD =COX :
1
Here, CD and COX are the depletion and the gate capacitance, respectively. At the biasing condition VS VB 0 [9]: p CD qeSi NSUB =2wS ; 2 COX eOX =TOX :
3
In Eqs. (2) and (3), eSi and eOX are the dielectric constants of Si and SiO2 , respectively, q is the electronic
Fig. 3. Ioff vs IDSAT as a function of TOX eff for the optimized technologies with (a) Lg 40 nm, (b) 50 nm, and (c) 60 nm. IDSAT is obtained at jVGS j jVDS j 1 V while Ioff is extracted at jVDS j 1 V and VGS 0. For all data VBS 0.
charge, and wS is the surface potential near the inversion region of the channel. In sub-threshold region, wS is given by [9]:
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Fig. 4. Simulated device characteristics for the target 50 nm technology with Leff 25 nm and TOX eff 1 nm. (a) IDS vs VGS and (b) IDS vs VDS .
Fig. 5. Simulated device characteristics for the target 50 nm technology with Leff 25 nm and TOX eff 1:5 nm. (a) IDS vs VGS and (b) IDS vs VDS .
wS 1:5 kT =q ln NSUB =ni ;
TOX eff 2 nm. This value of S is too high for a faster switching of 25 nm devices. Thus, scaling TOX eff < 2 nm is critical to improve sub-threshold swing and DIBL for 25 nm MOSFETs.
4
where k is the Boltzman constant, and ni is the intrinsic carrier concentration at the ambient temperature T. Substituting Eqs. (2)±(4) in Eq. (1), it can be shown that p S 60 mV=decade 1 aTOX NSUB = ln NSUB =ni ; 5 where p a q2 eSi =3kT e2OX :
6
Eq. (5) shows that the variation in S is dominated by the variation in TOX . Though the value of NSUB for a target technology with a target Ioff is lower for the thicker devices, the value of TOX dominates over the value of NSUB . As a result, S increases with the increase of TOX as shown in Figs. 4(a)±6(a). From Fig. 6(a), it is found that the value of S 98 for the devices with
4.2. Importance of scaling Xj for device performance In order to show the importance of scaling Xj < 30, 40, 50, and 60 nm CMOS technologies were designed and optimized using Xj 14, 20, and 26 nm, respectively. The simulation results do not show a signi®cant degradation of device performance for the devices with shallower Xj . Comparing Vth vs Leff plots in Fig. 2 for technologies with dierent Xj , it is seen that Vth increase with the decrease of Xj is insigni®cant. The minor increase in Vth with the decrease in Xj can be attributed to the reduction in channel charge sharing with SDE regions as Xj decreases. Since the variation in Vth is insigni®cant within the range of Xj used in this study, the
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Fig. 7. IDSAT vs Xj as a function of TOX eff for 25 nm devices optimized for jIoff j 10 nA/lm at jVDD j 1 V and VGS 0 VBS . IDSAT is obtained at jVGS j jVDS j 1 V and VBS 0.
Fig. 6. Simulated device characteristics for the target 50 nm technology with Leff 25 nm and TOX eff 2 nm. (a) IDS vs VGS and (b) IDS vs VDS .
drive current degradation for shallower devices is, also, found to be insigni®cant. Fig. 7 shows IDSAT vs Xj for 25 nm devices as a function of TOX eff. It is observed from Fig. 7 that the degradation in IDSAT for 25 nm devices with TOX eff 2 nm is >30% compared to the devices with TOX eff 1 nm. And, the degradation in IDSAT for Xj 14 nm devices is <7% compared to the devices with Xj 26 nm. Similarly, no signi®cant variation in S and DIBL were observed for the shallower Xj 14 nm devices compared to the devices with Xj 26 nm. Thus, a shallower Xj does not degrade the device performance signi®cantly. On the contrary, this investigation shows that a shallower Xj 14 nm allows to scale Lg 40 nm that decreases gate area capacitance resulting in a higher device speed. Fig. 8 shows the percentage increase in the inverter delay, Ds vs Xj for 25 nm devices of dierent technolo-
Fig. 8. The incremental gate delay vs Xj as a function of TOX eff for 25 nm devices. The incremental delay of a device is calculated with respect to the devices with Xj 14 nm corresponding to Lg 40 nm.
gies with reference to the technology with Xj 14 nm and Lg 40 nm. Here, s represents the gate delay of a device. It is seen from Fig. 8 that in comparison to 40 nm technology with Xj 14 nm, the increase in gate delay is 12% for Lg 50 nm with Xj 20 nm and is 30% for Lg 60 nm with Xj 26 nm technologies. Thus, the speed of 25 nm devices increases tremendously with an aggressive scaling of Xj and Lg . However, within the range of this study it is found that a CMOS technology with Lg 50 nm and Xj 20 nm is essential to substantially reduce the gate delay for 25 nm devices. Therefore, scaling Xj 6 20 nm is crucial to design high performance 25 nm MOSFETs.
S. Saha / Solid-State Electronics 45 (2001) 1851±1857
5. Conclusions A systematic study to understand the issues of scaling Xj and TOX to design 25 nm MOSFETs is presented. The simulation results show that the continuous scaling of TOX and Xj is critical to achieve high performance deep sub-100 nm CMOS technologies with Leff 25 nm. The results show that a thinner gate oxide signi®cantly improves the current drivability, sub-threshold swing, and DIBL for these devices. It is shown that a thinner gate oxide is required to maintain a lower target jVth j 0:25 V as well as a lower S 80 mV/decade for faster switching of 25 nm devices at a jVDD j of about 1 V. Similarly, an ultra shallow Xj is required to scale Lg and achieve a higher speed of 25 nm devices. It is found that the shallow SDE junctions required to achieve near 40 nm technologies do not reduce DC device performance such as current drivability, sub-threshold swing, and DIBL signi®cantly. On the contrary, the shallower Xj devices with 40 nm gate lengths show a tremendous improvement in device speed. Therefore, it is crucial to scale TOX and Xj continuously to design high performance deep sub-100 nm MOSFETs. This study, clearly, demonstrates the advantage of scaling gate oxide thickness and SDE junction depth for designing a 40 nm CMOS technology with a huge improvement in device speed for low power operation. More importantly, this study shows the importance of a high-K dielectric as a
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gate material in order to scale TOX in proportion to Lg and achieve the presently understood ultimate MOSFETs with Leff 25 nm.
References [1] Taur Y, Wann CH, Frank DJ. IEDM Tech Dig 1998:789. [2] Frank DJ, Laux SE, Fischetti MV. IEDM Tech Dig 1992:553. [3] Lo S-H, Buchanan DA, Taur Y, Wang W. IEEE Electron Dev Lett 1997;EDL-18:209. [4] Saha S, Srinivasan G, Rezvani GA, Farr M. Mater Res Soc Symp Proc 1999;567:275. [5] Park D, King Y, Lu Q, King TJ, Hu C, Kalnitsky A, Tay S-P, Cheng CC. IEEE Electron Dev Lett 1998;EDL-19: 441. [6] Thompson S, Packan P, Ghani T, Stettler M, Alavi M, Post I, Tyagi S, Ahmed S, Yang S, Bohr M. Proc Symp VLSI Tech 1998:132. [7] Saha S. Proc SPIE 1999;3881:195. [8] TMA MEDICI, Version 1999.4, Avant! Corporation, Fremont, CA, 1999. [9] Saha S. Solid-State Electron 1998;42:1985. [10] van Dort MJ, Woerlee PH, Walker AJ. Solid-State Electron 1994;37:411. [11] Saha S. Proceedings of Semiconductor Technology CAD Workshop and Exhibition, vol. 2. Hsinchu, Taiwan, 1999. p. 6-1.
Technical Note
Design considerations for 25 nm MOSFET devices Samar Saha *,1 Technology Development, Philips Semiconductors, 1109 McKay Drive, San Jose, CA 95131, USA Received 7 February 2000; received in revised form 27 April 2001
Abstract This paper presents the results of a systematic theoretical investigation on scaling gate oxide thickness and the source-drain extension (SDE) junction depth to design high performance MOSFET devices with eective channel lengths near 25 nm. In order to obtain 25 nm MOSFETs, CMOS technologies with 40, 50, and 60 nm gate lengths were designed by scaling SDE junction depth to 14, 20, and 26 nm, respectively. Each technology with the target gate oxide thickness was optimized for an o-state leakage current 10 nA/lm for 25 nm devices and the device characteristics were obtained for an equivalent gate oxide thickness of 1, 1.5, and 2 nm. The results show that for a target o-state leakage current of 25 nm devices the magnitude of threshold voltage, sub-threshold slope, and drain-induced barrier lowering increases while the magnitude of drive current decreases with the increase of gate oxide thickness. On the other hand, the variation in the magnitude of threshold voltage, sub-threshold slope, drain-induced barrier lowering, and the drive current for the similar devices is insigni®cant within the range of SDE junction depth 14±26 nm. It is, also, found that the gate delay for 25 nm devices increases with the increase of SDE junction depth. This study, clearly, demonstrates the importance of scaling gate oxide thickness and the SDE junction depth below the presently reported limits to design high performance 25 nm MOSFET devices for low voltage application. Ó 2001 Elsevier Science Ltd. All rights reserved. Keywords: Sub-100 nm CMOS; MOSFET scaling; Double-halo MOSFETs; 25 nm MOSFETs; Device simulation
1. Introduction The continuous scaling of MOSFET gate dimension has generated much interest to understand the design and performance of these devices at the outer limits of presently understood scaling [1,2]. The reported simulation based studies show the feasibility of MOSFETs with eective channel lengths (Leff ) near 25 nm [1]. In the reported studies, the value of gate length, Lg was scaled without a proportionate scaling of gate oxide thickness (TOX ) due to the constraints imposed by direct tunneling gate leakage current (Ig ) for silicon-dioxide (SiO2 ) di-
*
Corresponding address: 286 Aspenridge Drive, Milpitas, CA 95035, USA. Tel.: +1-408-474-5648; fax: +1-408-922-5393. E-mail address: [email protected] (S. Saha). 1 Present address: Silicon Storage Technology Inc., 1171 Sonora Court, Sunnyvale, CA 94086, USA.
electric. In order to design 25 nm MOSFETs with a tolerable limit of Ig 1 A/cm2 , the scaling limit for TOX is P 1:5 nm, or, the equivalent TOX including the quantum mechanical (QM) and polysilicon gate depletion eects, TOX eff is P 2 nm [3,4]. On the other hand, the conventional scaling of MOSFET devices requires a reduction in TOX nearly in proportion to the reduction in Lg to improve device performance. The required value of TOX below the presently reported constraint is achievable due to the progress in the development of high-K dielectric material and gate engineering [5]. A high-K material as a gate oxide oers a feasibility to use thicker TOX 2 nm while maintaining a higher gate capacitance equivalent to that of an ultra-thin SiO2 material with TOX eff 2 nm. Therefore, it is important to assess the performance of 25 nm MOSFETs with TOX eff 6 2 nm. Again, the reported studies [6,7] predict the limit of source-drain extension (SDE) junction depth, Xj P 30 nm and consequently the value of gate length, Lg P 60 nm
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to achieve the ultimate 25 nm MOSFETs. Since the capacitance of MOSFETs decreases as Lg and the gate area decrease, the speed of the devices increases with decreasing Xj . Therefore, it is, also, critical to evaluate the device performance for Lg 6 60 nm technologies with Leff 25 nm obtained by scaling Xj below the presently understood limit. The objective of this study is to assess the performance of 25 nm MOSFET devices operating at a supply voltage, jVDD j 6 1 V and establish the requirements for scaling TOX and Xj . In order to achieve this goal, we have designed CMOS technologies with Lg 40, 50, and 60 nm using Xj 14, 20, and 26 nm, respectively. Each technology was optimized to oer the same target ostate leakage current (Ioff ) for each value of TOX eff 1, 1.5, and 2 nm. For each technology, the device characteristics were simulated to show the importance of an appropriate scaling of TOX , Xj , and hence Lg to achieve high performance 25 nm MOSFETs for low power application. The results are obtained based on device simulation using a hydrodynamic model for semiconductors and an analytical QM model [8].
2. Device architecture The idealized bulk MOSFET test structure for device simulation consists of an n+/p+ polysilicon gate, a gate oxide, a vertically and laterally non-uniform channel doping pro®le [1], shallow n+/p+ SDE, deep n+/p+ source-drain (DSD) regions, and halo doping pro®les around SDE regions as shown in Fig. 1. A super-steep retrograde (SSR) doping pro®le with a low impurity concentration at the silicon (Si)/SiO2 interface and a higher peak concentration at a ®nite depth below the interface was used to provide the non-uniform vertical channel pro®le [9]. The SSR pro®le was optimized to achieve a target threshold voltage (Vth ) for the long channel devices. SSR pro®les, also, provide superior Vth control due to dopant ¯uctuation [9]. The non-uniform lateral channel doping pro®le was formed by halo implants during drain-pro®le engineer-
Fig. 1. An idealized MOSFET device structure showing the basic technology elements for device design.
ing [7]. A heavily doped shallow implant and a lightly doped deep implant were used to form the halo regions and the peak doping concentrations were optimized to control SCE due to SDE and DSD regions, respectively. The shallow halo doping pro®le was implanted after the gate de®nition [6] with the peak concentration immediately below Xj . Then about a 2 nm wide oset spacer was used to implant the deep halo and the SDE pro®les. Since the depth of the shallow halo is Xj , SDE regions are encroached by about 2 nm with the halo doping near the Si/SiO2 interface within the channel. Thus, the shallow doping pro®les only enhances the channel doping by about 4 nm of Leff 25 nm near the Si/SiO2 interface. On the other hand, the deep halo doping pro®les with depth DSD junction depth diuses laterally into the channel region to enhance the channel doping at a ®nite depth below the Si/SiO2 interface. Thus, the combination of double-halo pro®les provides the non-uniform lateral channel doping while maintaining a lower channel doping concentration near the surface due to SSR channel doping pro®le. The halo doping pro®les were optimized to achieve a target value of Ioff for the nominal devices of the target technology. The source-drain regions were optimized to achieve an improved device behavior and the peak impurity concentrations for SDE and DSD pro®les were 2:5 1020 cm 3 and 3:7 1020 cm 3 , respectively [7]. The applied voltages to the source, drain, gate, and the body are VS , VD , VG , and VB , respectively. In order to study the performance of 25 nm MOSFETs, CMOS technologies with Lg 40, 50, and 60 nm were designed using Xj 14, 20, and 26 nm, respectively. For each technology, MOSFET device structures were generated with TOX eff 1, 1.5, and 2 nm and SSR channel pro®les were optimized to achieve Vth 0:23 V for long channel devices. For each target TOX eff, each technology was optimized to achieve Ioff 10 nA/lm at jVDD j 1 V for the nominal 25 nm devices.
3. Simulation procedure In deep sub-micron devices, the local carrier heating and the non-local transport phenomena in¯uence the modeling of spatial carrier distributions and hence the terminal currents. Therefore, a predictive modeling of the DC terminal behavior of deep sub-micron devices must include balance equations for electron density, momentum, and energy. Again, the reported data show that the inversion layer quantization causes an increase of Vth by about 100 mV for a channel doping concentration of about 1 1018 cm 3 [9]. Therefore, it is, also, crucial to use QM model for an accurate modeling of deep sub-100 nm MOSFETs. In this study, the full energy balance solution [8] with an analytical QM model
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[10] was used for device simulation. For the simplicity of theoretical analysis, it is assumed that the average channel doping concentration in the depletion region of the non-uniform channel pro®le models the eective potential for QM calculation [9]. The energy relaxation time used for hydrodynamic simulation was 0.2 ps. The Fermi±Dirac statistics with incomplete ionization of dopant atoms were used to determine the active carrier density within the simulation structures. A combination of uncoupled and coupled solution technique was used for simulation of devices at T 300°K, and the temperature to compute the carrier concentration was obtained by using the carrier temperature calculated by hydrodynamic solution (T Telectron ). In order to perform an accurate device analysis, the material parameters for numerical device simulation were extracted from the measured data [7,9,11]. The bias condition for device simulation was VS 0 VB . First of all, the basic technology elements for each technology with each TOX eff were optimized to achieve Vth 0:23 V for long channel devices, and Ioff 10 nA/lm at VDD 1 V for 25 nm devices. For each technology, the device characteristics were simulated as a function of TOX eff. From the simulation data the magnitude of Vth , sub-threshold slope (S), draininduced barrier lowering (DIBL), drive current (IDSAT ), and gate delay (s) were extracted for each technology as a function of TOX eff. Finally, the simulation results were compared to show the importance of scaling TOX , Xj , and hence Lg below the presently reported limits in achieving high performance 25 nm MOSFETs.
4. Results and discussions The procedure outlined in Sections 2 and 3 was used to simulate the device characteristics for 40, 50, and 60 nm CMOS technologies with corresponding Xj 14, 20, and 26 nm, respectively as a function of TOX eff. The device characteristics such as (i) IDS vs VGS at jVDS j 0:05 and 1 V, (ii) IDS vs VDS at jVGS j 0:4, 0.6, 0.8, and 1 V, and (iii) capacitance vs voltage were simulated for each technology as a function TOX eff. The simulation data show the importance of scaling TOX and Xj for high performance 25 nm devices. 4.1. Importance of scaling TOX for device performance Fig. 2(a)±(c) shows Vth vs Leff plots as a function of TOX eff for both nMOSFET and pMOSFET devices of 40, 50, and 60 nm technologies optimized to provide jIoff j 10 nA/lm at jVDD j 1 V for 25 nm devices. Here, jVth j VGS at IDS 0:1 lA) (W =Leff ). It is seen from Fig. 2 that for TOX eff 2 nm, all the devices of 40, 50, and 60 nm technologies show a strong increase in
Fig. 2. Vth vs Leff as a function of TOX eff for the optimized technologies with (a) Lg 40 nm, (b) 50 nm, and (c) 60 nm.
jVth j with decreasing Leff , referred to as the reverse short channel eect (RSCE). However, the strength of RSCE decreases as TOX eff decreases and for TOX eff 1 nm
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all the technologies in Fig. 2 show an excellent short channel eect (SCE), that is, jVth j constant for 15 nm 6 Leff 6 40 nm. Fig. 2(a)±(c), also, shows that the magnitude of Vth increases with the increase of TOX eff and for the devices with Leff 25 nm, jVth j P 0:4 V at TOX eff 2 nm. Thus, scaling TOX eff < 2 nm is critical to maintain low jVth j 0:25 V and operate 25 nm MOSFETs at VDD 6 1 V. Fig. 3(a)±(c) shows jIoff j vs jIDSAT j plots as a function of TOX eff for both nMOSFET and pMOSFET devices of the optimized 40, 50, and 60 nm technologies. In Fig. 3(a)±(c), the value of jIoff j 10 nA/lm corresponds to Leff 25 nm devices. Fig. 3(a)±(c) shows that for a target value of jIoff j P 2 nA/lm, a thinner TOX (thinner) device oers a higher value of jIDSAT j compared to a thicker TOX (thicker) device. The higher current driving capability of a thinner device is due to its lower value of jVth j compared to a thicker device as shown in Fig. 2(a)± (c). Thus, scaling TOX eff < 2 nm is critical to improve the current drivability of 25 nm MOSFETs. The simulation results show a superb device characteristics for the optimized 40, 50, and 60 nm technologies. Figs. 4±6 show the device characteristics for 25 nm MOSFETs of the optimized 50 nm technology. Figs. 4(a)±6(a) show jIDS j vs VGS characteristics at jVDS j 0:05 and 1 V for 25 nm devices of the optimized 50 nm technology while Figs. 4(b)±6(b) show the family of curves. It is obvious from Figs. 4(a)±6(a) that for a certain value of IDS in the sub-threshold region, the magnitude of DIBL VGS at VDS 0:05 V VGS at VDS 1 V increases with the increase of TOX eff for both nMOSFET and pMOSFET devices. The increase in DIBL with the increase in TOX eff is due to the fact that to maintain a constant value of Ioff , the value of eective channel doping concentration (NSUB ) for the thicker devices is less than that of the thinner devices of the same technology. It is, also, seen from Figs. 4(a)±6(a) that the value of S increases with the increase in the value of TOX eff for both nMOSFET and pMOSFET devices. Similar characteristics are, also, observed for 25 nm devices of 40 and 60 nm technologies. This behavior of S can be quantitatively described using the simpli®ed expression [9]: S 60 mV=decade 1 CD =COX :
1
Here, CD and COX are the depletion and the gate capacitance, respectively. At the biasing condition VS VB 0 [9]: p CD qeSi NSUB =2wS ; 2 COX eOX =TOX :
3
In Eqs. (2) and (3), eSi and eOX are the dielectric constants of Si and SiO2 , respectively, q is the electronic
Fig. 3. Ioff vs IDSAT as a function of TOX eff for the optimized technologies with (a) Lg 40 nm, (b) 50 nm, and (c) 60 nm. IDSAT is obtained at jVGS j jVDS j 1 V while Ioff is extracted at jVDS j 1 V and VGS 0. For all data VBS 0.
charge, and wS is the surface potential near the inversion region of the channel. In sub-threshold region, wS is given by [9]:
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Fig. 4. Simulated device characteristics for the target 50 nm technology with Leff 25 nm and TOX eff 1 nm. (a) IDS vs VGS and (b) IDS vs VDS .
Fig. 5. Simulated device characteristics for the target 50 nm technology with Leff 25 nm and TOX eff 1:5 nm. (a) IDS vs VGS and (b) IDS vs VDS .
wS 1:5 kT =q ln NSUB =ni ;
TOX eff 2 nm. This value of S is too high for a faster switching of 25 nm devices. Thus, scaling TOX eff < 2 nm is critical to improve sub-threshold swing and DIBL for 25 nm MOSFETs.
4
where k is the Boltzman constant, and ni is the intrinsic carrier concentration at the ambient temperature T. Substituting Eqs. (2)±(4) in Eq. (1), it can be shown that p S 60 mV=decade 1 aTOX NSUB = ln NSUB =ni ; 5 where p a q2 eSi =3kT e2OX :
6
Eq. (5) shows that the variation in S is dominated by the variation in TOX . Though the value of NSUB for a target technology with a target Ioff is lower for the thicker devices, the value of TOX dominates over the value of NSUB . As a result, S increases with the increase of TOX as shown in Figs. 4(a)±6(a). From Fig. 6(a), it is found that the value of S 98 for the devices with
4.2. Importance of scaling Xj for device performance In order to show the importance of scaling Xj < 30, 40, 50, and 60 nm CMOS technologies were designed and optimized using Xj 14, 20, and 26 nm, respectively. The simulation results do not show a signi®cant degradation of device performance for the devices with shallower Xj . Comparing Vth vs Leff plots in Fig. 2 for technologies with dierent Xj , it is seen that Vth increase with the decrease of Xj is insigni®cant. The minor increase in Vth with the decrease in Xj can be attributed to the reduction in channel charge sharing with SDE regions as Xj decreases. Since the variation in Vth is insigni®cant within the range of Xj used in this study, the
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Fig. 7. IDSAT vs Xj as a function of TOX eff for 25 nm devices optimized for jIoff j 10 nA/lm at jVDD j 1 V and VGS 0 VBS . IDSAT is obtained at jVGS j jVDS j 1 V and VBS 0.
Fig. 6. Simulated device characteristics for the target 50 nm technology with Leff 25 nm and TOX eff 2 nm. (a) IDS vs VGS and (b) IDS vs VDS .
drive current degradation for shallower devices is, also, found to be insigni®cant. Fig. 7 shows IDSAT vs Xj for 25 nm devices as a function of TOX eff. It is observed from Fig. 7 that the degradation in IDSAT for 25 nm devices with TOX eff 2 nm is >30% compared to the devices with TOX eff 1 nm. And, the degradation in IDSAT for Xj 14 nm devices is <7% compared to the devices with Xj 26 nm. Similarly, no signi®cant variation in S and DIBL were observed for the shallower Xj 14 nm devices compared to the devices with Xj 26 nm. Thus, a shallower Xj does not degrade the device performance signi®cantly. On the contrary, this investigation shows that a shallower Xj 14 nm allows to scale Lg 40 nm that decreases gate area capacitance resulting in a higher device speed. Fig. 8 shows the percentage increase in the inverter delay, Ds vs Xj for 25 nm devices of dierent technolo-
Fig. 8. The incremental gate delay vs Xj as a function of TOX eff for 25 nm devices. The incremental delay of a device is calculated with respect to the devices with Xj 14 nm corresponding to Lg 40 nm.
gies with reference to the technology with Xj 14 nm and Lg 40 nm. Here, s represents the gate delay of a device. It is seen from Fig. 8 that in comparison to 40 nm technology with Xj 14 nm, the increase in gate delay is 12% for Lg 50 nm with Xj 20 nm and is 30% for Lg 60 nm with Xj 26 nm technologies. Thus, the speed of 25 nm devices increases tremendously with an aggressive scaling of Xj and Lg . However, within the range of this study it is found that a CMOS technology with Lg 50 nm and Xj 20 nm is essential to substantially reduce the gate delay for 25 nm devices. Therefore, scaling Xj 6 20 nm is crucial to design high performance 25 nm MOSFETs.
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5. Conclusions A systematic study to understand the issues of scaling Xj and TOX to design 25 nm MOSFETs is presented. The simulation results show that the continuous scaling of TOX and Xj is critical to achieve high performance deep sub-100 nm CMOS technologies with Leff 25 nm. The results show that a thinner gate oxide signi®cantly improves the current drivability, sub-threshold swing, and DIBL for these devices. It is shown that a thinner gate oxide is required to maintain a lower target jVth j 0:25 V as well as a lower S 80 mV/decade for faster switching of 25 nm devices at a jVDD j of about 1 V. Similarly, an ultra shallow Xj is required to scale Lg and achieve a higher speed of 25 nm devices. It is found that the shallow SDE junctions required to achieve near 40 nm technologies do not reduce DC device performance such as current drivability, sub-threshold swing, and DIBL signi®cantly. On the contrary, the shallower Xj devices with 40 nm gate lengths show a tremendous improvement in device speed. Therefore, it is crucial to scale TOX and Xj continuously to design high performance deep sub-100 nm MOSFETs. This study, clearly, demonstrates the advantage of scaling gate oxide thickness and SDE junction depth for designing a 40 nm CMOS technology with a huge improvement in device speed for low power operation. More importantly, this study shows the importance of a high-K dielectric as a
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gate material in order to scale TOX in proportion to Lg and achieve the presently understood ultimate MOSFETs with Leff 25 nm.
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