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Electrothermal characterization of silicon-on-glass VDMOSFETs
Microelectronics Reliability 45 (2005) 541–550 www.elsevier.com/locate/microrel
Electrothermal characterization of silicon-on-glass VDMOSFETs q N. Nenadovic´ a,*, V. Cuoco b, S.J.C.H. Theeuwen c, L.K. Nanver a, H. Schellevis a, G. Spierings c, H.F.F. Jos c, J.W. Slotboom a a b
Laboratory of ECTM, DIMES, Delft University of Technology, Feldmannweg 17, 2628 CT Delft, The Netherlands Laboratory of HiTeC, DIMES, Delft University of Technology, Feldmannweg 17, 2628 CT Delft, The Netherlands c Philips Semiconductors—RF Modules, Gerstweg 2, 6534 AE Nijmegen, The Netherlands Received 28 June 2004; received in revised form 16 August 2004 Available online 10 November 2004
Abstract Electrothermal consequences of implementing bulk-silicon RF power MOS processes in the silicon-on-glass substrate transfer technology are investigated in this paper. Fabricated silicon-on-glass vertical double-diffused MOSFETs are measured on-wafer and very large thermal resistance values are extracted for each design. The influence of the thermal resistance on RF performance is analyzed, and it is shown that strong electrothermal feedback severely lowers the power capability and strongly increases the operating temperature. A combination of low-thermal contacting and surface mounting to thermally conducting printed circuit board is shown to be very efficient in reducing the large thermal resistance. Numerical thermal simulations demonstrate that surface-mounted silicon-on-glass transistors can have lower thermal resistance than the bulk-silicon device with a wafer thickness reduced down to 100 lm. Ó 2004 Elsevier Ltd. All rights reserved.
1. Introduction Lateral double-diffused MOSFETs (LDMOSFETs) are todayÕs most advanced silicon technologies for linear radio frequency (RF) applications [1–3]. In the future, to meet the demand for very highly integrated wireless sys-
q
An earlier version of the paper was published in proceedings of 24th International conference on Microelectronics (MIEL 2004), 16–19 May 2004, NIS, Serbia and Montenegro, Vol. 1, pp. 145–148. * Corresponding author. Tel.: +31 15 2782185; fax: +31 15 2787369. E-mail address: [email protected] (N. Nenadovic´).
tems, new RF power device concepts and technologies will, however, be required [4]. We have developed and fabricated a new device called the silicon-on-glass (SOG) vertical double-diffused MOSFET (VDMOSFET) [5–7]. In this technology, a bulk-silicon LDMOS process of Philips Semiconductors for 2 GHz base-station applications is implemented in a substrate transfer silicon-on-glass technology [8]. Pure electrically these silicon-on-glass VDMOSFETs have been shown to be the first VDMOSFETs that are suitable for 2 GHz power applications [7]. Fabricated devices with a gate length of 0.8 lm and gate width of 350 lm were measured to have an fT/fmax of 6/10 GHz and a breakdown voltage approaching 100 V. These devices feature output power of 12 dBm at the 1-dB compression point, excellent linearity of IMD3 = 50 dBc and
0026-2714/$ - see front matter Ó 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2004.08.015
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N. Nenadovic´ et al. / Microelectronics Reliability 45 (2005) 541–550
IMD5 = 70 dBc, and high-power gain of Gt = 14 dB at 2 GHz. Electrothermally, however, glass is a very poor thermal conductor and it is shown here that replacing the silicon wafer by glass will very seriously increase the thermal resistance. Lowering this very high-thermal resistance becomes entirely dependent on the packaging of the devices, where the formation of a reliable and lowthermal contact resistance to the package heat sink becomes vital. This is studied in this paper by investigating the influence of the thermal resistance on the device RF performance. For this purpose we have employed the Smoothie database model for FET devices [9], which has been recently extended with electrothermal capabilities [10]. Finally, an extended thermal comparison of surface-mounted silicon-on-glass and bulk-silicon VDMOSFETs is performed. Numerical simulations are used to study the influence of the thermal conductivity of the printed circuit board (PCB), thickness of bulksilicon wafer, and other design parameters on the value of the thermal resistance.
minimizes debiasing over long drain fingers, while the second two times thicker layer to the source improves thermal conductance to thermal ground after packaging. In Fig. 2 a SEM image of a device with two copper layers is given. Successively, the drain copper interconnects are covered with a Benzo-Cyclo-Butane (BCB) layer before the individual devices are diced and soldered to thermally conducting PCB. Schematic cross-section of the surface-mounted silicon-on-glass VDMOSFET is given in Fig. 1(d). Based on the initial numerical thermal simulations it has been concluded in [7] that the surface-mounted silicon-on-glass VDMOSFETs can feature even much lower thermal resistance RTH than the corresponding bulk-silicon transistor mounted on the same copper heat sink. Thus, the wafer-level devices, schematically given in Fig. 1(c), have been measured in an isothermal (pulsed) condition to resemble performance of the surface-mounted transistors from Fig. 1(d). Results on the isothermal characterization of the first fabricated devices are presented in [7].
2. Device fabrication
3. Measurements of the thermal resistance
The silicon-on-glass VDMOS process flow is schematically presented in Fig. 1. It is divided into four parts: (a) the modified LDMOS processing on the SOI starting material, (b) the substrate transfer to glass with the backwafer low-ohmic contacting, (c) the copper electroplating of electrical and thermal interconnects on the backwafer, and (d) the surface mounting to a thermally conducting printed circuit board (PCB). The front-wafer processing defines the intrinsic device and is based on a production-line LDMOS process of Philips Semiconductors. The substrate transfer is introduced to reduce device parasitics, improve long-term reliability and enhance the quality of integrated passives. It is also a Philips production process, but is run in DIMES with several enhancements: the back-wafer is patterned with the same high-precision lithography as the front-wafer [11], and low-ohmic p- and n-type contacts are formed by implanting, laser annealing and metallizing with a sputtered 1.4lm-thick Al/Si(1%) [12]. The front-wafer source and gate bond-pads are brought to the back-wafer by the diffused vias (p+-sinkers), while the drain is directly contacted from the back-wafer. The gate p+-sinkers are isolated from the n-drain by the deep trenches etched from the back-wafer to the front-wafer oxide. To reduce self-heating, both the copper thermal interconnects and surface-mounted assembly [13,14] are introduced. First, a Ti/TiN diffusion and adhesion barrier, and a copper seed layer are sputtered on the back-wafer. This is followed by electroplating of two layers of copper as is schematically shown in Fig. 1(c). The first, approximately 5-lm-thick layer on the drain
In this section, three silicon-on-glass VDMOSFET designs are measured and compared with respect to RTH. Schematic cross-sections of the investigated transistors are given in Fig. 3. All the devices are single-drain transistors, such as the one from Fig. 2. The measured devices have a gate width Wg of 350 lm and are characterized on-wafer, i.e. before dicing and soldering. The transistors (a) and (b) differ only with respect to the back-wafer metallization. In fact, the back-wafer metal of device (a) is made of a 1.4-lm-thick Al/Si, while the transistor (b) is also metallized with a thick copper both on the drain and source. Compared to (b), the transistor (c) has a thicker top-silicon layer. With the chosen transistors the effect of the top-silicon layer and a thick, thermally floating metal interconnect on the thermal resistance can be studied. All the measurements are performed on the Cascade probing station equipped with a thermal-chuck. The measurement method used here to extract the thermal resistance is illustrated in Fig. 4, where the data measured on the device from Fig. 3(a) are shown. First, input ID-VGS characteristics are measured for a constant drain–source voltage VDS. The measurements are performed in isothermal conditions for several thermalchuck temperatures using the AgilentÕs 85124A pulsemeasurement system. The isothermal characteristics are used for extraction of the temperature coefficient of the drain current dIdTD . Successively, a non-isothermal (DC) measurement is performed for a fixed thermalchuck temperature of 25C, using an HP4156B parameter analyzer. The DC characteristic is compared to the isothermal measurements at 25C, and a temperature
N. Nenadovic´ et al. / Microelectronics Reliability 45 (2005) 541–550
(a) Front-wafer processing: field-plate gate gate source n+ p-
p++ p+sinker
~ ~
gate plug source
p- n+ n-drain
p++
p++
p+sinker
p+sinker
~5 µm
~ ~ ~500 µm
BOX
Si substrate
(b) Silicon substrate transfer to glass, back-wafer implantation, laser annealing and metallizing with sputtered Al/Si:
~ ~
~ ~ ~400 µm
glass field-plate gate gate
adhesive source
~10 µm
gate plug
p+ sinker p++
p+ sinker p++
n-drain n++ drain
source
trench
source
source
~5 µm
p+ sinker p++
gate
(c) Back-wafer copper plating and BCB deposition: ~ ~
~ ~
glass field-plate gate gate
adhesive source
BCB
n++
p++
trench
p++ Cu
gate plug source
Cu drain
Cu
BCB
source
p++ ~10 µm
Cu
source
gate
(d) Surface mounting to thermally conducting printed circuit board: ~ ~
~ ~ ~400 µm
glass field-plate gate gate
adhesive source
n-epi
BCB
source
metal
n++ Cu drain
PCB
oxide
p++
~10 µm
p++
p+ sinker p++
trench
p- n++
n++ p-
p++ p+ sinker p++ Cu
gate plug source
Cu
BCB
source
solder
p+ sinker p++
~5 µm
Cu
~10 µm
gate
polysilicon
Fig. 1. Schematic of the silicon-on-glass VDMOS process flow.
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544
DT ¼
DI D ; dI D dT
ð1Þ
where DID is the change in drain current due to selfheating. Thus, it is straightforward to extract the thermal resistance from: RTH ¼
Fig. 2. Scanning electron microscopy image of a silicon-onglass VDMOSFET seen from the back-wafer side. WG = 70 lm.
increase with respect to ambient is calculated as function of bias: ~ ~
DT DI D DI D ¼ ; ¼ dI D dI D P P I D;DC V DS dT dT
where ID,DC is the drain current measured in DC condition. The thermal resistance is dependent on bias due to the size modulation of the heat source [15], and the temperature dependence of the thermal conductivity of silicon and glass [16]. However, only a small change in RTH with bias is measured here for all the investigated devices. This is due to a weak modulation of the size of the heat source under normal operating conditions, and due to an opposite temperature dependence of the ~ ~
glass adhesive gate source
gate
gate plug source
oxide
3.5 µm drain
source
~ ~
source
gate (a)
~ ~
glass adhesive gate source
gate
gate plug source
oxide
3.5 µm Cu drain
Cu
Cu
source
~ ~
source
Cu
8 µm
gate (b)
~ ~
glass adhesive gate source
gate
gate plug source
oxide
4 µm
Cu
source
Cu drain
ð2Þ
Cu
source
Cu
8 µm
gate (c)
Fig. 3. Schematic cross-sections of the three types of devices measured and compared with respect to the thermal resistance.
N. Nenadovic´ et al. / Microelectronics Reliability 45 (2005) 541–550
IDSX
VDS=5 V
20
∆ID ID [mA]
15
ID,DC
T0=25,50,75,100OC
10
5
non-isothermal, for TAMB=25OC
VTH
isothermal
0 2
3
4
5
6
7
8
VGS [V] Fig. 4. Measured isothermal (pulsed) and non isothermal (DC) ID–VGS characteristics of a silicon-on-glass VDMOSFET such as the one shown in Fig. 3(a) with WG = 350 lm.
thermal conductivity of silicon and glass. The extracted thermal resistances are: 1200 K/W for device (a), 780 K/ W for device (b), and 660 K/W for device (c). Thus, it can be concluded that even with thermally floating heat spreaders significant reduction of RTH can be achieved. Nevertheless, even the lowest measured value of RTH is almost one order of magnitude larger than that of the comparable wafer-level bulk-silicon device, which has been measured to be only 80 K/W for a silicon wafer thickness of 120 lm. It should be noted that the thermal resistance is usually reduced by the silicon wafer thinning and furthermore by packaging, and typically a bulk-silicon device with a large gate width of for example 70 mm will have a thermal resistance as low as 1 K/W.
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Small signal S-parameters of the device from Fig. 3(b) together with DC data are collected at 2 GHz and at different temperatures, and Smoothie databases are extracted from this data. Successively, the measured single-pole RTH–CTH parallel thermal impedance network is coupled to the electrical databases, and the device RF performance is evaluated by means of two-tone load-pull electrothermal simulation performed at 2 GHz with a tone spacing of 200 kHz. The thermal cut-off frequency fTH = 1/(2pRTHCTH) was extracted from transient thermal impedance data. Both the thermal resistance and thermal capacitance are considered temperature independent. Note that the exact value of fTH, i.e. CTH, is not crucial for the analysis, since the thermal response is anyway limited to low-frequencies. Thus, neither the fundamental tone nor the higher harmonics and the IF tone significantly modulate the temperature. Therefore, only DC power influences the operating temperature. The two-tone transducer gain and third- and fifth-order intermodulation distortion versus output power are derived in class AB bias condition with a supply voltage of VDD = 26 V and quiescent current Idq of 2.12 mA, and the results are shown in Fig. 5. The simulations are repeated with different values of the thermal resistance and keeping the thermal cut-off frequency fTH 10 kHz unchanged. In the first set of calculations it is assumed that 13.6 dB power-gain is required for the application. Therefore, the bias conditions for each simulation are adjusted in order to meet this requirement. From Table 1 it appears that as the thermal resistance increases, the output power measured at the 1-dB compression point drops dramatically, although the RF power gain is unchanged and linearity
0
14.5 14
f = 2 GHz ∆f = 200 kHz
10 dB -20
From the measured isothermal and non-isothermal characteristics from Fig. 4, it is clear that self-heating reduces the transconductance gm, lowers the threshold voltage VTH and reduces the quasi-saturation current IDSX [17]. Lower gm, for example, negatively influences the cut-off frequency and maximum oscillation frequency of a device. However, for other figures of merit, such as the RF power gain, linearity and output power, the dependence on the thermal resistance is less clear, since these quantities depend on the external matching circuitry. Therefore, it is useful to study how VDMOS transistors with different thermal resistances behave in terms of RF performance. For this purpose, we have used the Smoothie electrothermal database model for FET devices.
Gain [dB]
1 dB
-40
13 12.5
-60
IMD3 [dBc]
13.5
4. RF performance as function of thermal resistance
12 -80 11.5 11 -10
-5
0
5
10
-100 15
Pout [dBm]
Fig. 5. Two-tone transducer gain and third-order intermodulation distortion versus output power for the device from Fig. 3(b), derived with the Smoothie database model. Calculations are performed in class AB bias condition (VDD = 26 V and Idq = 2.12 mA) based on the measured isothermal S-parameters and thermal single-pole network (RTH = 780 K/W, fTH = 10 kHz). WG = 350 lm.
N. Nenadovic´ et al. / Microelectronics Reliability 45 (2005) 541–550
546
Table 1 RF performance of silicon-on-glass VDMOSFETs as function of the thermal resistance
14
RTH=0,300,750,1500 K/W
P1 dB [dBm]
IMD310 dB [dBc]
Idq [mA]
Tq [°C]
0 30 100 200 300 500 750 1000 1500
13.6 13.2 11.5 10.8 10.4 10.3 10.0 9.7 9.3
45 45 45 45.5 45.8 46.5 48.0 49.0 50.0
2.00 2.00 2.05 2.06 2.07 2.09 2.12 2.15 2.20
25 26 30 36 41 52 66 90 111
Power gain Gt is kept constant to 13.6 dB for each RTH. Wg = 350 lm.
at the 10 dB back-off improved. In fact, already with a value of RTH equal to 100 K/W, the drop in the output power is larger than 2 dB compared to the situation in which the thermal resistance is negligible. The drop becomes larger than 3.5 dB for a RTH of 750 K/W. This has obvious negative consequences on the cost, since the only way to increase the output power of a transistor with large RTH would be to make it bigger. Moreover, the quiescent point temperature Tq, i.e. the temperature of the device without any RF power applied, strongly increases with RTH. It is also useful to note that behavior of IMD performance as the temperature increases (i.e. RTH increases) is regulated by the relative phases of various harmonic components. This could be better investigated with the aid of Volterra series analysis [18]. In the second set of calculations, characterization for different values of the thermal resistance is repeated but now with the quiescent current Idq kept constant at 2 mA. The thermal cut-off frequency of 10 kHz is again kept unchanged for each RTH. The results of the simulations are summarized in Table 2 and Fig. 6. Under these
Table 2 RF performance of silicon-on-glass VDMOSFETs as function of the thermal resistance RTH [K/W]
GT [dB]
P1 dB [dBm]
IMD310 dB [dBc]
Tq [°C]
0 30 100 200 300 500 750 1000 1500
13.6 13.6 13.6 13.1 12.7 12.3 11.9 11.4 10.7
13.6 13.6 13.6 12.8 12.1 11.6 11.0 10.6 10.1
45 45 45 45.4 45.7 46.1 47.0 48.0 49.0
25 26 30 35 40 51 63 77 103
Biasing current is kept constant to 2 mA for each RTH. Wg = 350 lm.
Gain [dB]
13
RTH [K/W]
12 11 10 9 8 -10
-5
0
5
10
15
Pout [dBm]
Fig. 6. Two-tone transducer gain versus output power for several different thermal resistance values. The quiescent current and thermal cut-off frequency are kept constant at 2 mA and 10 kHz, respectively. WG = 350 lm.
conditions, a significant drop of the gain occurs. With an RTH of 750 K/W, this drop is 1.7 dB. However, the drop of the output power is lower compared to that of the first experiment, and there is still an improvement in the linearity. The quiescent temperature, although lower than in the previous case, still reaches very high values for large thermal resistances.
5. Numerical thermal simulations A technology solution for reduction of large electrothermal feedback in the silicon-on-glass VDMOSFETs is shown in Fig. 1(d) and explained in Section 2. In this section, two-dimensional numerical thermal simulations are employed to calculate thermal performance of the packaged devices. Various bulk-silicon and silicon-onglass device designs are analyzed and compared. The simulated devices are high-power transistors with an infinite number of sections, the middle section of which defines the simulation domain. The domains for the silicon-on-glass and bulk-silicon transistors are given in Fig. 7(a) and (b) respectively. The boundary conditions are: isothermal for the bottom of the PCB substrate, and adiabatic for the AA 0 and BB 0 axis. Note that, since both glass and air have very poor thermal conductivities, the top silicon surface is also made adiabatic. For each device, the power density distribution is calculated in an isothermal condition using MEDICI [19] for VDS = 26 V and ID = 7 lA/lm. This approximately corresponds to the quiescent point in class AB bias condition, found above by the Smoothie model. In fact, the current of 7 lA/lm corresponds to 2.45 mA for devices with Wg of 350 lm. The calculated power density distributions are imported into Femlab [20] for thermal simulations. The temperature profiles are thus
N. Nenadovic´ et al. / Microelectronics Reliability 45 (2005) 541–550
A
B
AIR
gate
A
547
source B
400 µm
~ ~ gate
GLASS
BOX tD
~
tSi
SILICON
Cu
SILICON
source
underfill
drain
tSi,sub
source ~
Cu
dDS
tS
dS
dD
~ ~
~ ~ drain
source
~ ~
~ ~
~ ~ PCB
A'
~ ~ PCB
tPCB
B'
L/2
A'
(a)
(b)
∆Tmax=11.44 K
gate
400
0
395
-5
~ ~ gate 0
-5
GLASS
311.44
-10
308.36
-15
y[µm]
313.77
SILICON 312.67
-20
307.92
source
source
314.32
source
-10
-15
∆Tmax=14.32 K
313.22
~ source ~
SILICON
drain
B'
L/2
307.48
~ ~
~ ~
-100
drain
-105
AlN
307.04
-20 -110
~ ~
~ ~
~ ~
AlN
-190
-290
-195
-295 300.00
-200 -16
-12
-8
~ ~
300.00
-300 -4
0
-16
-12
-8
x[µm]
x[µm]
(c)
(d)
-4
0
Fig. 7. Simulation domains of (a) the silicon-on-glass VDMOSFET and (b) the bulk-Si VDMOSFET used for numerical thermal simulations. Simulated temperature profile of (c) the silicon-on-glass VDMOSFET and (d) the bulk-Si VDMOSFET both mounted on the same 200-lm-thick AlN PCB. The shorts protective layer (underfill) in (c) is made of BCB, while in (d) tSi,sub = 100 lm. Simulations are performed for the dissipated power of 0.182 mW/lm and ambient temperature of 300 K.
found for an input DC power of IDVDS = 0.182 mW/lm. This corresponds to 63.7 mW per section, if the sections are 350 lm long. Three sets of simulations are performed. The details on the simulation conditions are listed in Table 3. Typical values of the thermal conductivities k for the materials used in the simulations are given in Table 4. The
thermal contact resistance and non linearity of the thermal conductivity with temperature is not taken into account. In the first set of simulations (SIM-1) the thermal conductivity of the PCB, kPCB is varied, and the maximum temperature increase with respect to ambient is calculated for the silicon-on-glass and bulk-silicon
N. Nenadovic´ et al. / Microelectronics Reliability 45 (2005) 541–550
548
Table 3 Variables used for numerical thermal simulations Name
Comment
SIM-1
SIM-2
SIM-3
tSi [lm] dD [lm] dS [lm] dDS [lm] tPCB [lm] tD [lm] tS [lm] L [lm] tSi,sub [lm] kPCB kunderfill
Silicon top-layer thickness Half-width of the drain metal Half-width of the source metal Distance between the source and drain metal interconnects Thickness of the PCB Thickness of the drain metal Thickness of the source metal Distance between two fingers Thickness of the silicon substrate thermal conductivity of the PCB Thermal conductivity of the underfill
3.5 2 5.5 10 200 4 8 35 Varied Varied Of BCB
3.5 2 5.5 10 200 4 8 Varied Varied Of Al2O3 Of BCB
3.5 2 5.5 10 200 Varied Varied 35 Not used Of Al2O3 Varied
Table 4 Bulk values of thermal conductivity Material
BCB
SiO2
Al2O3
Si
AlN
Cu
k [W/mK]
0.7
1.4
25
150
270
400
VDMOSFETs. In addition, the thickness of the silicon substrate, tSi,sub of the bulk-silicon device is also varied. The results shown in Fig. 8 demonstrate that the wafer thinning strongly influences the value of DT, i.e. RTH. However, the benefit of the wafer thinning strongly depends on the type of the PCB. For example, if the PCB is made of Al2O3, it is beneficial to decrease the silicon wafer down to 100 lm. On the other hand, for a more thermally conducting PCB made of AlN, for example, wafer thinning is beneficial at least down-to 50 lm. An important result from this set of simulations is that RTH of a silicon-on-glass VDMOSFET can be made lower than that of the bulk-silicon counterpart with a silicon wafer thickness of only 100 lm, which is typical for the base-station LDMOSFET technologies. As the thermal conductivity of the PCB increases, the
silicon-on-glass VDMOSFET outperforms the bulk-silicon device even more. Such low values of RTH of the silicon-on-glass devices are due to the very close proximity of the PCB to the active device regions. In Fig. 7(c) and (d) the temperature distribution across the silicon-onglass VDMOSFET and bulk-silicon counterpart with tSi,sub = 100 lm are compared. Both devices are mounted to a 200-lm-thick PCB made of AlN. In the second set of thermal simulations (SIM-2), the distance between the neighboring fingers L is varied, and the maximum temperature increase with respect to ambient is calculated for the two type of devices. Like in the previous set of simulations, the thickness of the silicon substrate of the bulk-silicon device is also varied. The simulation results are given in Fig. 9. A strong reduction of the thermal resistance is achieved here at the expense of larger consumption of the silicon area. In the fabrication of the silicon-on-glass VDMOSFETs, the BCB is used to cover the drain interconnects before soldering, in order to prevent creation of shorts between the drain and source. The goal of the last set of simulations presented in this paper (SIM-3) is to
120 110
Bulk-Si VDMOSFET SOG VDMOSFET
100
100
∆T [K]
∆T [K]
tSi,sub=500 µm tSi,sub=300 µm Bulk-Si VDMOSFET
10
tSi,sub=100 µm
tSi,sub=50 µm
tSi,sub=300 µm
60
Al2O3 1
tSi,sub=500 µm
80 70
SOG VDMOSFET
10
90
Si
AlN 2
10
3
10
kPCB [W/m K]
Fig. 8. Maximum temperature increase with respect to ambient as a function of thermal conductivity of the PCB for siliconon-glass (SOG) and bulk-Si VDMOSFETs.
50 30
tSi,sub=100 µm
tSi,sub=50 µm
Cu 35
40
45
50
55
60
L [µm]
Fig. 9. Maximum temperature increase with respect to ambient as a function of distance between the device fingers for siliconon-glass (SOG) and bulk-Si VDMOSFETs.
N. Nenadovic´ et al. / Microelectronics Reliability 45 (2005) 541–550 90
tS=2tD=8 µm 88
tS=2tD=12 µm tS=2tD=20 µm
∆T [K]
86 84 82 80
BCB
78 10
-1
10
0
Cu
Si
SiO2 10
1
10
2
10
3
kunderfill [W/m K]
Fig. 10. Maximum temperature increase with respect to ambient as a function of the thermal conductivity of underfill for silicon-on-glass VDMOSFETs with different back-wafer metal thicknesses.
check to what extent the thermal performance of the silicon-on-glass VDMOSFETs depends on the thermal conductivity of this shorts-protective material, also called the underfill. The simulations are performed for 200-lm-thick PCBs made of Al2O3, and for different copper layer thickness on the drain and source. It can be seen from the results given in Fig. 10, that both the drain and source copper thickness, and the thermal conductivity of the shorts-protective layer do not influence the total RTH more than a few percent. This is due to a very large temperature drop across the Al2O3 PCB. In some other situations, where the PCB is made of a more thermally conducting material, the temperature drop across the PCB is smaller, and therefore the contribution from the shorts-protective layer and the backwafer copper thickness are more important. It is worth noting that the effect of the thermally conducting solder, which is used to assemble the devices on the printed circuit board, is not taken into account in the three sets of simulations presented here. This is due to uncertainty of both the thickness and the thermal conductivity of the solder. With the results from SIM-3, it is clear that any effect on the thermal resistance will not be significant for less thermally conducting packages. On the other hand, the effect of the solder will have to be taken into account for a more precise analysis of devices packaged on highly thermally conducting substrates.
6. Conclusions With the presented electrothermal characterization, both measurements and simulations demonstrate that unpackaged silicon-on-glass VDMOSFETs can have a very high thermal resistance and due to this the de-
549
vice temperatures can go up to the 100 °C range. The consequences of such large temperature rise on the RF performance are shown to be important for the output power rather than for the RF power gain and linearity. It is concluded that by adjusting the matching circuitry and biasing point, a condition can be created where the latter two parameters are unaffected by self-heating. The output power, however, significantly degrades, which is due to an enormous decrease in quasi-saturation current upon self-heating. Therefore, the thermal contact resistivity to the packaging heat sink will become a reliability risk if not kept controllably low. The proposed technology solution for reduction of the thermal resistance, based on backwafer low-thermal contacting and surface mounting, is shown to be very effective. By numerical simulations, different device designs have been compared and it was found that silicon-on-glass VDMOSFETs can have as low-thermal resistance as the comparable bulk-silicon devices with a silicon wafer thickness of 100 lm. This suggests that many of the thermal problems encountered in the silicon-on-insulator technologies in general can be solved by the surface mounting and low-thermal contacting.
References [1] Xu S, Baiocchi F, Safar H, Lott J, Shibib A, Xie Z, et al. High power silicon RF LDMOSFET technology for 2.1 GHz power amplifier applications. In: Proc. ISPSDÕ03, 2003. p.190–3. [2] Brech H, Brakensiek W, Burdeaux D, Burger W, Dragon C, Formicone G, et al. Record efficiency and gain at 2.1 GHz of high power RF transistors for cellular and 3G base stations. In: Tech Digest IEEE IEDMÕ03, 2003. p. 359–62. [3] Hammes PCA, Jos HFF, van Rijs F, Theeuwen SJCH, Vannema K. Advanced shield, drain and gate engineering for high efficiency, high power W-CDMA LDMOS transistors for base-stations. Microwave J 2004:94–101. [4] Fiorenza JG, Antoniadis DA, del Alamo JA. RF power LDMOSFET on SOI. IEEE Electron Dev Lett 2001;22: 139–41. [5] Nenadovic´ N, Cuoco V, Theeuwen SJCH, Nanver LK, Jos HFF, Slotboom JW. A novel vertical DMOS transistor in SOA technology for RF power applications. In: Proc. MIELÕ02, 2002. p. 159–62. [6] Nenadovic´ N, Cuoco V, Theeuwen SJCH, Nanver LK, Jos HFF, Slotboom JW. High-performance silicon-on-glass VDMOS transistor for RF-power applications. In: Proc. ESSDERCÕ02, 2002. p. 379–82. [7] Nenadovic´ N, Cuoco V, Theeuwen SJCH, Schellevis H, Spierings G, Griffo A et al. RF power silicon-on-glass VDMOSFETs. IEEE Electron Dev Lett 2004;25:424–6. [8] Dekker R, Baltus PGM, Maas HGR. Substrate transfer for RF technologies. IEEE Trans Electron Dev 2003;50: 747–57.
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[9] Cuoco V, van der Heijden MP, Pelk M, de Vreede LCN. Experimental Verification of the Smoothie database model for third and fifth order intermodulation distortion. In: Proc. ESSDERCÕ02, 2002. p. 635–8. [10] Cuoco V, Neo WCE, Spirito M, Yanson O, Nenadovic´ N, de Vreede LCN, et al. The electro-thermal Smoothie database model for LDMOS devices. In: Proc. ESSDERCÕ04, 2004, p. 457–60. [11] van Zeijl HW, Slabbekoorn J. Front- to back-wafer overlay accuracy in substrate transfer technologies. In: Proc. ISTCÕ01, 2001-17. p. 356–67. [12] Nanver LK, Nenadovic´ N, dÕAlessandro V, Schellevis H, van Zeijl HW, Dekker R et al. A back-wafer contacted silicon-on-glass integrated bipolar process, Part I—The conflict electrical versus thermal isolation. IEEE Trans Electron Dev 2004;51:42–50. [13] Lau John H, editor. Flip Chip technologies. New York: McGraw-Hill; 1996.
[14] Dekker R, Hartskeerl DMH, Maas HGR, van Rijsand F, Slotboom JW. 77% power added efficiency surfacemounted bipolar power transistors for low-voltage wireless applications. In: Proc IEEE BCTMÕ00, 2000. p. 191–4. [15] dÕAlessandro V, Rinaldi N. A critical review of thermal models for electro-thermal simulation. Solid-State Electron 2002;46:487–96. [16] Weast Robert C. Handbook of Chemistry and Physics. Boca Raton, Florida: CRC Press Inc.; 1990. [17] Sze SM. Physics of semiconductor devices. 2nd ed. New York: Wiley; 1981. [18] Vuolevi J, Rahkonen T. Extracting a polynomial ac FET model with thermal couplings from S-parameter measurements. In: Proc. IEEE ISCASÕ01, 2001, p. 461–4. [19] MEDICI UserÕs Manual. Palo Alto, California: TMA Inc.; 1992. [20] Femlab Reference Manual. Stockholm, Sweden: Comsol Inc. AB; 2003.
Electrothermal characterization of silicon-on-glass VDMOSFETs q N. Nenadovic´ a,*, V. Cuoco b, S.J.C.H. Theeuwen c, L.K. Nanver a, H. Schellevis a, G. Spierings c, H.F.F. Jos c, J.W. Slotboom a a b
Laboratory of ECTM, DIMES, Delft University of Technology, Feldmannweg 17, 2628 CT Delft, The Netherlands Laboratory of HiTeC, DIMES, Delft University of Technology, Feldmannweg 17, 2628 CT Delft, The Netherlands c Philips Semiconductors—RF Modules, Gerstweg 2, 6534 AE Nijmegen, The Netherlands Received 28 June 2004; received in revised form 16 August 2004 Available online 10 November 2004
Abstract Electrothermal consequences of implementing bulk-silicon RF power MOS processes in the silicon-on-glass substrate transfer technology are investigated in this paper. Fabricated silicon-on-glass vertical double-diffused MOSFETs are measured on-wafer and very large thermal resistance values are extracted for each design. The influence of the thermal resistance on RF performance is analyzed, and it is shown that strong electrothermal feedback severely lowers the power capability and strongly increases the operating temperature. A combination of low-thermal contacting and surface mounting to thermally conducting printed circuit board is shown to be very efficient in reducing the large thermal resistance. Numerical thermal simulations demonstrate that surface-mounted silicon-on-glass transistors can have lower thermal resistance than the bulk-silicon device with a wafer thickness reduced down to 100 lm. Ó 2004 Elsevier Ltd. All rights reserved.
1. Introduction Lateral double-diffused MOSFETs (LDMOSFETs) are todayÕs most advanced silicon technologies for linear radio frequency (RF) applications [1–3]. In the future, to meet the demand for very highly integrated wireless sys-
q
An earlier version of the paper was published in proceedings of 24th International conference on Microelectronics (MIEL 2004), 16–19 May 2004, NIS, Serbia and Montenegro, Vol. 1, pp. 145–148. * Corresponding author. Tel.: +31 15 2782185; fax: +31 15 2787369. E-mail address: [email protected] (N. Nenadovic´).
tems, new RF power device concepts and technologies will, however, be required [4]. We have developed and fabricated a new device called the silicon-on-glass (SOG) vertical double-diffused MOSFET (VDMOSFET) [5–7]. In this technology, a bulk-silicon LDMOS process of Philips Semiconductors for 2 GHz base-station applications is implemented in a substrate transfer silicon-on-glass technology [8]. Pure electrically these silicon-on-glass VDMOSFETs have been shown to be the first VDMOSFETs that are suitable for 2 GHz power applications [7]. Fabricated devices with a gate length of 0.8 lm and gate width of 350 lm were measured to have an fT/fmax of 6/10 GHz and a breakdown voltage approaching 100 V. These devices feature output power of 12 dBm at the 1-dB compression point, excellent linearity of IMD3 = 50 dBc and
0026-2714/$ - see front matter Ó 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2004.08.015
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IMD5 = 70 dBc, and high-power gain of Gt = 14 dB at 2 GHz. Electrothermally, however, glass is a very poor thermal conductor and it is shown here that replacing the silicon wafer by glass will very seriously increase the thermal resistance. Lowering this very high-thermal resistance becomes entirely dependent on the packaging of the devices, where the formation of a reliable and lowthermal contact resistance to the package heat sink becomes vital. This is studied in this paper by investigating the influence of the thermal resistance on the device RF performance. For this purpose we have employed the Smoothie database model for FET devices [9], which has been recently extended with electrothermal capabilities [10]. Finally, an extended thermal comparison of surface-mounted silicon-on-glass and bulk-silicon VDMOSFETs is performed. Numerical simulations are used to study the influence of the thermal conductivity of the printed circuit board (PCB), thickness of bulksilicon wafer, and other design parameters on the value of the thermal resistance.
minimizes debiasing over long drain fingers, while the second two times thicker layer to the source improves thermal conductance to thermal ground after packaging. In Fig. 2 a SEM image of a device with two copper layers is given. Successively, the drain copper interconnects are covered with a Benzo-Cyclo-Butane (BCB) layer before the individual devices are diced and soldered to thermally conducting PCB. Schematic cross-section of the surface-mounted silicon-on-glass VDMOSFET is given in Fig. 1(d). Based on the initial numerical thermal simulations it has been concluded in [7] that the surface-mounted silicon-on-glass VDMOSFETs can feature even much lower thermal resistance RTH than the corresponding bulk-silicon transistor mounted on the same copper heat sink. Thus, the wafer-level devices, schematically given in Fig. 1(c), have been measured in an isothermal (pulsed) condition to resemble performance of the surface-mounted transistors from Fig. 1(d). Results on the isothermal characterization of the first fabricated devices are presented in [7].
2. Device fabrication
3. Measurements of the thermal resistance
The silicon-on-glass VDMOS process flow is schematically presented in Fig. 1. It is divided into four parts: (a) the modified LDMOS processing on the SOI starting material, (b) the substrate transfer to glass with the backwafer low-ohmic contacting, (c) the copper electroplating of electrical and thermal interconnects on the backwafer, and (d) the surface mounting to a thermally conducting printed circuit board (PCB). The front-wafer processing defines the intrinsic device and is based on a production-line LDMOS process of Philips Semiconductors. The substrate transfer is introduced to reduce device parasitics, improve long-term reliability and enhance the quality of integrated passives. It is also a Philips production process, but is run in DIMES with several enhancements: the back-wafer is patterned with the same high-precision lithography as the front-wafer [11], and low-ohmic p- and n-type contacts are formed by implanting, laser annealing and metallizing with a sputtered 1.4lm-thick Al/Si(1%) [12]. The front-wafer source and gate bond-pads are brought to the back-wafer by the diffused vias (p+-sinkers), while the drain is directly contacted from the back-wafer. The gate p+-sinkers are isolated from the n-drain by the deep trenches etched from the back-wafer to the front-wafer oxide. To reduce self-heating, both the copper thermal interconnects and surface-mounted assembly [13,14] are introduced. First, a Ti/TiN diffusion and adhesion barrier, and a copper seed layer are sputtered on the back-wafer. This is followed by electroplating of two layers of copper as is schematically shown in Fig. 1(c). The first, approximately 5-lm-thick layer on the drain
In this section, three silicon-on-glass VDMOSFET designs are measured and compared with respect to RTH. Schematic cross-sections of the investigated transistors are given in Fig. 3. All the devices are single-drain transistors, such as the one from Fig. 2. The measured devices have a gate width Wg of 350 lm and are characterized on-wafer, i.e. before dicing and soldering. The transistors (a) and (b) differ only with respect to the back-wafer metallization. In fact, the back-wafer metal of device (a) is made of a 1.4-lm-thick Al/Si, while the transistor (b) is also metallized with a thick copper both on the drain and source. Compared to (b), the transistor (c) has a thicker top-silicon layer. With the chosen transistors the effect of the top-silicon layer and a thick, thermally floating metal interconnect on the thermal resistance can be studied. All the measurements are performed on the Cascade probing station equipped with a thermal-chuck. The measurement method used here to extract the thermal resistance is illustrated in Fig. 4, where the data measured on the device from Fig. 3(a) are shown. First, input ID-VGS characteristics are measured for a constant drain–source voltage VDS. The measurements are performed in isothermal conditions for several thermalchuck temperatures using the AgilentÕs 85124A pulsemeasurement system. The isothermal characteristics are used for extraction of the temperature coefficient of the drain current dIdTD . Successively, a non-isothermal (DC) measurement is performed for a fixed thermalchuck temperature of 25C, using an HP4156B parameter analyzer. The DC characteristic is compared to the isothermal measurements at 25C, and a temperature
N. Nenadovic´ et al. / Microelectronics Reliability 45 (2005) 541–550
(a) Front-wafer processing: field-plate gate gate source n+ p-
p++ p+sinker
~ ~
gate plug source
p- n+ n-drain
p++
p++
p+sinker
p+sinker
~5 µm
~ ~ ~500 µm
BOX
Si substrate
(b) Silicon substrate transfer to glass, back-wafer implantation, laser annealing and metallizing with sputtered Al/Si:
~ ~
~ ~ ~400 µm
glass field-plate gate gate
adhesive source
~10 µm
gate plug
p+ sinker p++
p+ sinker p++
n-drain n++ drain
source
trench
source
source
~5 µm
p+ sinker p++
gate
(c) Back-wafer copper plating and BCB deposition: ~ ~
~ ~
glass field-plate gate gate
adhesive source
BCB
n++
p++
trench
p++ Cu
gate plug source
Cu drain
Cu
BCB
source
p++ ~10 µm
Cu
source
gate
(d) Surface mounting to thermally conducting printed circuit board: ~ ~
~ ~ ~400 µm
glass field-plate gate gate
adhesive source
n-epi
BCB
source
metal
n++ Cu drain
PCB
oxide
p++
~10 µm
p++
p+ sinker p++
trench
p- n++
n++ p-
p++ p+ sinker p++ Cu
gate plug source
Cu
BCB
source
solder
p+ sinker p++
~5 µm
Cu
~10 µm
gate
polysilicon
Fig. 1. Schematic of the silicon-on-glass VDMOS process flow.
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N. Nenadovic´ et al. / Microelectronics Reliability 45 (2005) 541–550
544
DT ¼
DI D ; dI D dT
ð1Þ
where DID is the change in drain current due to selfheating. Thus, it is straightforward to extract the thermal resistance from: RTH ¼
Fig. 2. Scanning electron microscopy image of a silicon-onglass VDMOSFET seen from the back-wafer side. WG = 70 lm.
increase with respect to ambient is calculated as function of bias: ~ ~
DT DI D DI D ¼ ; ¼ dI D dI D P P I D;DC V DS dT dT
where ID,DC is the drain current measured in DC condition. The thermal resistance is dependent on bias due to the size modulation of the heat source [15], and the temperature dependence of the thermal conductivity of silicon and glass [16]. However, only a small change in RTH with bias is measured here for all the investigated devices. This is due to a weak modulation of the size of the heat source under normal operating conditions, and due to an opposite temperature dependence of the ~ ~
glass adhesive gate source
gate
gate plug source
oxide
3.5 µm drain
source
~ ~
source
gate (a)
~ ~
glass adhesive gate source
gate
gate plug source
oxide
3.5 µm Cu drain
Cu
Cu
source
~ ~
source
Cu
8 µm
gate (b)
~ ~
glass adhesive gate source
gate
gate plug source
oxide
4 µm
Cu
source
Cu drain
ð2Þ
Cu
source
Cu
8 µm
gate (c)
Fig. 3. Schematic cross-sections of the three types of devices measured and compared with respect to the thermal resistance.
N. Nenadovic´ et al. / Microelectronics Reliability 45 (2005) 541–550
IDSX
VDS=5 V
20
∆ID ID [mA]
15
ID,DC
T0=25,50,75,100OC
10
5
non-isothermal, for TAMB=25OC
VTH
isothermal
0 2
3
4
5
6
7
8
VGS [V] Fig. 4. Measured isothermal (pulsed) and non isothermal (DC) ID–VGS characteristics of a silicon-on-glass VDMOSFET such as the one shown in Fig. 3(a) with WG = 350 lm.
thermal conductivity of silicon and glass. The extracted thermal resistances are: 1200 K/W for device (a), 780 K/ W for device (b), and 660 K/W for device (c). Thus, it can be concluded that even with thermally floating heat spreaders significant reduction of RTH can be achieved. Nevertheless, even the lowest measured value of RTH is almost one order of magnitude larger than that of the comparable wafer-level bulk-silicon device, which has been measured to be only 80 K/W for a silicon wafer thickness of 120 lm. It should be noted that the thermal resistance is usually reduced by the silicon wafer thinning and furthermore by packaging, and typically a bulk-silicon device with a large gate width of for example 70 mm will have a thermal resistance as low as 1 K/W.
545
Small signal S-parameters of the device from Fig. 3(b) together with DC data are collected at 2 GHz and at different temperatures, and Smoothie databases are extracted from this data. Successively, the measured single-pole RTH–CTH parallel thermal impedance network is coupled to the electrical databases, and the device RF performance is evaluated by means of two-tone load-pull electrothermal simulation performed at 2 GHz with a tone spacing of 200 kHz. The thermal cut-off frequency fTH = 1/(2pRTHCTH) was extracted from transient thermal impedance data. Both the thermal resistance and thermal capacitance are considered temperature independent. Note that the exact value of fTH, i.e. CTH, is not crucial for the analysis, since the thermal response is anyway limited to low-frequencies. Thus, neither the fundamental tone nor the higher harmonics and the IF tone significantly modulate the temperature. Therefore, only DC power influences the operating temperature. The two-tone transducer gain and third- and fifth-order intermodulation distortion versus output power are derived in class AB bias condition with a supply voltage of VDD = 26 V and quiescent current Idq of 2.12 mA, and the results are shown in Fig. 5. The simulations are repeated with different values of the thermal resistance and keeping the thermal cut-off frequency fTH 10 kHz unchanged. In the first set of calculations it is assumed that 13.6 dB power-gain is required for the application. Therefore, the bias conditions for each simulation are adjusted in order to meet this requirement. From Table 1 it appears that as the thermal resistance increases, the output power measured at the 1-dB compression point drops dramatically, although the RF power gain is unchanged and linearity
0
14.5 14
f = 2 GHz ∆f = 200 kHz
10 dB -20
From the measured isothermal and non-isothermal characteristics from Fig. 4, it is clear that self-heating reduces the transconductance gm, lowers the threshold voltage VTH and reduces the quasi-saturation current IDSX [17]. Lower gm, for example, negatively influences the cut-off frequency and maximum oscillation frequency of a device. However, for other figures of merit, such as the RF power gain, linearity and output power, the dependence on the thermal resistance is less clear, since these quantities depend on the external matching circuitry. Therefore, it is useful to study how VDMOS transistors with different thermal resistances behave in terms of RF performance. For this purpose, we have used the Smoothie electrothermal database model for FET devices.
Gain [dB]
1 dB
-40
13 12.5
-60
IMD3 [dBc]
13.5
4. RF performance as function of thermal resistance
12 -80 11.5 11 -10
-5
0
5
10
-100 15
Pout [dBm]
Fig. 5. Two-tone transducer gain and third-order intermodulation distortion versus output power for the device from Fig. 3(b), derived with the Smoothie database model. Calculations are performed in class AB bias condition (VDD = 26 V and Idq = 2.12 mA) based on the measured isothermal S-parameters and thermal single-pole network (RTH = 780 K/W, fTH = 10 kHz). WG = 350 lm.
N. Nenadovic´ et al. / Microelectronics Reliability 45 (2005) 541–550
546
Table 1 RF performance of silicon-on-glass VDMOSFETs as function of the thermal resistance
14
RTH=0,300,750,1500 K/W
P1 dB [dBm]
IMD310 dB [dBc]
Idq [mA]
Tq [°C]
0 30 100 200 300 500 750 1000 1500
13.6 13.2 11.5 10.8 10.4 10.3 10.0 9.7 9.3
45 45 45 45.5 45.8 46.5 48.0 49.0 50.0
2.00 2.00 2.05 2.06 2.07 2.09 2.12 2.15 2.20
25 26 30 36 41 52 66 90 111
Power gain Gt is kept constant to 13.6 dB for each RTH. Wg = 350 lm.
at the 10 dB back-off improved. In fact, already with a value of RTH equal to 100 K/W, the drop in the output power is larger than 2 dB compared to the situation in which the thermal resistance is negligible. The drop becomes larger than 3.5 dB for a RTH of 750 K/W. This has obvious negative consequences on the cost, since the only way to increase the output power of a transistor with large RTH would be to make it bigger. Moreover, the quiescent point temperature Tq, i.e. the temperature of the device without any RF power applied, strongly increases with RTH. It is also useful to note that behavior of IMD performance as the temperature increases (i.e. RTH increases) is regulated by the relative phases of various harmonic components. This could be better investigated with the aid of Volterra series analysis [18]. In the second set of calculations, characterization for different values of the thermal resistance is repeated but now with the quiescent current Idq kept constant at 2 mA. The thermal cut-off frequency of 10 kHz is again kept unchanged for each RTH. The results of the simulations are summarized in Table 2 and Fig. 6. Under these
Table 2 RF performance of silicon-on-glass VDMOSFETs as function of the thermal resistance RTH [K/W]
GT [dB]
P1 dB [dBm]
IMD310 dB [dBc]
Tq [°C]
0 30 100 200 300 500 750 1000 1500
13.6 13.6 13.6 13.1 12.7 12.3 11.9 11.4 10.7
13.6 13.6 13.6 12.8 12.1 11.6 11.0 10.6 10.1
45 45 45 45.4 45.7 46.1 47.0 48.0 49.0
25 26 30 35 40 51 63 77 103
Biasing current is kept constant to 2 mA for each RTH. Wg = 350 lm.
Gain [dB]
13
RTH [K/W]
12 11 10 9 8 -10
-5
0
5
10
15
Pout [dBm]
Fig. 6. Two-tone transducer gain versus output power for several different thermal resistance values. The quiescent current and thermal cut-off frequency are kept constant at 2 mA and 10 kHz, respectively. WG = 350 lm.
conditions, a significant drop of the gain occurs. With an RTH of 750 K/W, this drop is 1.7 dB. However, the drop of the output power is lower compared to that of the first experiment, and there is still an improvement in the linearity. The quiescent temperature, although lower than in the previous case, still reaches very high values for large thermal resistances.
5. Numerical thermal simulations A technology solution for reduction of large electrothermal feedback in the silicon-on-glass VDMOSFETs is shown in Fig. 1(d) and explained in Section 2. In this section, two-dimensional numerical thermal simulations are employed to calculate thermal performance of the packaged devices. Various bulk-silicon and silicon-onglass device designs are analyzed and compared. The simulated devices are high-power transistors with an infinite number of sections, the middle section of which defines the simulation domain. The domains for the silicon-on-glass and bulk-silicon transistors are given in Fig. 7(a) and (b) respectively. The boundary conditions are: isothermal for the bottom of the PCB substrate, and adiabatic for the AA 0 and BB 0 axis. Note that, since both glass and air have very poor thermal conductivities, the top silicon surface is also made adiabatic. For each device, the power density distribution is calculated in an isothermal condition using MEDICI [19] for VDS = 26 V and ID = 7 lA/lm. This approximately corresponds to the quiescent point in class AB bias condition, found above by the Smoothie model. In fact, the current of 7 lA/lm corresponds to 2.45 mA for devices with Wg of 350 lm. The calculated power density distributions are imported into Femlab [20] for thermal simulations. The temperature profiles are thus
N. Nenadovic´ et al. / Microelectronics Reliability 45 (2005) 541–550
A
B
AIR
gate
A
547
source B
400 µm
~ ~ gate
GLASS
BOX tD
~
tSi
SILICON
Cu
SILICON
source
underfill
drain
tSi,sub
source ~
Cu
dDS
tS
dS
dD
~ ~
~ ~ drain
source
~ ~
~ ~
~ ~ PCB
A'
~ ~ PCB
tPCB
B'
L/2
A'
(a)
(b)
∆Tmax=11.44 K
gate
400
0
395
-5
~ ~ gate 0
-5
GLASS
311.44
-10
308.36
-15
y[µm]
313.77
SILICON 312.67
-20
307.92
source
source
314.32
source
-10
-15
∆Tmax=14.32 K
313.22
~ source ~
SILICON
drain
B'
L/2
307.48
~ ~
~ ~
-100
drain
-105
AlN
307.04
-20 -110
~ ~
~ ~
~ ~
AlN
-190
-290
-195
-295 300.00
-200 -16
-12
-8
~ ~
300.00
-300 -4
0
-16
-12
-8
x[µm]
x[µm]
(c)
(d)
-4
0
Fig. 7. Simulation domains of (a) the silicon-on-glass VDMOSFET and (b) the bulk-Si VDMOSFET used for numerical thermal simulations. Simulated temperature profile of (c) the silicon-on-glass VDMOSFET and (d) the bulk-Si VDMOSFET both mounted on the same 200-lm-thick AlN PCB. The shorts protective layer (underfill) in (c) is made of BCB, while in (d) tSi,sub = 100 lm. Simulations are performed for the dissipated power of 0.182 mW/lm and ambient temperature of 300 K.
found for an input DC power of IDVDS = 0.182 mW/lm. This corresponds to 63.7 mW per section, if the sections are 350 lm long. Three sets of simulations are performed. The details on the simulation conditions are listed in Table 3. Typical values of the thermal conductivities k for the materials used in the simulations are given in Table 4. The
thermal contact resistance and non linearity of the thermal conductivity with temperature is not taken into account. In the first set of simulations (SIM-1) the thermal conductivity of the PCB, kPCB is varied, and the maximum temperature increase with respect to ambient is calculated for the silicon-on-glass and bulk-silicon
N. Nenadovic´ et al. / Microelectronics Reliability 45 (2005) 541–550
548
Table 3 Variables used for numerical thermal simulations Name
Comment
SIM-1
SIM-2
SIM-3
tSi [lm] dD [lm] dS [lm] dDS [lm] tPCB [lm] tD [lm] tS [lm] L [lm] tSi,sub [lm] kPCB kunderfill
Silicon top-layer thickness Half-width of the drain metal Half-width of the source metal Distance between the source and drain metal interconnects Thickness of the PCB Thickness of the drain metal Thickness of the source metal Distance between two fingers Thickness of the silicon substrate thermal conductivity of the PCB Thermal conductivity of the underfill
3.5 2 5.5 10 200 4 8 35 Varied Varied Of BCB
3.5 2 5.5 10 200 4 8 Varied Varied Of Al2O3 Of BCB
3.5 2 5.5 10 200 Varied Varied 35 Not used Of Al2O3 Varied
Table 4 Bulk values of thermal conductivity Material
BCB
SiO2
Al2O3
Si
AlN
Cu
k [W/mK]
0.7
1.4
25
150
270
400
VDMOSFETs. In addition, the thickness of the silicon substrate, tSi,sub of the bulk-silicon device is also varied. The results shown in Fig. 8 demonstrate that the wafer thinning strongly influences the value of DT, i.e. RTH. However, the benefit of the wafer thinning strongly depends on the type of the PCB. For example, if the PCB is made of Al2O3, it is beneficial to decrease the silicon wafer down to 100 lm. On the other hand, for a more thermally conducting PCB made of AlN, for example, wafer thinning is beneficial at least down-to 50 lm. An important result from this set of simulations is that RTH of a silicon-on-glass VDMOSFET can be made lower than that of the bulk-silicon counterpart with a silicon wafer thickness of only 100 lm, which is typical for the base-station LDMOSFET technologies. As the thermal conductivity of the PCB increases, the
silicon-on-glass VDMOSFET outperforms the bulk-silicon device even more. Such low values of RTH of the silicon-on-glass devices are due to the very close proximity of the PCB to the active device regions. In Fig. 7(c) and (d) the temperature distribution across the silicon-onglass VDMOSFET and bulk-silicon counterpart with tSi,sub = 100 lm are compared. Both devices are mounted to a 200-lm-thick PCB made of AlN. In the second set of thermal simulations (SIM-2), the distance between the neighboring fingers L is varied, and the maximum temperature increase with respect to ambient is calculated for the two type of devices. Like in the previous set of simulations, the thickness of the silicon substrate of the bulk-silicon device is also varied. The simulation results are given in Fig. 9. A strong reduction of the thermal resistance is achieved here at the expense of larger consumption of the silicon area. In the fabrication of the silicon-on-glass VDMOSFETs, the BCB is used to cover the drain interconnects before soldering, in order to prevent creation of shorts between the drain and source. The goal of the last set of simulations presented in this paper (SIM-3) is to
120 110
Bulk-Si VDMOSFET SOG VDMOSFET
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100
∆T [K]
∆T [K]
tSi,sub=500 µm tSi,sub=300 µm Bulk-Si VDMOSFET
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tSi,sub=500 µm
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Fig. 8. Maximum temperature increase with respect to ambient as a function of thermal conductivity of the PCB for siliconon-glass (SOG) and bulk-Si VDMOSFETs.
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tSi,sub=100 µm
tSi,sub=50 µm
Cu 35
40
45
50
55
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L [µm]
Fig. 9. Maximum temperature increase with respect to ambient as a function of distance between the device fingers for siliconon-glass (SOG) and bulk-Si VDMOSFETs.
N. Nenadovic´ et al. / Microelectronics Reliability 45 (2005) 541–550 90
tS=2tD=8 µm 88
tS=2tD=12 µm tS=2tD=20 µm
∆T [K]
86 84 82 80
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Fig. 10. Maximum temperature increase with respect to ambient as a function of the thermal conductivity of underfill for silicon-on-glass VDMOSFETs with different back-wafer metal thicknesses.
check to what extent the thermal performance of the silicon-on-glass VDMOSFETs depends on the thermal conductivity of this shorts-protective material, also called the underfill. The simulations are performed for 200-lm-thick PCBs made of Al2O3, and for different copper layer thickness on the drain and source. It can be seen from the results given in Fig. 10, that both the drain and source copper thickness, and the thermal conductivity of the shorts-protective layer do not influence the total RTH more than a few percent. This is due to a very large temperature drop across the Al2O3 PCB. In some other situations, where the PCB is made of a more thermally conducting material, the temperature drop across the PCB is smaller, and therefore the contribution from the shorts-protective layer and the backwafer copper thickness are more important. It is worth noting that the effect of the thermally conducting solder, which is used to assemble the devices on the printed circuit board, is not taken into account in the three sets of simulations presented here. This is due to uncertainty of both the thickness and the thermal conductivity of the solder. With the results from SIM-3, it is clear that any effect on the thermal resistance will not be significant for less thermally conducting packages. On the other hand, the effect of the solder will have to be taken into account for a more precise analysis of devices packaged on highly thermally conducting substrates.
6. Conclusions With the presented electrothermal characterization, both measurements and simulations demonstrate that unpackaged silicon-on-glass VDMOSFETs can have a very high thermal resistance and due to this the de-
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vice temperatures can go up to the 100 °C range. The consequences of such large temperature rise on the RF performance are shown to be important for the output power rather than for the RF power gain and linearity. It is concluded that by adjusting the matching circuitry and biasing point, a condition can be created where the latter two parameters are unaffected by self-heating. The output power, however, significantly degrades, which is due to an enormous decrease in quasi-saturation current upon self-heating. Therefore, the thermal contact resistivity to the packaging heat sink will become a reliability risk if not kept controllably low. The proposed technology solution for reduction of the thermal resistance, based on backwafer low-thermal contacting and surface mounting, is shown to be very effective. By numerical simulations, different device designs have been compared and it was found that silicon-on-glass VDMOSFETs can have as low-thermal resistance as the comparable bulk-silicon devices with a silicon wafer thickness of 100 lm. This suggests that many of the thermal problems encountered in the silicon-on-insulator technologies in general can be solved by the surface mounting and low-thermal contacting.
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