Negative bias temperature instability mechanisms in p-channel power VDMOSFETs

Microelectronics Reliability 45 (2005) 1343–1348 www.elsevier.com/locate/microrel

Negative bias temperature instability mechanisms in p-channel power VDMOSFETs N. Stojadinoviüa, *, D. Dankoviüa, S. Djoriü-Veljkoviüb, V. Davidoviüa, I. Maniüa, S. Goluboviüa a b

Faculty of Electronic Engineering, University of Niš, Aleksandra Medvedeva 14, 18000 Niš, Serbia and Montenegro Faculty of Civil Engineering and Architecture, University of Niš, A. Medvedeva 14, 18000 Niš, Serbia and Montenegro

Abstract The negative bias temperature stress induced instabilities of threshold voltage in commercial p-channel power VDMOSFETs have been investigated. The threshold voltage shifts, which are more pronounced at higher voltages and/or temperatures, are caused by the NBT stress induced buildup of both oxide trapped charge and interface traps. However, the observed power low time dependencies of threshold voltage shifts are found to be affected mostly by the oxide trapped charge. The results are analysed in terms of the mechanisms responsible for buildup of oxide charge and interface traps, and the model that explains experimental data is discussed in details. Ó 2005 Elsevier Ltd. All rights reserved.

1. Introduction In spite of continuous scaling down of the dimensions of CMOS devices, widespread utilization of MOS technology for the realization of power devices and ICs has lead to an increased interest in ultra-thick gate oxides as well. Consequently, investigations of related reliability issues have gained in importance, and degradation of power MOSFETs under various stresses (irradiation, high field, temperature, and even hot carrier) has been subject of extensive research [1]. However, very few authors addressed the negative bias temperature instabilities (NBTI) in these devices [2, 3]. NBTI are known to occur in p-channel MOSFETs stressed with negative gate voltages corresponding to the fields of 2 – 6 MV/cm at elevated temperatures in the range of 100 – 250o C [2-5]. These fields and temperatures are typically found during the device burn-in [6], but also 

* Corresponding author. Tel. +381 18 529 326; fax: +381 18 588 399. E-mail: [email protected] (N. Stojadinoviü).

can be approached during the power MOSFET routine operation in automotive and industrial applications [3]. In this paper we present detailed analysis of NBT stress induced instabilities of threshold voltage in commercial p-channel power VDMOSFETs. The underlying changes of gate oxide trapped charge and interface trap densities are calculated and analysed in terms of the mechanisms responsible, and model that explains experimental data is discussed in details. 2. Results and discussion Devices used in this study were commercial pchannel power VDMOSFETs IRF9520 built in standard Si-gate technology with 100 nm thick gate oxide. Devices were stressed by negative gate voltages in the range 35 – 45 V, with drain and source terminals grounded, at temperatures ranging from 125 to 175o C. Electrical characterization of investigated devices was performed by measuring the subthreshold and above-threshold transfer and charge pumping characteristics.

0026-2714/$ - see front matter Ó 2005 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2005.07.018

N. Stojadinovic´ et al. / Microelectronics Reliability 45 (2005) 1343–1348

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The time dependencies of threshold voltage shift (ǻVT) during the NBT stressing of IRF9520 pchannel VDMOSFETs are shown in Fig. 1. As can be seen, NBT stress caused significant threshold voltage shifts, more pronounced at higher voltages and/or

temperatures. Further analysis has shown that ǻVT time dependencies followed the tn power low, but with three different phases (as indicated by the dashed lines), which can be clearly distinguished depending on the value of parameter n. In the first

1

t t

0.14

0.25

'VT(V)

0.1

o

t

T( C) VG(V)

0.4~0.63

0.01

0.1

1

10

Stress time (hours)

125 125 125

-35 -40 -45

150 150 150

-35 -40 -45

175 175 175

-35 -40 -45

100

1000

Fig. 1. Time dependencies of 'VT during NBT stressing of p-channel power VDMOSFETs.

(early) phase, n strongly depends on both bias and temperature, varying from 0.4 to 0.63. In the second phase, parameter n is almost independent on bias and temperature, and ǻVT follows the well-known t0.25 law, as obtained in all earlier NBTI investigations on devices manufactured in various technologies [2-5]. This phase begins earlier in devices stressed at higher voltages and/or temperatures, and one may even expect the first phase to disappear under more severe stress conditions. Applying an approach from [5] to the results in Fig. 1, the following ǻVT dependence on stress field, time, and temperature in the second phase was obtained:

'VT

3.04E 2.05 t 0.25 exp(0.24 / kT ) .

(1)

Finally, in the third phase, n becomes bias and temperature dependent again, gradually decreasing from 0.25 to 0.14, and ǻVT tends to saturate. The ǻVT in saturation after near 2000 hours of stressing was found to vary from 6.5% (125oC, -35 V) to 20% (175oC, -45 V). More elaborate analysis of all three phases indicates that the overall ǻVT time dependencies can be expressed as [7]:

'VT

B1[1  exp(t / W 1 )]  B2 [1  exp(t / W 2 )] , (2)

where the fitting parameters IJ1 and IJ2 are the time constants related to the transitions from early to second phase and from second to third phase, respectively, while B1 and B2 are related to corresponding VT shifts. As an illustration, Table 1 shows the fitting parameters for two characteristic sets of data (different stress voltages at medium temperature and different temperatures at medium stress voltage) from Fig. 1. As can be seen, IJ1 and IJ2 are nearly equal to the stress times at which the phase transitions (early-to-second and second-to-saturation phase, respectively) occur, while B1 and B2 are nearly equal to corresponding VT shifts. Table 1: Fitting parameters for NBTI data shown in Fig. 1. T=150oC VG (V) -35 -40 -45

B1 (mV) 85 121 121

B2 (mV) 156 219 262

W1

W2

(h) 1.8 1.7 2.0

(h) 119.8 130.7 155.5

VG=-40V T (oC) 125 150 175

B1 (mV) 77 121 205

B2 (mV) 146 219 226

W1

W2

(h) 2.5 1.7 3.1

(h) 118.8 130.7 86.5

N. Stojadinovic´ et al. / Microelectronics Reliability 45 (2005) 1343–1348

Dependencies of the underlying buildup of gate oxide trapped charge (ǻNot) and interface traps (ǻNit) on stress bias (at 150o C) and temperature (at -40 V) are shown in Figs. 2 and 3, respectively. ǻNot was determined by subthreshold midgap technique (SMGT) [8], while ǻNit by both SMGT and charge pumping technique (CPT) [9]. The SMGT and CPT

10

-2

'Not, 'Nit (10 cm )

10

1

'Not

0.1

'Nit

o

T=150 C

0.1

1

10

Stress time (hours)

100

VG(V) -35 -40 -45

1000

Fig. 2. Dependencies of 'Not and 'Nit on NBT stress bias at 150oC.

influenced by increase of both temperature and bias than ǻNit (note that the bias voltage effect becomes more obvious by plotting Fig. 2 in linear scale). In order to establish the dominant cause of stress induced VT shifts, time dependencies of ǻVT are compared with those of ǻNot and ǻNit in Figs. 4 and 5, respectively. As can be seen in Fig. 4, either the stress temperature was kept constant and bias varied (a) or vice versa (b), the time dependencies of ǻVT look very similar to those of ǻNot. On the other hand, Fig. 5 does not indicate such a strong correlation between ǻVT and ǻNit time dependencies, with disagreement becoming more pronounced as the NBT stressing advances into the second phase and, especially, further into the saturation. Therefore, ǻVT time dependencies in power VDMOSFETs seem to be mostly affected by NBT stress induced buildup of oxide trapped charge, which does not appear to be consistent with most of literature data emphasizing dominant role of stress induced interface traps [3-5]. Applying the same approach from [5] (as in the case of ǻVT data, see Eq. 1) to 'Not and 'Nit data shown in Figs. 2 and 3, the following dependencies

10

1

10

-2

'Not (10 cm )

1

0.1

1

0.1

VG=-40V

0.1

1

10

Stress time (hours)

100

'Nit

'Not

o

T( C) 125 150 175

0.1

1

10

Stress time (hours)

100

0.01

1000

0.1

1

10

-2

'Not (10 cm )

(a) 1

10

Fig. 3. Dependencies of 'Not and 'Nit on NBT stress temperature at VG =-40 V.

yielded similar values of ǻNit, indicating negligible contribution from border traps. Note that the phase transitions observed in ǻVT data (Fig. 1) cannot be clearly seen in the case of ǻNot and ǻNit time dependencies, but earlier established transitions were maintained in Figs. 2 and 3 (dashed lines) for the purpose of data analysis. Both figures indicate larger buildup of oxide charge in all three stress phases, independently on bias and temperature conditions. On the other hand, ǻNit rapidly increases in the early phase, but slows down in the second phase and tends to saturate faster than ǻNot. In addition, ǻNot is more

-35 -40 -45

o

T=150 C

0.1

1000

'VT VG (V)

'VT(V)

'Not

'VT(V)

10

10

-2

'Not, 'Nit (10 cm )

1345

'Not

0.1

'VT

VG=-40V

0.1

1

10

Stress time (hours)

100

o

T ( C) 125 150 175

0.01

1000

(b)

Fig. 4. Comparison of 'VT and 'Not dependencies on NBT stress bias at 150oC (a) and on temperature at VG =-40V (b).

N. Stojadinovic´ et al. / Microelectronics Reliability 45 (2005) 1343–1348

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or by dissociation of weak SiH bonds near the interface by high electric field [11]:

1

10

-2

'Nit (10 cm )

O3 {SiH  h  l O3 {Si   H x . 0.1

'Nit

0.1

'VT VG(V)

-35 -40 -45

o

T=150 C

0.1

1

10

100

Stress time (hours)

'VT(V)

10

1

1000

0.01

(a)

-2

'Nit (10 cm )

10

'Nit

0.1

VG=-40V

0.1

1

10

Stress time (hours)

100

o

'VT T( C)

125 150 175

'VT(V)

0.1

1

The trapped positive charge gradually decreases the local electric field in the vicinity of SiO2-Si interface, leading to slower buildup of Not as the stress time increases. Also, the trapped oxide charge may be transformed into the interface traps [10]:

O3 { Si  x Si { O3  Si3 { Si  H  e  o

1

10

(6)

0.01

Si3 { Si x  O3 { Si xx Si { O3  H x . (7) However, the above reaction is not quite satisfactory to explain very fast increase of Nit in the early phase, and an additionial buildup of interface traps is likely to occur due to dissociation of weak interfacial SiH bonds by high electric field [4, 5]:

Si3 {SiH l Si 3 {Si x  H x .

The released hydrogen atoms are highly reactive, and they also can dissociate the SiH bonds at the interface or in the oxide near the interface [4, 5]:

Si3 {SiH  H x l Si3 {Si x  H 2 ,

1000

(b)

Fig. 5. Comparison of 'VT and 'Nit dependencies on NBT stress bias at 150oC (a) and on temperature at VG =-40V (b).

of 'Not and 'Nit on NBT stress field, time, and temperature in the second stress phase were obtained:

(8)

(9)

O3 {SiH  H x  h  l O3 {Si   H 2 , (10) leading to creation of additional interface traps or positively charged oxide defects. Some recent studies indicate that the unstable hydrogen atoms released in (6)-(8) are more likely to dimerize into molecules or to react with the holes to form ions [12]:

'N ot

1.16 ˜ 1011 E 2.44 t 0.25 exp( 0.21 / kT ) , (3)

H x  H x o H2 ,

(11)

'N it

1.56 ˜ 1010 E 2.11t 0.18 exp( 0.15 / kT ) . (4)

H x  h o H  ,

(12)

As can be seen, ǻNot follows the same t0.25 time dependence as ǻVT, which clearly confirms dominant influence of oxide trapped charge on VT shift in NBT stressed power VDMOSFETs. 3. Mechanisms responsible Stress induced buildup of oxide trapped charge and interface traps is known to occur due to various electrochemical reactions involving the oxide and interface defects and various water-related species (Hx, H+, H2, H2O). Remarkable initial increase of oxide charge density can be explained by hole trapping at the oxide vacancy defects [10]:

O3 { Si xx Si { O3  h  o O3 { Si  x Si { O3 , (5)

but hydrogen ions also dissociate SiH bonds at the interface or in the oxide near the interface [4, 12]:

Si3 {SiH  H   e  l Si3 {Si x  H 2 , O3 {SiH  H  l O3 {Si   H 2 ,

(13) (14)

leading to creation of interface traps or positively charged oxide defects. The buildup of interface traps and oxide trapped charge through the above reactions is particularly enhanced in the early phase when there is still high concentration of SiH trap precursors. However, the number of both interface traps and positively charged oxide defects gradually increases over the stress time; consequently, the probability that reverse reactions (6), (8)-(10), (13), and (14) (passivation processes) occur is getting higher as the stressing progresses.

N. Stojadinovic´ et al. / Microelectronics Reliability 45 (2005) 1343–1348

The H2 molecules released in reactions (9)-(11), (13), and (14) diffuse into the oxide and can be cracked at positively charged oxide traps [13]:

O3 { Si   H 2 o O3 { Si  H   H x .

(15)

Neutral hydrogen released in (15) can take part in forward reactions (9)-(12) and reverse reactions (6) and (8), rounding up the chain of reactions (6)-(15). Note that the H2 and H2O molecules, originating from the oxide adjacent layers or even package inside, can diffuse at elevated temperatures toward the SiO2-Si interface [6, 14]. These H2 molecules represent an additional source of reacting species for passivation (reverse reactions 9, 10, 13, and 14), while H2O molecules can cause either interface trap passivation [13] or dissociation of SiH bonds [14]:

Si3 {Si x  H 2 O l Si3 {Si  OH  H x ,

(16)

Si3 {Si  H  H 2 O  h  o Si3 {Si x  H 3 O  . (17) Forward reaction (16) seems to be responsible for observing faster saturation of ǻNit (already in the second stress phase) than that of ǻNot. Namely, this reaction that involves H2O leads to passivation of interface traps only, while the other passivating reactions that involve H2 molecules (reverse reactions 9, 10, 13, and 14) can passivate both interface traps and charged oxide defects. Estimated time needed for the diffusion of H2O molecules through the gate oxide and their arrival to SiO2-Si interface (about 34 h at 125oC, 2.5 h at 175oC) [15] falls in the second stress phase, which is an additional support for the above observation. Note that the ǻNot tends to saturate over the stress time only in the third stress phase, indicating the existence of some reaction limited mechanism, which is most probably related to reverse reaction (10) [5]. Considering influences of both ǻNit and ǻNot, one would expect the VT shift to be limited by the total amount of hydrogen species available for breaking SiH bonds and the total number of potential trapping sites at the SiO2-Si interface and in the oxide [4]. As already noted, most of the above reactions can occur in either forward or reverse direction, depending on the numbers of defects and reacting species available. That is, the direction of each reaction can change over the different NBT stress phases, either leading to defect creation or to its passivation. In order to examine which of the processes prevail in each stressing phase, we have determined the activation energies for the observed NBT stress induced threshold voltage shifts and formation of both oxide trapped charge and interface

1347

traps in all three phases. The values of real activation energies, which were determined following the procedure described in [5] and differ from the experimental values found in (1), (3), and (4), are listed in Table 2. It can be noticed that the activation Table 2: Activation energies for ǻVT, 'Not, and 'Nit calculated using the data shown in Figs. 1 and 2.

Ea (eV) ǻVT 'Not 'Nit

1st phase

2nd phase

3rd phase

0.43 – 0.67 0.45 – 0.68 0.35 – 0.45

0.88 – 0.96 0.84 – 0.90 0.81 – 0.85

0.98 – 1.10 0.98 – 1.15 0.99 – 1.02

energy for each of three quantities varies within the same stressing phase. These variations are the consequence of non-smoothness and slope changes of the experimental curves shown in Figs. 1 and 2 used to determine the activation energies. However, this also indicates that various mechanisms and/or reacting species can be involved in the processes occurring within the same phase. On the other hand, it can be clearly seen that activation energies in each of three stressing phases lie in different range, suggesting that different mechanism and/or reaction may dominate in each particular phase. Looking into the data listed in Table 2, one can expect the real activation energy in the first phase to be around 0.5 eV, which is very close to the value of activation energy for diffusion of H2 molecules [5, 15]. This indicates that dominant influence on the processes occurring in this phase most probably have the direct reactions (9)-(11) and/or (13) and (14), in which the H2 molecules are released. Of course, in accordance with the discussion above, other mechanisms that lead to buildup of oxide trapped charge and interface traps (hole trapping, dissociation of SiH bonds by electric field, etc.) are probably involved as well. Reverse reactions (9), (10), (13), and (14), which lead to defect passivation, are not likely in this phase since there is still high concentration of passivated defects, but cannot be completely ruled out. Estimated activation energies in the second and third stressing phase lie near 0.9 eV and around 1 eV, respectively. The values for the second phase are close to the activation energy corresponding to the motion of hydrogen atoms [5] and ions [15] in the oxide, while those in the third phase are nearly equal to the activation energy of H2O diffusion. This indicates that dissociation processes (direct reactions 6 and 8, which further lead to reactions 9, 10, and/or 12-14) prevail in the second phase, but smaller slope

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N. Stojadinovic´ et al. / Microelectronics Reliability 45 (2005) 1343–1348

of ǻNot and ǻNit time dependencies than in the first phase suggests that the occurrence of passivation processes (reverse reactions 6, 8-10, 13, and 14) becomes more frequent. In addition, it can be noticed that estimated activation energies already in the second phase start shifting above 0.9 eV, i.e. gradually approaching the value of 1 eV. This probably indicates the beginning of H2O arrival and is in agreement with earlier estimated time needed for diffusion of H2O molecules through the gate oxide and their arrival to SiO2-Si interface. As a consequence, the interface trap passivation through the reaction (16) leads to saturation of stress induced ǻNit, which is definitely obvious in the third phase when activation energy becomes near 1 eV. On the other hand, ǻNot does not saturate in the second stressing phase, suggesting that full balance between two opposite processes (defect creation versus passivation) can be achieved only in the third phase. 4. Conclusion The NBT stressing of commercial p-channel power VDMOSFETs caused significant threshold voltage shifts, more pronounced at higher voltages and/or temperatures, which were the consequence of stress induced buildup of oxide trapped charge and interface traps. The observed power low time dependencies (tn) of threshold voltage shifts, with three distinct phases according to parameter n, were found to be mostly affected by the oxide trapped charge. Hole trapping, dissociation of SiH bonds by electric field, and various electrochemical reactions involving both oxide and interface defects and waterrelated species were shown to be the mechanisms responsible for buildup of oxide charge and interface traps. Estimated activation energies suggested that reactions in which H2 molecules were released dominated in the first, while the reactions producing hydrogen atoms and/or ions dominated in the second stress phase. The passivation process involving H2O molecules, which lead to saturation of ǻNit, became also important in this phase. Finally, the processes of defect creation and passivation were fully balanced in the third phase when ǻNot saturated as well. References [1] Stojadinovic N, Manic I, Djoric-Veljkovic S, Davidovic V, Golubovic S, Dimitrijev S. Effects of high electric field and elevated-temperature bias stressing on radiation response in power VDMOSFETs,

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