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Degradation dynamics, recovery, and characterization of negative bias temperature instability
Microelectronics Reliability 45 (2005) 99–105 www.elsevier.com/locate/microrel
Degradation dynamics, recovery, and characterization of negative bias temperature instability M. Ershov, S. Saxena, S. Minehane, P. Clifton, M. Redford *, R. Lindley, H. Karbasi, S. Graves, S. Winters PDF Solutions, 333 West San Carlos Street, San Jose, CA 95110, USA Received 2 December 2003
Abstract This article describes several deficiencies with traditional assessments of negative bias temperature instability (NBTI) in pMOS transistors and proposes methods for handling them. These effects include: (a) a decrease in the rate of degradation over time, (b) a deviation of the stress bias dependence of NBTI lifetime from simple analytical models, (c) partial dynamic recovery of apparent NBTI degradation after interruption of stress, and (d) errors well beyond what might naively be expected in lifetime extrapolation due to uncertainties in measurement and modeling of NBTI. These errors can even be several orders of magnitude. If these effects are not adequately considered in NBTI characterization, assessment, benchmarking, and optimization, they could lead excessive expense in product reliability evaluation or, worse, to unanticipated, costly field reliability problems. Ó 2004 Published by Elsevier Ltd.
1. Introduction Negative bias temperature instability (NBTI) in pMOSFETs is a major reliability concern in modern CMOS technologies [1,2] (see also references in [2]). This degradation mechanism causes an increase of threshold voltage and decrease of the drive current, which reduces the speed of degraded transistors, increases transistor mismatch and, finally, accelerates failure of logic and analog circuits. NBTI is exacerbated by further device scaling (both vertical and lateral), increase of temperature due to high dissipation power, increase of the electric field in the gate oxide, and introduction of heavy nitridation of the gate oxide. In processes with multiple gate oxides, both thin- and thick-oxide transistors suffer from NBTI. The microscopic mechanisms of NBTI are still not well understood, and optimization of process
* Corresponding author. Tel.: +1-408-280-7900; fax: +1-408280-7915. E-mail addresses: [email protected], [email protected] (M. Redford).
0026-2714/$ - see front matter Ó 2004 Published by Elsevier Ltd. doi:10.1016/j.microrel.2004.03.020
conditions to minimize NBTI is a very difficult problem. In particular, many process steps and chemical species were shown to have a strong impact on NBTI (plasma processes, back end-of-line processes, thermal budget, nitrogen, fluorine, hydrogen, etc.), but the process optimization options are often unclear or restricted. Accurate NBTI assessment is complicated by a lack of a reliable characterization procedure. Extrapolation of lifetime to nominal operating conditions based on the accelerated stress voltage measurements, and extrapolation of degradation data with respect to time introduce a significant uncertainty in estimated lifetime. Further complications arise due to dynamic recovery of NBTI reported recently in several papers [6–9]. NBTI degradation appears to be partially recoverable, which may significantly increase NBTI lifetime. On the other hand, this requires a strict control over time delays between stress interruption and monitoring measurements in characterization. In this paper, we discuss NBTI characterization and analysis techniques that we have found useful. A typical NBTI characterization procedure is described in ‘‘JEDEC/FSA Foundry Process Qualification
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Guidelines’’ document [3] as well as in many research publications––see references in [2] (it should be noted that there is no NBTI characterization method which is accepted as ‘‘standard’’ by the industry; ‘‘standard’’ NBTI method is still under development). The goal of NBTI measurements is to characterize NBTI degradation as a function of time, stress conditions (stress voltage, temperature), and device architecture (gate dimensions, gate oxide thickness, etc.), and to estimate NBTI lifetime by ‘‘extrapolation’’ of degradation data (or lifetime at stress conditions) to nominal conditions. NBTI measurements involve application of stress voltage to the gate, Vg , that is higher than the nominal supply voltage, Vdd , to accelerate degradation. All other contacts (source, drain, and substrate) are grounded during the stress. The stress is periodically interrupted and device characteristics (threshold voltage, drive current, I–V characteristics, etc.) are measured at nominal voltages to monitor device degradation under stress (see the diagram in Fig. 1). NBTI lifetime is defined as stress time when the device degradation reaches a certain limit (e.g. 10% for the saturation current Id;sat or 50 mV for the threshold voltage Vt ). If degradation does not reach this limit, the lifetime is estimated by extrapolating the degradation with respect to time using a power-law model (dId;sat ta , a ¼ 0:15–0:3 [2]) fitted to measurement data. Stress measurements are performed on different samples under different stress voltages to obtain the NBTI lifetime dependence on stress voltage and to estimate the lifetime at nominal conditions, e.g. Vg ¼ 1:1 Vdd . There are several problems with the typical NBTI characterization. First, NBTI stress is usually applied
under accelerated conditions (high stress bias and/or temperature) to speed up the degradation. This implies that NBTI testing and analysis suffers from the pitfalls common to all accelerated testing techniques [4,5]. Second, traditional NBTI analysis ignores the dynamic recovery effect reported recently by several research groups [6–9]. This effect leads to decrease of degradation after interruption of stress. NBTI characterization procedures that ignore this effect may have substantial, unknown biases, thereby producing statistical estimates that are highly misleading. Identifying and modeling these biases add significant complexity to measurement and data analysis protocols. These and other problems are discussed in more detail in the subsequent sections of this paper.
2. Experimental procedure Devices tested in this work were pMOSFETs (W ¼ 10 lm and L ¼ 0:13 lm) with 17 A thick gate oxide (EOT) fabricated in a standard 0.13 lm CMOS technology. NBTI testing involves stressing a device by a high gate voltage (at Vss ¼ Vds ¼ Vbs ¼ 0) at high temperature, and monitoring degradation as a function of time (Fig. 1). The ‘‘no stress’’ block on the schematic diagram of the measurement flow accounts for a controlled (and intrinsic) delay between stress interruption and measurements. Monitoring measurements included measurement of saturation and linear drive current, saturation and linear threshold voltage. In this work, we tested one device at each stress measurement conditions (for more accurate statistical estimate of degradation,
Pre-stress I-V characterization
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Fig. 2. Time dependence of drive current degradation. Solid lines show the power-law fit (dI=I ta , a 0:16 for low stress bias and 0.19 for high stress bias), and dashed lines show 99% confidence limits. Solid horizontal line represents a lifetime spec of 10% degradation of drive current.
M. Ershov et al. / Microelectronics Reliability 45 (2005) 99–105
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several devices should be tested at each stress bias). Fig. 2 shows the time dependence of the drive current (Id;sat ) degradation for various stress voltages. Other device characteristics showed very similar degradation behavior. We observed a strong correlation between degradation of various device characteristics, similar to what has been published in literature [2], and hence this analysis is omitted in the present paper.
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1.0 0.8 0.6 Experimental data Linear fit 99% confidence limit 2nd order polinomial fit 99% confidence limit
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3. Discussion
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3.1. Extrapolation of degradation to lifetime spec 0.0
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Fig. 3. Fitting of drive current degradation using linear and parabolic models on the double log scale with respective 99% confidence limits. These model predicts significantly different lifetimes and confidence intervals when used for extrapolation far beyond the range of the experimental data.
from a simple power-law fit. Lifetimes and their confidence limits predicted by these models diverge substantially when extrapolating far outside the range of the measured data. This point illustrates the sensitivity of the predicted lifetime to the fitting model. Of course, with excessive extrapolation, a parabola will produce nonsensical predictions. However, in some region, it could still approximate reality more accurately than the naive linear model. Fig. 4 shows that the NBTI degradation slows down on a long stress time scale. The slope of the degradation curve decreases from 0.185 for short stress times to
Lifetime
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exp. data Fitting: 10-103 s 10-105 s 104-105 s
3.2. Slow-down of degradation rate Degradation data may be fitted by any reasonable empirical model that can approximate the dynamics of degradation. Fig. 3 compares the extrapolation of degradation and corresponding confidence limits for linear and parabolic models (on the double log scale). A slightly better fit of the experimental data by a second order polynomial (R2 ¼ 0:996 vs 0.990 for linear fit) indicates the deviation of the degradation dynamics
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Log (stress time) (s)
dIdsat (%)
NBTI degradation is extrapolated with respect to time using power law fitting to obtain the lifetime at stress conditions. Power law fitting dI=I / ta (linear fitting on the double log scale) for various stress voltages is presented in Fig. 2. It should be noted that the slope of the degradation curves ‘‘a’’ is increasing from 0.16 at low stress voltages to 0.20 at high stress bias conditions. These values are close to the ‘‘classical’’ value of a ¼ 0:25 [2], but in fact the factor ‘‘a’’ is not a universal parameter, and may be dependent on stress condition, measurement conditions, and other factors. In fact, a single-point lifetime at stress conditions estimated by power-law extrapolation may be misleading. The confidence limits of this extrapolation show that the extrapolated lifetime may vary within a wide range (one order of magnitude or more at low stress bias) due to extrapolation of degradation beyond the range of the measurement data over several orders of magnitude in time. The uncertainty of the lifetime is larger for lower stress voltages due to lower degradation and longer extrapolation. Another factor significantly enhancing the range of the confidence band and increasing the lifetime uncertainty is the measurement noise, which may be very large for small stress voltage and short stress time, and which is increasing in small-area devices. Moreover, confidence limits assume the model is adequate. That assumption is often reasonable for interpolation. In many cases, however, different models can be virtually identical in the test range but can differ by several orders of magnitude with substantial extrapolation, as we now explain.
1 101
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Stress time (s) Fig. 4. Fitting of Id;sat degradation on different time intervals. Slow-down of degradation on a long time scale leads to an increase of the extrapolated lifetime with respect to the lifetime extrapolated from the short stress time measurements.
M. Ershov et al. / Microelectronics Reliability 45 (2005) 99–105
0.14 for long stress times. This effect may indicate a change in the degradation mechanism over long stress time, or a saturation (or self-limiting) behavior of degradation. The specific physical mechanisms responsible for the slow-down of degradation are not understood. This effect leads to an increase of the estimated NBTI lifetime (as compared to lifetime estimated from short stress time testing). The reduction of the power-law factor ‘‘a’’ and increase of the lifetime with duration of stress are illustrated in Fig. 5. The lifetime predicted from short stress measurements may be significantly underestimated––by an order of magnitude or more, depending on the range of extrapolation. The accuracy of the extrapolated lifetime may be increased if only the final region of the degradation curve is used for fitting. Alternatively, the statistical weight of the final stress interval may be increased by increasing the sampling size, or the number of measurement points. 3.3. Lifetime extrapolation to nominal gate voltage NBTI lifetime estimated at stress conditions (see Fig. 2) has to be extrapolated to nominal gate voltage. For safeguarding, this voltage is typically set at 10% higher than the nominal operating voltage for the CMOS technology Vdd : Vnom ¼ 1:1 Vdd . Extrapolation procedure is based on the fitting of experimental sðVg Þ data points with an analytical model, and using this model to estimate the lifetime for stress biases beyond the measurement interval. Unfortunately, there is currently no analytical model or theory reliably predicting the dependence of NBTI lifetime (or degradation) on stress
gate voltage or on electric field in the gate oxide [2]. As a result, one has to use the empirical, or phenomenological models. Two of the most frequently used analytical models for extrapolation along voltage axis are ‘‘Vg model’’ (or ‘‘E model’’): s ¼ A expðB Vg Þ and ‘‘1=Vg model’’ (‘‘1=E model’’): s ¼ A expðB=Vg Þ: Fig. 6 illustrates the extrapolation procedure using these two models. The values of the extrapolated lifetime at nominal gate bias for Vg model and 1=Vg model are summarized in Table 1. The values of the NBTI lifetime predicted by Vg and 1=Vg models are quite different. Depending on the interval of stress biases used for fitting such models, the lifetimes may be different by more than one order of magnitude. 1=Vg model always predicts longer lifetime than Vg model. The difference becomes larger if only high stress bias data points are used for fitting, i.e. when the extrapolation is performed over a large voltage interval (Vstress –Vnom ). Estimated lifetime depends significantly on the range of stress voltages used
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(b) Fig. 5. Estimated lifetime at stress conditions (Vg ¼ 2:1 V) and factor ‘‘a’’ based on different stress intervals (fitting was done over one decade of stress time interval; the upper limit of the fitting interval is used for axis x). The slope of the degradation curve (factor ‘‘a’’) is decreasing and the extrapolated lifetime is increasing with an increase of the stress time. Dashed lines (fits to data) show the trends for lifetime and factor ‘‘a’’.
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Fig. 6. Extrapolation of lifetime at stress to nominal conditions (Vg ¼ 1:1 Vdd ) using (a) Vg model and (b) 1=Vg model. The value and the uncertainty of the NBTI lifetime at nominal operating conditions depend strongly on the choice of the extrapolation model (see also Table 1). Extrapolated lifetime at nominal conditions (‘‘Tau’’) is shown by empty symbols.
M. Ershov et al. / Microelectronics Reliability 45 (2005) 99–105 Table 1 Estimated lifetime (in years) for Vg and 1=Vg models based on various voltage intervals Fitting
Vg model
1=Vg model
All Vg Low Vg High Vg
1.05E+01 3.17E+02 1.94E+00
7.73E+02 5.16E+03 6.07E+03
for fitting. In particular, the Vg model significantly underestimates the lifetime based on high stress data. It appears that the lifetime extrapolated from high stress data using Vg model represents a lower limit for the lifetime. Fitting the Vg model to low stress data leads to a much higher value of lifetime, which is probably closer to the real value of lifetime at nominal conditions. The spread of the extrapolated lifetime values may be as large as one or two orders of magnitude. To the contrary, 1=Vg model overestimates the lifetime if only high stress voltage data are used for fitting. Overall, 1=Vg model provides much better fit to the degradation data over a wide range of stress voltages, and the spread of the predicted lifetime values is much smaller than for the Vg model. However, while this statement is true for the technology used in this work, and for the selected NBTI characterization method, it may not be valid for other technologies or other testing conditions. More specifically, a significant uncertainty in estimating lifetime at stress conditions may arise due to NBTI recovery effect discussed in the next section, and due to slow-down of degradation with increasing stress time (see Section 3.2). Thus, the best fitting model for voltage dependence of lifetime may depend on the measurements conditions. The data plotted in Fig. 6 were collected with zero delay between stress interruption and measurement, and using fitting over the whole range of stress times (from 10 s to maximum stress time, which was different for different stress voltages––see Fig. 2). We would like to note that both Vg and 1=Vg models are particular cases of a more general model based on Box–Cox transformation: s ¼ A expðB Y ðVg ; kÞÞ; where 8 k < Vg 1 ; Y ðVg ; kÞ ¼ k : lnðVg Þ;
if k 6¼ 0; if k ¼ 0:
Vg and 1=Vg model correspond to cases of k ¼ 1 and 1, respectively. In principle, this more general model has more fitting parameters and can provide better fitting than Vg or 1=Vg models, but the quality of the fit does not have a physical basis. One advantage of it is that it can provide a statistical test of one model vs. the other. If, for example, a 95% confidence interval for k
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ranges from )1.2 to )0.8, it would provide substantial evidence for the 1=Vg . For the present work, we did not estimate k. In general, one has to obtain stress data for as low stress bias as possible in order to provide high confidence of the extrapolated lifetime. The smaller the difference between the stress voltage and the nominal voltage, the higher the accuracy of the extrapolated lifetime. However, getting NBTI degradation data at low stress conditions requires a very long stress time, which may not be practical. Therefore, there should be a reasonable compromise between the accuracy of the estimated lifetime and the total testing time. No specific guidelines for the selection of the minimum stress voltage and required stress time have been proposed in the literature (including this paper) so far. This issue remains an art of reliability testing. However, a practical advice regarding the choice of the fitting model would be to use several different models (Vg , 1=Vg , Box–Cox, etc.) to extrapolate the lifetime to nominal conditions, and select the shortest plausible lifetime as a conservative estimate. If the estimated lifetime does not meet the requirements, longer stress measurements may be tried at low stress voltage since lifetime may increase due to the degradation slow-down effect.
4. Dynamic recovery of NBTI degradation An important aspect of NBTI measurements is that the device degradation should be monitored at nominal conditions (e.g., Vgs ¼ Vds ¼ Vdd for Id;sat ). In order to perform monitoring measurements, the stress has to be interrupted. Until very recently, it has been commonly assumed that NBTI degradation is permanent, i.e. it stays constant after stress removal. However, this implicit assumption is not correct. To explore the effect of stress interruption, we performed a series of NBTI experiments with measurements done during and after the stress (during ‘‘no-stress’’ periods the gate was grounded). The results shown in Fig. 7(a) reveal that NBTI degradation is not constant after stress removal. NBTI degradation is decreased by up to 40% during the no-stress period. The dynamics of degradation recovery contains a fast initial transient (on the time scale of seconds) followed by a very slow nonexponential transient, which appears to saturate with time. When stress voltage is re-applied to the gate after a period of no-stress, the degradation quickly returns to its previous level and continues to increase at a slow rate (Fig. 7(b)). Transient degradation on a longer time scale for pulsed stress measurements is shown in Fig. 7(c). These results indicate that NBTI degradation contains ‘‘permanent’’ (fixed) and recoverable (‘‘relaxable’’,
M. Ershov et al. / Microelectronics Reliability 45 (2005) 99–105 8 continuous stress
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Time (s) Fig. 7. Time dependence of Id;sat degradation for repetitive application of stress voltage (Vg ¼ 2:7 V) for 100 s followed by 20 min of relaxation (Vg ¼ 0 V) period. Degradation recovers by 2% after stress removal, and quickly reaches its previous level after repetitive application of stress. Dashed line corresponds to continuous stress conditions (deviation of the continuous stress from ‘‘interrupted’’ stress during first 100 s is due to device-to-device NBTI degradation variability). Thin short dashed lines represent envelopes of degradation right after stress interruption and after recovery (these curves are offset by a constant value of 2%).
reversible) components. Permanent damage may be related to generation of fixed positive charge in the gate oxide and interface states due to the breaking of silicon bonds at the Si/SiO2 interface passivated by hydrogen. The amplitude of the reversible component appears to be independent of stress time in this experiment (see Fig. 7(c)), so it is unlikely that this component is related to fixed NBTI damage. The ratio of the magnitudes of the reversible component to the permanent degradation decreases with time, so the relative importance of relaxation becomes smaller for long stress measurements. We speculate that the reversible component of NBTI degradation may be related to recharging of traps located near silicon–oxide interface when the gate volt-
age and Fermi level are changed. These traps may be present prior to NBTI stress, and their concentration may be independent of stress. These traps may be filled by positive charge when high negative bias is applied to the gate, but this charge is de-trapped after the decrease of gate voltage. The recharging process appears to be nonexponential in time, and may involve both fast (seconds) and slow (hours and days) transient components. Even though the recharging processes may be completely reversible, they occur simultaneously with the ‘‘real’’ degradation processes due to the high applied gate voltage. Without adequate consideration of this recovery effect, NBTI degradation is not even well defined. It further suggest the need for an operational definitions for NBTI degradation and lifetime, because if we change the measurement procedures, we get different answers. Fig. 8 shows the drive current degradation measured with different delays between stress interruption and measurement. Increasing delay leads to a significant reduction of the measured degradation and to increased lifetime under stress conditions due to the relaxation of NBTI degradation. The delay between stress and measurement may be caused by communication delay in the measurement setup and by the finite time required to complete the measurements. Hence, caution must be exercised when comparing NBTI degradation data measured with different experimental setups or different measurement procedures. The comparison may be inconsistent and even wrong if different measurement equipment or different measurement techniques are compared directly. Random variability in the delay between stress and measurement is reflected in the statistical confidence
lifetime
Idsat degradation (%)
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Delay between stress and measurement: 0.4 s 3s 10 s 100 s 1 10
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Stress time (s) Fig. 8. Time dependence of ‘‘apparent’’ degradation at Vg stress ¼ 2:7 V for different delays between stress interruption and measurement. Increasing delay leads to reduction of NBTI degradation and to increase of lifetime.
M. Ershov et al. / Microelectronics Reliability 45 (2005) 99–105
intervals in plots such as Fig. 3. Inadequate modeling of NBTI recovery can generate biases that produce confidence intervals in analyses like Fig. 3 that can mislead engineers and managers into thinking their extrapolations are more accurate than they really are. Similar relaxation effects have been found in hot carrier degradation of nMOSFETs and TDDB testing [10–12]. The origin of these effects has been attributed to the recharging of energy states near the silicon/oxide interface. Although the mechanisms of NBTI and hot carrier degradation are different, the physical root causes of the relaxation of degradation in both cases may be similar. More detailed investigation of these NBTI recovery effects are needed to better understand their properties, including the dependence of recovery on stress and measurement conditions. This could contribute to more accurate and potentially less expensive NBTI characterization methods.
5. Conclusions In conclusion, we have discussed several effects that have a strong impact on NBTI characterization: (1) a declining rate of degradation over time, (2) partial dynamic recovery of NBTI degradation after interruption of stress, (3) deviation of stress voltage dependence of NBTI lifetime from simple analytical models, and (4) both statistical and nonstatistical uncertainties in extrapolated predictions of lifetimes. NBTI lifetime predictions under nominal conditions can vary two or more orders of magnitude depending on details of measurement and analysis technique. The first two of these problems could cause engineers to suspect an NBTI problem where none exists, thereby increasing unnecessarily the cost of product development. The third could contribute to the opposite error, creating an inappropriate extrapolation that could even pass reliability testing, and only appear as an extremely costly field reliability disaster. These effects should be taken into account for reliable NBTI characterization.
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Acknowledgements The authors thank George Cheroff for useful discussions and comments on the manuscript. References [1] EE Times, April 12, 2002. Reliability fears scales up as CMOS scales down; D. Lammers, Researchers debate negative-bias effects on chips, EE Times, January 5, 2004; L. Peters, NBTL A Growing Threat to Device Reliability, Semiconductor International, March 1, 2004. [2] Schroder DK, Babcock JA. Negative bias temperature instability: road to cross in deep submicron silicon semiconductor manufacturing. J Appl Phys 2003;94(l):1–18. [3] JEDEC/FSA Foundry Process Qualification Guidelines, JP-001, JEDEC Solid State Technology Association 2002. Available: (www.jedec.org). [4] Nelson W. Accelerated testing: statistical models, test plans, and data analysis. John Wiley & Sons; 1990. [5] Meeker WQ, Escobar LA. Pitfalls of accelerated testing. IEEE Trans Reliab 1998;47(2):114–8. [6] Proceedings of International Reliability Physics Symposium. Dallas: IEEE; 2003. p. 17, 178, 183, 196, 606, 610. [7] Technical Digest of IEDM. Washington: IEEE; 2003. p. 341, 345, 349. [8] Chen G, Li MF, Ang CH, Zheng JZ, Kwong DL. Dynamic NBTI of p-MOS transistors and its impact on MOSFET scaling. IEEE Electron Dev Lett 2003;23(12):734–6. [9] Ershov M, Saxena S, Karbasi H, Winters S, Minehane S, Babcock J, et al. Dynamic recovery of negative bias temperature instability in p-type metal-oxide-semiconductor field-effect transistors. Appl Phys Lett 2003;83(8):1647–9. [10] Doyle BS, Bourcerie M, Marchetaux JC, Boudou A. Relaxation effect in NMOS transistors after hot-carrier stressing. IEEE Electron Dev Lett 1987;8:234–6. [11] Bourcerie M, Doyle BS, Marchetaux J-C, Soret J-C, Boudou A. Relaxable damage in hot-carrier stressing of n-MOS transistors––oxide traps in the near interfacial region of the gate oxide. IEEE Trans Electron Dev 1990; 37:708–17. [12] Wang B, Suehle JS, Vogel EM, Bernstein JB. The effect of stress interruption and pulsed bias stress on ultra-thin gate dielectric reliability. Proceedings of International Reliability Workshop 2000. p. 74–79.
Degradation dynamics, recovery, and characterization of negative bias temperature instability M. Ershov, S. Saxena, S. Minehane, P. Clifton, M. Redford *, R. Lindley, H. Karbasi, S. Graves, S. Winters PDF Solutions, 333 West San Carlos Street, San Jose, CA 95110, USA Received 2 December 2003
Abstract This article describes several deficiencies with traditional assessments of negative bias temperature instability (NBTI) in pMOS transistors and proposes methods for handling them. These effects include: (a) a decrease in the rate of degradation over time, (b) a deviation of the stress bias dependence of NBTI lifetime from simple analytical models, (c) partial dynamic recovery of apparent NBTI degradation after interruption of stress, and (d) errors well beyond what might naively be expected in lifetime extrapolation due to uncertainties in measurement and modeling of NBTI. These errors can even be several orders of magnitude. If these effects are not adequately considered in NBTI characterization, assessment, benchmarking, and optimization, they could lead excessive expense in product reliability evaluation or, worse, to unanticipated, costly field reliability problems. Ó 2004 Published by Elsevier Ltd.
1. Introduction Negative bias temperature instability (NBTI) in pMOSFETs is a major reliability concern in modern CMOS technologies [1,2] (see also references in [2]). This degradation mechanism causes an increase of threshold voltage and decrease of the drive current, which reduces the speed of degraded transistors, increases transistor mismatch and, finally, accelerates failure of logic and analog circuits. NBTI is exacerbated by further device scaling (both vertical and lateral), increase of temperature due to high dissipation power, increase of the electric field in the gate oxide, and introduction of heavy nitridation of the gate oxide. In processes with multiple gate oxides, both thin- and thick-oxide transistors suffer from NBTI. The microscopic mechanisms of NBTI are still not well understood, and optimization of process
* Corresponding author. Tel.: +1-408-280-7900; fax: +1-408280-7915. E-mail addresses: [email protected], [email protected] (M. Redford).
0026-2714/$ - see front matter Ó 2004 Published by Elsevier Ltd. doi:10.1016/j.microrel.2004.03.020
conditions to minimize NBTI is a very difficult problem. In particular, many process steps and chemical species were shown to have a strong impact on NBTI (plasma processes, back end-of-line processes, thermal budget, nitrogen, fluorine, hydrogen, etc.), but the process optimization options are often unclear or restricted. Accurate NBTI assessment is complicated by a lack of a reliable characterization procedure. Extrapolation of lifetime to nominal operating conditions based on the accelerated stress voltage measurements, and extrapolation of degradation data with respect to time introduce a significant uncertainty in estimated lifetime. Further complications arise due to dynamic recovery of NBTI reported recently in several papers [6–9]. NBTI degradation appears to be partially recoverable, which may significantly increase NBTI lifetime. On the other hand, this requires a strict control over time delays between stress interruption and monitoring measurements in characterization. In this paper, we discuss NBTI characterization and analysis techniques that we have found useful. A typical NBTI characterization procedure is described in ‘‘JEDEC/FSA Foundry Process Qualification
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M. Ershov et al. / Microelectronics Reliability 45 (2005) 99–105
Guidelines’’ document [3] as well as in many research publications––see references in [2] (it should be noted that there is no NBTI characterization method which is accepted as ‘‘standard’’ by the industry; ‘‘standard’’ NBTI method is still under development). The goal of NBTI measurements is to characterize NBTI degradation as a function of time, stress conditions (stress voltage, temperature), and device architecture (gate dimensions, gate oxide thickness, etc.), and to estimate NBTI lifetime by ‘‘extrapolation’’ of degradation data (or lifetime at stress conditions) to nominal conditions. NBTI measurements involve application of stress voltage to the gate, Vg , that is higher than the nominal supply voltage, Vdd , to accelerate degradation. All other contacts (source, drain, and substrate) are grounded during the stress. The stress is periodically interrupted and device characteristics (threshold voltage, drive current, I–V characteristics, etc.) are measured at nominal voltages to monitor device degradation under stress (see the diagram in Fig. 1). NBTI lifetime is defined as stress time when the device degradation reaches a certain limit (e.g. 10% for the saturation current Id;sat or 50 mV for the threshold voltage Vt ). If degradation does not reach this limit, the lifetime is estimated by extrapolating the degradation with respect to time using a power-law model (dId;sat ta , a ¼ 0:15–0:3 [2]) fitted to measurement data. Stress measurements are performed on different samples under different stress voltages to obtain the NBTI lifetime dependence on stress voltage and to estimate the lifetime at nominal conditions, e.g. Vg ¼ 1:1 Vdd . There are several problems with the typical NBTI characterization. First, NBTI stress is usually applied
under accelerated conditions (high stress bias and/or temperature) to speed up the degradation. This implies that NBTI testing and analysis suffers from the pitfalls common to all accelerated testing techniques [4,5]. Second, traditional NBTI analysis ignores the dynamic recovery effect reported recently by several research groups [6–9]. This effect leads to decrease of degradation after interruption of stress. NBTI characterization procedures that ignore this effect may have substantial, unknown biases, thereby producing statistical estimates that are highly misleading. Identifying and modeling these biases add significant complexity to measurement and data analysis protocols. These and other problems are discussed in more detail in the subsequent sections of this paper.
2. Experimental procedure Devices tested in this work were pMOSFETs (W ¼ 10 lm and L ¼ 0:13 lm) with 17 A thick gate oxide (EOT) fabricated in a standard 0.13 lm CMOS technology. NBTI testing involves stressing a device by a high gate voltage (at Vss ¼ Vds ¼ Vbs ¼ 0) at high temperature, and monitoring degradation as a function of time (Fig. 1). The ‘‘no stress’’ block on the schematic diagram of the measurement flow accounts for a controlled (and intrinsic) delay between stress interruption and measurements. Monitoring measurements included measurement of saturation and linear drive current, saturation and linear threshold voltage. In this work, we tested one device at each stress measurement conditions (for more accurate statistical estimate of degradation,
Pre-stress I-V characterization
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Post-stress I-V characterization Fig. 1. Schematic diagram of NBTI testing procedure. Highlighted box corresponds to intentional or unintentional (instrumentation) delay between stress interruption and measurement.
Fig. 2. Time dependence of drive current degradation. Solid lines show the power-law fit (dI=I ta , a 0:16 for low stress bias and 0.19 for high stress bias), and dashed lines show 99% confidence limits. Solid horizontal line represents a lifetime spec of 10% degradation of drive current.
M. Ershov et al. / Microelectronics Reliability 45 (2005) 99–105
1.4
T=105°C Vg=-2.1 V
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several devices should be tested at each stress bias). Fig. 2 shows the time dependence of the drive current (Id;sat ) degradation for various stress voltages. Other device characteristics showed very similar degradation behavior. We observed a strong correlation between degradation of various device characteristics, similar to what has been published in literature [2], and hence this analysis is omitted in the present paper.
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1.0 0.8 0.6 Experimental data Linear fit 99% confidence limit 2nd order polinomial fit 99% confidence limit
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3. Discussion
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3.1. Extrapolation of degradation to lifetime spec 0.0
1
3
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4
5
7
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Fig. 3. Fitting of drive current degradation using linear and parabolic models on the double log scale with respective 99% confidence limits. These model predicts significantly different lifetimes and confidence intervals when used for extrapolation far beyond the range of the experimental data.
from a simple power-law fit. Lifetimes and their confidence limits predicted by these models diverge substantially when extrapolating far outside the range of the measured data. This point illustrates the sensitivity of the predicted lifetime to the fitting model. Of course, with excessive extrapolation, a parabola will produce nonsensical predictions. However, in some region, it could still approximate reality more accurately than the naive linear model. Fig. 4 shows that the NBTI degradation slows down on a long stress time scale. The slope of the degradation curve decreases from 0.185 for short stress times to
Lifetime
T=105°C Vg=-2.1 V 10
exp. data Fitting: 10-103 s 10-105 s 104-105 s
3.2. Slow-down of degradation rate Degradation data may be fitted by any reasonable empirical model that can approximate the dynamics of degradation. Fig. 3 compares the extrapolation of degradation and corresponding confidence limits for linear and parabolic models (on the double log scale). A slightly better fit of the experimental data by a second order polynomial (R2 ¼ 0:996 vs 0.990 for linear fit) indicates the deviation of the degradation dynamics
6
Log (stress time) (s)
dIdsat (%)
NBTI degradation is extrapolated with respect to time using power law fitting to obtain the lifetime at stress conditions. Power law fitting dI=I / ta (linear fitting on the double log scale) for various stress voltages is presented in Fig. 2. It should be noted that the slope of the degradation curves ‘‘a’’ is increasing from 0.16 at low stress voltages to 0.20 at high stress bias conditions. These values are close to the ‘‘classical’’ value of a ¼ 0:25 [2], but in fact the factor ‘‘a’’ is not a universal parameter, and may be dependent on stress condition, measurement conditions, and other factors. In fact, a single-point lifetime at stress conditions estimated by power-law extrapolation may be misleading. The confidence limits of this extrapolation show that the extrapolated lifetime may vary within a wide range (one order of magnitude or more at low stress bias) due to extrapolation of degradation beyond the range of the measurement data over several orders of magnitude in time. The uncertainty of the lifetime is larger for lower stress voltages due to lower degradation and longer extrapolation. Another factor significantly enhancing the range of the confidence band and increasing the lifetime uncertainty is the measurement noise, which may be very large for small stress voltage and short stress time, and which is increasing in small-area devices. Moreover, confidence limits assume the model is adequate. That assumption is often reasonable for interpolation. In many cases, however, different models can be virtually identical in the test range but can differ by several orders of magnitude with substantial extrapolation, as we now explain.
1 101
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Stress time (s) Fig. 4. Fitting of Id;sat degradation on different time intervals. Slow-down of degradation on a long time scale leads to an increase of the extrapolated lifetime with respect to the lifetime extrapolated from the short stress time measurements.
M. Ershov et al. / Microelectronics Reliability 45 (2005) 99–105
0.14 for long stress times. This effect may indicate a change in the degradation mechanism over long stress time, or a saturation (or self-limiting) behavior of degradation. The specific physical mechanisms responsible for the slow-down of degradation are not understood. This effect leads to an increase of the estimated NBTI lifetime (as compared to lifetime estimated from short stress time testing). The reduction of the power-law factor ‘‘a’’ and increase of the lifetime with duration of stress are illustrated in Fig. 5. The lifetime predicted from short stress measurements may be significantly underestimated––by an order of magnitude or more, depending on the range of extrapolation. The accuracy of the extrapolated lifetime may be increased if only the final region of the degradation curve is used for fitting. Alternatively, the statistical weight of the final stress interval may be increased by increasing the sampling size, or the number of measurement points. 3.3. Lifetime extrapolation to nominal gate voltage NBTI lifetime estimated at stress conditions (see Fig. 2) has to be extrapolated to nominal gate voltage. For safeguarding, this voltage is typically set at 10% higher than the nominal operating voltage for the CMOS technology Vdd : Vnom ¼ 1:1 Vdd . Extrapolation procedure is based on the fitting of experimental sðVg Þ data points with an analytical model, and using this model to estimate the lifetime for stress biases beyond the measurement interval. Unfortunately, there is currently no analytical model or theory reliably predicting the dependence of NBTI lifetime (or degradation) on stress
gate voltage or on electric field in the gate oxide [2]. As a result, one has to use the empirical, or phenomenological models. Two of the most frequently used analytical models for extrapolation along voltage axis are ‘‘Vg model’’ (or ‘‘E model’’): s ¼ A expðB Vg Þ and ‘‘1=Vg model’’ (‘‘1=E model’’): s ¼ A expðB=Vg Þ: Fig. 6 illustrates the extrapolation procedure using these two models. The values of the extrapolated lifetime at nominal gate bias for Vg model and 1=Vg model are summarized in Table 1. The values of the NBTI lifetime predicted by Vg and 1=Vg models are quite different. Depending on the interval of stress biases used for fitting such models, the lifetimes may be different by more than one order of magnitude. 1=Vg model always predicts longer lifetime than Vg model. The difference becomes larger if only high stress bias data points are used for fitting, i.e. when the extrapolation is performed over a large voltage interval (Vstress –Vnom ). Estimated lifetime depends significantly on the range of stress voltages used
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(b) Fig. 5. Estimated lifetime at stress conditions (Vg ¼ 2:1 V) and factor ‘‘a’’ based on different stress intervals (fitting was done over one decade of stress time interval; the upper limit of the fitting interval is used for axis x). The slope of the degradation curve (factor ‘‘a’’) is decreasing and the extrapolated lifetime is increasing with an increase of the stress time. Dashed lines (fits to data) show the trends for lifetime and factor ‘‘a’’.
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Fig. 6. Extrapolation of lifetime at stress to nominal conditions (Vg ¼ 1:1 Vdd ) using (a) Vg model and (b) 1=Vg model. The value and the uncertainty of the NBTI lifetime at nominal operating conditions depend strongly on the choice of the extrapolation model (see also Table 1). Extrapolated lifetime at nominal conditions (‘‘Tau’’) is shown by empty symbols.
M. Ershov et al. / Microelectronics Reliability 45 (2005) 99–105 Table 1 Estimated lifetime (in years) for Vg and 1=Vg models based on various voltage intervals Fitting
Vg model
1=Vg model
All Vg Low Vg High Vg
1.05E+01 3.17E+02 1.94E+00
7.73E+02 5.16E+03 6.07E+03
for fitting. In particular, the Vg model significantly underestimates the lifetime based on high stress data. It appears that the lifetime extrapolated from high stress data using Vg model represents a lower limit for the lifetime. Fitting the Vg model to low stress data leads to a much higher value of lifetime, which is probably closer to the real value of lifetime at nominal conditions. The spread of the extrapolated lifetime values may be as large as one or two orders of magnitude. To the contrary, 1=Vg model overestimates the lifetime if only high stress voltage data are used for fitting. Overall, 1=Vg model provides much better fit to the degradation data over a wide range of stress voltages, and the spread of the predicted lifetime values is much smaller than for the Vg model. However, while this statement is true for the technology used in this work, and for the selected NBTI characterization method, it may not be valid for other technologies or other testing conditions. More specifically, a significant uncertainty in estimating lifetime at stress conditions may arise due to NBTI recovery effect discussed in the next section, and due to slow-down of degradation with increasing stress time (see Section 3.2). Thus, the best fitting model for voltage dependence of lifetime may depend on the measurements conditions. The data plotted in Fig. 6 were collected with zero delay between stress interruption and measurement, and using fitting over the whole range of stress times (from 10 s to maximum stress time, which was different for different stress voltages––see Fig. 2). We would like to note that both Vg and 1=Vg models are particular cases of a more general model based on Box–Cox transformation: s ¼ A expðB Y ðVg ; kÞÞ; where 8 k < Vg 1 ; Y ðVg ; kÞ ¼ k : lnðVg Þ;
if k 6¼ 0; if k ¼ 0:
Vg and 1=Vg model correspond to cases of k ¼ 1 and 1, respectively. In principle, this more general model has more fitting parameters and can provide better fitting than Vg or 1=Vg models, but the quality of the fit does not have a physical basis. One advantage of it is that it can provide a statistical test of one model vs. the other. If, for example, a 95% confidence interval for k
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ranges from )1.2 to )0.8, it would provide substantial evidence for the 1=Vg . For the present work, we did not estimate k. In general, one has to obtain stress data for as low stress bias as possible in order to provide high confidence of the extrapolated lifetime. The smaller the difference between the stress voltage and the nominal voltage, the higher the accuracy of the extrapolated lifetime. However, getting NBTI degradation data at low stress conditions requires a very long stress time, which may not be practical. Therefore, there should be a reasonable compromise between the accuracy of the estimated lifetime and the total testing time. No specific guidelines for the selection of the minimum stress voltage and required stress time have been proposed in the literature (including this paper) so far. This issue remains an art of reliability testing. However, a practical advice regarding the choice of the fitting model would be to use several different models (Vg , 1=Vg , Box–Cox, etc.) to extrapolate the lifetime to nominal conditions, and select the shortest plausible lifetime as a conservative estimate. If the estimated lifetime does not meet the requirements, longer stress measurements may be tried at low stress voltage since lifetime may increase due to the degradation slow-down effect.
4. Dynamic recovery of NBTI degradation An important aspect of NBTI measurements is that the device degradation should be monitored at nominal conditions (e.g., Vgs ¼ Vds ¼ Vdd for Id;sat ). In order to perform monitoring measurements, the stress has to be interrupted. Until very recently, it has been commonly assumed that NBTI degradation is permanent, i.e. it stays constant after stress removal. However, this implicit assumption is not correct. To explore the effect of stress interruption, we performed a series of NBTI experiments with measurements done during and after the stress (during ‘‘no-stress’’ periods the gate was grounded). The results shown in Fig. 7(a) reveal that NBTI degradation is not constant after stress removal. NBTI degradation is decreased by up to 40% during the no-stress period. The dynamics of degradation recovery contains a fast initial transient (on the time scale of seconds) followed by a very slow nonexponential transient, which appears to saturate with time. When stress voltage is re-applied to the gate after a period of no-stress, the degradation quickly returns to its previous level and continues to increase at a slow rate (Fig. 7(b)). Transient degradation on a longer time scale for pulsed stress measurements is shown in Fig. 7(c). These results indicate that NBTI degradation contains ‘‘permanent’’ (fixed) and recoverable (‘‘relaxable’’,
M. Ershov et al. / Microelectronics Reliability 45 (2005) 99–105 8 continuous stress
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Time (s) Fig. 7. Time dependence of Id;sat degradation for repetitive application of stress voltage (Vg ¼ 2:7 V) for 100 s followed by 20 min of relaxation (Vg ¼ 0 V) period. Degradation recovers by 2% after stress removal, and quickly reaches its previous level after repetitive application of stress. Dashed line corresponds to continuous stress conditions (deviation of the continuous stress from ‘‘interrupted’’ stress during first 100 s is due to device-to-device NBTI degradation variability). Thin short dashed lines represent envelopes of degradation right after stress interruption and after recovery (these curves are offset by a constant value of 2%).
reversible) components. Permanent damage may be related to generation of fixed positive charge in the gate oxide and interface states due to the breaking of silicon bonds at the Si/SiO2 interface passivated by hydrogen. The amplitude of the reversible component appears to be independent of stress time in this experiment (see Fig. 7(c)), so it is unlikely that this component is related to fixed NBTI damage. The ratio of the magnitudes of the reversible component to the permanent degradation decreases with time, so the relative importance of relaxation becomes smaller for long stress measurements. We speculate that the reversible component of NBTI degradation may be related to recharging of traps located near silicon–oxide interface when the gate volt-
age and Fermi level are changed. These traps may be present prior to NBTI stress, and their concentration may be independent of stress. These traps may be filled by positive charge when high negative bias is applied to the gate, but this charge is de-trapped after the decrease of gate voltage. The recharging process appears to be nonexponential in time, and may involve both fast (seconds) and slow (hours and days) transient components. Even though the recharging processes may be completely reversible, they occur simultaneously with the ‘‘real’’ degradation processes due to the high applied gate voltage. Without adequate consideration of this recovery effect, NBTI degradation is not even well defined. It further suggest the need for an operational definitions for NBTI degradation and lifetime, because if we change the measurement procedures, we get different answers. Fig. 8 shows the drive current degradation measured with different delays between stress interruption and measurement. Increasing delay leads to a significant reduction of the measured degradation and to increased lifetime under stress conditions due to the relaxation of NBTI degradation. The delay between stress and measurement may be caused by communication delay in the measurement setup and by the finite time required to complete the measurements. Hence, caution must be exercised when comparing NBTI degradation data measured with different experimental setups or different measurement procedures. The comparison may be inconsistent and even wrong if different measurement equipment or different measurement techniques are compared directly. Random variability in the delay between stress and measurement is reflected in the statistical confidence
lifetime
Idsat degradation (%)
104
10
Delay between stress and measurement: 0.4 s 3s 10 s 100 s 1 10
100
1000
10000
Stress time (s) Fig. 8. Time dependence of ‘‘apparent’’ degradation at Vg stress ¼ 2:7 V for different delays between stress interruption and measurement. Increasing delay leads to reduction of NBTI degradation and to increase of lifetime.
M. Ershov et al. / Microelectronics Reliability 45 (2005) 99–105
intervals in plots such as Fig. 3. Inadequate modeling of NBTI recovery can generate biases that produce confidence intervals in analyses like Fig. 3 that can mislead engineers and managers into thinking their extrapolations are more accurate than they really are. Similar relaxation effects have been found in hot carrier degradation of nMOSFETs and TDDB testing [10–12]. The origin of these effects has been attributed to the recharging of energy states near the silicon/oxide interface. Although the mechanisms of NBTI and hot carrier degradation are different, the physical root causes of the relaxation of degradation in both cases may be similar. More detailed investigation of these NBTI recovery effects are needed to better understand their properties, including the dependence of recovery on stress and measurement conditions. This could contribute to more accurate and potentially less expensive NBTI characterization methods.
5. Conclusions In conclusion, we have discussed several effects that have a strong impact on NBTI characterization: (1) a declining rate of degradation over time, (2) partial dynamic recovery of NBTI degradation after interruption of stress, (3) deviation of stress voltage dependence of NBTI lifetime from simple analytical models, and (4) both statistical and nonstatistical uncertainties in extrapolated predictions of lifetimes. NBTI lifetime predictions under nominal conditions can vary two or more orders of magnitude depending on details of measurement and analysis technique. The first two of these problems could cause engineers to suspect an NBTI problem where none exists, thereby increasing unnecessarily the cost of product development. The third could contribute to the opposite error, creating an inappropriate extrapolation that could even pass reliability testing, and only appear as an extremely costly field reliability disaster. These effects should be taken into account for reliable NBTI characterization.
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Acknowledgements The authors thank George Cheroff for useful discussions and comments on the manuscript. References [1] EE Times, April 12, 2002. Reliability fears scales up as CMOS scales down; D. Lammers, Researchers debate negative-bias effects on chips, EE Times, January 5, 2004; L. Peters, NBTL A Growing Threat to Device Reliability, Semiconductor International, March 1, 2004. [2] Schroder DK, Babcock JA. Negative bias temperature instability: road to cross in deep submicron silicon semiconductor manufacturing. J Appl Phys 2003;94(l):1–18. [3] JEDEC/FSA Foundry Process Qualification Guidelines, JP-001, JEDEC Solid State Technology Association 2002. Available: (www.jedec.org). [4] Nelson W. Accelerated testing: statistical models, test plans, and data analysis. John Wiley & Sons; 1990. [5] Meeker WQ, Escobar LA. Pitfalls of accelerated testing. IEEE Trans Reliab 1998;47(2):114–8. [6] Proceedings of International Reliability Physics Symposium. Dallas: IEEE; 2003. p. 17, 178, 183, 196, 606, 610. [7] Technical Digest of IEDM. Washington: IEEE; 2003. p. 341, 345, 349. [8] Chen G, Li MF, Ang CH, Zheng JZ, Kwong DL. Dynamic NBTI of p-MOS transistors and its impact on MOSFET scaling. IEEE Electron Dev Lett 2003;23(12):734–6. [9] Ershov M, Saxena S, Karbasi H, Winters S, Minehane S, Babcock J, et al. Dynamic recovery of negative bias temperature instability in p-type metal-oxide-semiconductor field-effect transistors. Appl Phys Lett 2003;83(8):1647–9. [10] Doyle BS, Bourcerie M, Marchetaux JC, Boudou A. Relaxation effect in NMOS transistors after hot-carrier stressing. IEEE Electron Dev Lett 1987;8:234–6. [11] Bourcerie M, Doyle BS, Marchetaux J-C, Soret J-C, Boudou A. Relaxable damage in hot-carrier stressing of n-MOS transistors––oxide traps in the near interfacial region of the gate oxide. IEEE Trans Electron Dev 1990; 37:708–17. [12] Wang B, Suehle JS, Vogel EM, Bernstein JB. The effect of stress interruption and pulsed bias stress on ultra-thin gate dielectric reliability. Proceedings of International Reliability Workshop 2000. p. 74–79.